drm/i915: Semaphore MBOX update generalization

This replaces the existing MBOX update code with a more generalized
calculation for emitting mbox updates. We also create a sentinel for
doing the updates so we can more abstractly deal with the rings.

When doing MBOX updates the code must be aware of the /other/ rings.
Until now the platforms which supported semaphores had a fixed number of
rings and so it made sense for the code to be very specialized
(hardcoded).

The patch does contain a functional change, but should have no
behavioral changes.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

3 files changed, 34 insertions, 15 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6579d0c0d2f1..19f8e51d2bdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -593,6 +593,7 @@
 #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
 #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
 #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
+#define GEN6_NOSYNC 0
 #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
 #define RING_MAX_IDLE(base)     ((base)+0x54)
 #define RING_HWS_PGA(base)      ((base)+0x80)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 2d2a3622639c..5df179127e8b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -582,9 +582,16 @@ static void
 update_mboxes(struct intel_ring_buffer *ring,
               u32 mmio_offset)
 {
+/* NB: In order to be able to do semaphore MBOX updates for varying number
+ * of rings, it's easiest if we round up each individual update to a
+ * multiple of 2 (since ring updates must always be a multiple of 2)
+ * even though the actual update only requires 3 dwords.
+ */
+#define MBOX_UPDATE_DWORDS 4
         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
         intel_ring_emit(ring, mmio_offset);
         intel_ring_emit(ring, ring->outstanding_lazy_request);
+        intel_ring_emit(ring, MI_NOOP);
 }
 
 /**
@@ -599,19 +606,24 @@ update_mboxes(struct intel_ring_buffer *ring,
 static int
 gen6_add_request(struct intel_ring_buffer *ring)
 {
-        u32 mbox1_reg;
-        u32 mbox2_reg;
-        int ret;
+        struct drm_device *dev = ring->dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        struct intel_ring_buffer *useless;
+        int i, ret;
 
-        ret = intel_ring_begin(ring, 10);
+        ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
+                                      MBOX_UPDATE_DWORDS) +
+                                      4);
         if (ret)
                 return ret;
+#undef MBOX_UPDATE_DWORDS
 
-        mbox1_reg = ring->signal_mbox[0];
-        mbox2_reg = ring->signal_mbox[1];
+        for_each_ring(useless, dev_priv, i) {
+                u32 mbox_reg = ring->signal_mbox[i];
+                if (mbox_reg != GEN6_NOSYNC)
+                        update_mboxes(ring, mbox_reg);
+        }
 
-        update_mboxes(ring, mbox1_reg);
-        update_mboxes(ring, mbox2_reg);
         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
         intel_ring_emit(ring, ring->outstanding_lazy_request);
@@ -1674,8 +1686,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
-                ring->signal_mbox[0] = GEN6_VRSYNC;
-                ring->signal_mbox[1] = GEN6_BRSYNC;
+                ring->signal_mbox[RCS] = GEN6_NOSYNC;
+                ring->signal_mbox[VCS] = GEN6_VRSYNC;
+                ring->signal_mbox[BCS] = GEN6_BRSYNC;
         } else if (IS_GEN5(dev)) {
                 ring->add_request = pc_render_add_request;
                 ring->flush = gen4_render_ring_flush;
@@ -1833,8 +1846,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
-                ring->signal_mbox[0] = GEN6_RVSYNC;
-                ring->signal_mbox[1] = GEN6_BVSYNC;
+                ring->signal_mbox[RCS] = GEN6_RVSYNC;
+                ring->signal_mbox[VCS] = GEN6_NOSYNC;
+                ring->signal_mbox[BCS] = GEN6_BVSYNC;
         } else {
                 ring->mmio_base = BSD_RING_BASE;
                 ring->flush = bsd_ring_flush;
@@ -1879,8 +1893,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
-        ring->signal_mbox[0] = GEN6_RBSYNC;
-        ring->signal_mbox[1] = GEN6_VBSYNC;
+        ring->signal_mbox[RCS] = GEN6_RBSYNC;
+        ring->signal_mbox[VCS] = GEN6_VBSYNC;
+        ring->signal_mbox[BCS] = GEN6_NOSYNC;
         ring->init = init_ring_common;
 
         return intel_init_ring_buffer(dev, ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 24268fbe6855..f55d92eb6c2a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -105,9 +105,12 @@ struct  intel_ring_buffer {
         int             (*sync_to)(struct intel_ring_buffer *ring,
                                    struct intel_ring_buffer *to,
                                    u32 seqno);
+
         /* our mbox written by others */
         u32             semaphore_register[I915_NUM_RINGS];
-        u32             signal_mbox[2]; /* mboxes this ring signals to */
+        /* mboxes this ring signals to */
+        u32             signal_mbox[I915_NUM_RINGS];
+
         /**
          * List of objects currently involved in rendering from the
          * ringbuffer.