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authorYijing Wang <wangyijing@huawei.com>2013-09-05 03:55:26 -0400
committerBjorn Helgaas <bhelgaas@google.com>2013-09-23 19:30:03 -0400
commitad4d35f865408a494f0a4c02b1c7ebd3f80f5dbf (patch)
tree3fc6033c5ea9a39a385505101580f4b12742460b
parentc0102c00d8c9f4109509d9d68631a1ad47703b5f (diff)
[SCSI] csiostor: Use pcie_capability_clear_and_set_word() to simplify code
pci_is_pcie() and pcie_capability_clear_and_set_word() make it trivial to set the PCIe Completion Timeout, so just fold the csio_set_pcie_completion_timeout() function into its caller. [bhelgaas: changelog, fold csio_set_pcie_completion_timeout() into caller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@huawei.com> Cc: "James E.J. Bottomley" <JBottomley@parallels.com> Cc: Naresh Kumar Inna <naresh@chelsio.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jesper Juhl <jj@chaosbits.net>
-rw-r--r--drivers/scsi/csiostor/csio_hw.c22
-rw-r--r--include/uapi/linux/pci_regs.h3
2 files changed, 6 insertions, 19 deletions
diff --git a/drivers/scsi/csiostor/csio_hw.c b/drivers/scsi/csiostor/csio_hw.c
index 0eb35b9b3784..0eaec4748957 100644
--- a/drivers/scsi/csiostor/csio_hw.c
+++ b/drivers/scsi/csiostor/csio_hw.c
@@ -852,22 +852,6 @@ csio_hw_get_flash_params(struct csio_hw *hw)
852 return 0; 852 return 0;
853} 853}
854 854
855static void
856csio_set_pcie_completion_timeout(struct csio_hw *hw, u8 range)
857{
858 uint16_t val;
859 int pcie_cap;
860
861 if (!csio_pci_capability(hw->pdev, PCI_CAP_ID_EXP, &pcie_cap)) {
862 pci_read_config_word(hw->pdev,
863 pcie_cap + PCI_EXP_DEVCTL2, &val);
864 val &= 0xfff0;
865 val |= range ;
866 pci_write_config_word(hw->pdev,
867 pcie_cap + PCI_EXP_DEVCTL2, val);
868 }
869}
870
871/*****************************************************************************/ 855/*****************************************************************************/
872/* HW State machine assists */ 856/* HW State machine assists */
873/*****************************************************************************/ 857/*****************************************************************************/
@@ -2069,8 +2053,10 @@ csio_hw_configure(struct csio_hw *hw)
2069 goto out; 2053 goto out;
2070 } 2054 }
2071 2055
2072 /* Set pci completion timeout value to 4 seconds. */ 2056 /* Set PCIe completion timeout to 4 seconds */
2073 csio_set_pcie_completion_timeout(hw, 0xd); 2057 if (pci_is_pcie(hw->pdev))
2058 pcie_capability_clear_and_set_word(hw->pdev, PCI_EXP_DEVCTL2,
2059 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
2074 2060
2075 hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR); 2061 hw->chip_ops->chip_set_mem_win(hw, MEMWIN_CSIOSTOR);
2076 2062
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index baa7852468ef..1a38377a0032 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -558,7 +558,8 @@
558#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ 558#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
559#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ 559#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
560#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 560#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
561#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */ 561#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
562#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
562#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ 563#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
563#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ 564#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
564#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ 565#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */