ARM: AM33xx: hwmod: Add RNG module data

Add RNG hwmod data for AM33xx SoC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

1 files changed, 36 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index dd3aa31c313b..a166e5394113 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2493,6 +2493,41 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* rng */
+static struct omap_hwmod_class_sysconfig am33xx_rng_sysc = {
+        .rev_offs       = 0x1fe0,
+        .sysc_offs      = 0x1fe4,
+        .sysc_flags     = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
+        .idlemodes      = SIDLE_FORCE | SIDLE_NO,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class am33xx_rng_hwmod_class = {
+        .name           = "rng",
+        .sysc           = &am33xx_rng_sysc,
+};
+
+static struct omap_hwmod am33xx_rng_hwmod = {
+        .name           = "rng",
+        .class          = &am33xx_rng_hwmod_class,
+        .clkdm_name     = "l4ls_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "rng_fck",
+        .prcm           = {
+                .omap4  = {
+                        .clkctrl_offs   = AM33XX_CM_PER_RNG_CLKCTRL_OFFSET,
+                        .modulemode     = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+static struct omap_hwmod_ocp_if am33xx_l4_per__rng = {
+        .master         = &am33xx_l4_ls_hwmod,
+        .slave          = &am33xx_rng_hwmod,
+        .clk            = "rng_fck",
+        .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l3_main__emif,
         &am33xx_mpu__l3_main,
@@ -2572,6 +2607,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_cpgmac0__mdio,
         &am33xx_l3_main__sha0,
         &am33xx_l3_main__aes0,
+        &am33xx_l4_per__rng,
         NULL,
 };