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authorZou Nan hai <nanhai.zou@intel.com>2006-07-25 19:26:51 -0400
committerTony Luck <tony.luck@intel.com>2006-08-02 19:12:08 -0400
commitacb15c85de57d81d773b6e4184b7cb143ce83eba (patch)
tree3f8363f32e3a0bad1a7bce90915651e9d95b4711
parentc7c17423b9ea3c5559cfb480a00844f1df9eed06 (diff)
[IA64] Do not assume output registers be reservered.
We found an issue in pal.S. According to the software runtime SPEC, The caller's output registers do not need to be preserved for caller. The callee may reuse input registers for any other purpose within the procedure. in ia64_pal_call_phys_stacked, input registers are copied to output registers before call into ia64_switch_mode_phys, then used to call into PAL. This assumes output registers are preserved in ia64_switch_mode_phys, which may not be true. In this particular case, ia64_switch_mode_phys alloc a null frame , and mask off psr.i. If an interrupt comes at this small window, or an MCA comes inside the procedure, output registers maybe changed, then the pal call may got some staled input registers. This patch moves the copies from input to output after ia64_switch_mode_phys to follow the software runtime convention. It also removed some unused labels in ia64_pal_call_phys_stacked. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
-rw-r--r--arch/ia64/kernel/pal.S18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/ia64/kernel/pal.S b/arch/ia64/kernel/pal.S
index 5018c7f2e7a8..ebaf1e685f5e 100644
--- a/arch/ia64/kernel/pal.S
+++ b/arch/ia64/kernel/pal.S
@@ -217,12 +217,7 @@ GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
217 .body 217 .body
218 ;; 218 ;;
219 ld8 loc2 = [loc2] // loc2 <- entry point 219 ld8 loc2 = [loc2] // loc2 <- entry point
220 mov out0 = in0 // first argument 220 mov loc3 = psr // save psr
221 mov out1 = in1 // copy arg2
222 mov out2 = in2 // copy arg3
223 mov out3 = in3 // copy arg3
224 ;;
225 mov loc3 = psr // save psr
226 ;; 221 ;;
227 mov loc4=ar.rsc // save RSE configuration 222 mov loc4=ar.rsc // save RSE configuration
228 dep.z loc2=loc2,0,61 // convert pal entry point to physical 223 dep.z loc2=loc2,0,61 // convert pal entry point to physical
@@ -236,18 +231,23 @@ GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
236 ;; 231 ;;
237 andcm r16=loc3,r16 // removes bits to clear from psr 232 andcm r16=loc3,r16 // removes bits to clear from psr
238 br.call.sptk.many rp=ia64_switch_mode_phys 233 br.call.sptk.many rp=ia64_switch_mode_phys
239.ret6: 234
235 mov out0 = in0 // first argument
236 mov out1 = in1 // copy arg2
237 mov out2 = in2 // copy arg3
238 mov out3 = in3 // copy arg3
240 mov loc5 = r19 239 mov loc5 = r19
241 mov loc6 = r20 240 mov loc6 = r20
241
242 br.call.sptk.many rp=b7 // now make the call 242 br.call.sptk.many rp=b7 // now make the call
243.ret7: 243
244 mov ar.rsc=0 // put RSE in enforced lazy, LE mode 244 mov ar.rsc=0 // put RSE in enforced lazy, LE mode
245 mov r16=loc3 // r16= original psr 245 mov r16=loc3 // r16= original psr
246 mov r19=loc5 246 mov r19=loc5
247 mov r20=loc6 247 mov r20=loc6
248 br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode 248 br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
249 249
250.ret8: mov psr.l = loc3 // restore init PSR 250 mov psr.l = loc3 // restore init PSR
251 mov ar.pfs = loc1 251 mov ar.pfs = loc1
252 mov rp = loc0 252 mov rp = loc0
253 ;; 253 ;;