diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2013-04-28 19:44:33 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2013-06-30 23:43:42 -0400 |
commit | aca78e91581c05a4bddc5118cfea55d1cd740bd6 (patch) | |
tree | 30fa8ab6573356680bb0e8df69b23f94814601dd | |
parent | 48506d17d55911c9e814108c88a9b0747313ba89 (diff) |
drm/nve0/ce: stub interrupt handler
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/copy/nve0.c | 16 | ||||
-rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c | 1 |
2 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c index db351c99747d..30f1ef1edcc5 100644 --- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c +++ b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c | |||
@@ -67,6 +67,19 @@ nve0_copy_cclass = { | |||
67 | * PCOPY engine/subdev functions | 67 | * PCOPY engine/subdev functions |
68 | ******************************************************************************/ | 68 | ******************************************************************************/ |
69 | 69 | ||
70 | static void | ||
71 | nve0_copy_intr(struct nouveau_subdev *subdev) | ||
72 | { | ||
73 | const int ce = nv_subidx(nv_object(subdev)) - NVDEV_ENGINE_COPY0; | ||
74 | struct nve0_copy_priv *priv = (void *)subdev; | ||
75 | u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); | ||
76 | |||
77 | if (stat) { | ||
78 | nv_warn(priv, "unhandled intr 0x%08x\n", stat); | ||
79 | nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); | ||
80 | } | ||
81 | } | ||
82 | |||
70 | static int | 83 | static int |
71 | nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | 84 | nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
72 | struct nouveau_oclass *oclass, void *data, u32 size, | 85 | struct nouveau_oclass *oclass, void *data, u32 size, |
@@ -85,6 +98,7 @@ nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
85 | return ret; | 98 | return ret; |
86 | 99 | ||
87 | nv_subdev(priv)->unit = 0x00000040; | 100 | nv_subdev(priv)->unit = 0x00000040; |
101 | nv_subdev(priv)->intr = nve0_copy_intr; | ||
88 | nv_engine(priv)->cclass = &nve0_copy_cclass; | 102 | nv_engine(priv)->cclass = &nve0_copy_cclass; |
89 | nv_engine(priv)->sclass = nve0_copy_sclass; | 103 | nv_engine(priv)->sclass = nve0_copy_sclass; |
90 | return 0; | 104 | return 0; |
@@ -108,6 +122,7 @@ nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
108 | return ret; | 122 | return ret; |
109 | 123 | ||
110 | nv_subdev(priv)->unit = 0x00000080; | 124 | nv_subdev(priv)->unit = 0x00000080; |
125 | nv_subdev(priv)->intr = nve0_copy_intr; | ||
111 | nv_engine(priv)->cclass = &nve0_copy_cclass; | 126 | nv_engine(priv)->cclass = &nve0_copy_cclass; |
112 | nv_engine(priv)->sclass = nve0_copy_sclass; | 127 | nv_engine(priv)->sclass = nve0_copy_sclass; |
113 | return 0; | 128 | return 0; |
@@ -128,6 +143,7 @@ nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |||
128 | return ret; | 143 | return ret; |
129 | 144 | ||
130 | nv_subdev(priv)->unit = 0x00200000; | 145 | nv_subdev(priv)->unit = 0x00200000; |
146 | nv_subdev(priv)->intr = nve0_copy_intr; | ||
131 | nv_engine(priv)->cclass = &nve0_copy_cclass; | 147 | nv_engine(priv)->cclass = &nve0_copy_cclass; |
132 | nv_engine(priv)->sclass = nve0_copy_sclass; | 148 | nv_engine(priv)->sclass = nve0_copy_sclass; |
133 | return 0; | 149 | return 0; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c index 737bd4b682e1..c5da3babbc62 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c | |||
@@ -33,6 +33,7 @@ nvc0_mc_intr[] = { | |||
33 | { 0x00000001, NVDEV_ENGINE_PPP }, | 33 | { 0x00000001, NVDEV_ENGINE_PPP }, |
34 | { 0x00000020, NVDEV_ENGINE_COPY0 }, | 34 | { 0x00000020, NVDEV_ENGINE_COPY0 }, |
35 | { 0x00000040, NVDEV_ENGINE_COPY1 }, | 35 | { 0x00000040, NVDEV_ENGINE_COPY1 }, |
36 | { 0x00000080, NVDEV_ENGINE_COPY2 }, | ||
36 | { 0x00000100, NVDEV_ENGINE_FIFO }, | 37 | { 0x00000100, NVDEV_ENGINE_FIFO }, |
37 | { 0x00001000, NVDEV_ENGINE_GR }, | 38 | { 0x00001000, NVDEV_ENGINE_GR }, |
38 | { 0x00008000, NVDEV_ENGINE_BSP }, | 39 | { 0x00008000, NVDEV_ENGINE_BSP }, |