diff options
| author | Pranith Kumar <bobby.prani@gmail.com> | 2014-08-24 21:17:32 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-08-26 16:49:57 -0400 |
| commit | ac490f4dca9476bf8a309a2cae92ca68b8c5fca6 (patch) | |
| tree | 00b2014a350da2d5fbc2b24707a916ec0c40f5c0 | |
| parent | 270a00963cd367214e92e6deadb3bde65b49b16a (diff) | |
Documentation: this_cpu_ops.txt: Update description of this_cpu_ops
Update the description for per cpu operations to clarify use cases of
this_cpu operations and add considerations for remote access.
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
Signed-off-by: Christoph Lameter <cl@linux.com>
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| -rw-r--r-- | Documentation/this_cpu_ops.txt | 213 |
1 files changed, 171 insertions, 42 deletions
diff --git a/Documentation/this_cpu_ops.txt b/Documentation/this_cpu_ops.txt index 1a4ce7e3e05f..0ec995712176 100644 --- a/Documentation/this_cpu_ops.txt +++ b/Documentation/this_cpu_ops.txt | |||
| @@ -2,26 +2,26 @@ this_cpu operations | |||
| 2 | ------------------- | 2 | ------------------- |
| 3 | 3 | ||
| 4 | this_cpu operations are a way of optimizing access to per cpu | 4 | this_cpu operations are a way of optimizing access to per cpu |
| 5 | variables associated with the *currently* executing processor through | 5 | variables associated with the *currently* executing processor. This is |
| 6 | the use of segment registers (or a dedicated register where the cpu | 6 | done through the use of segment registers (or a dedicated register where |
| 7 | permanently stored the beginning of the per cpu area for a specific | 7 | the cpu permanently stored the beginning of the per cpu area for a |
| 8 | processor). | 8 | specific processor). |
| 9 | 9 | ||
| 10 | The this_cpu operations add a per cpu variable offset to the processor | 10 | this_cpu operations add a per cpu variable offset to the processor |
| 11 | specific percpu base and encode that operation in the instruction | 11 | specific per cpu base and encode that operation in the instruction |
| 12 | operating on the per cpu variable. | 12 | operating on the per cpu variable. |
| 13 | 13 | ||
| 14 | This means there are no atomicity issues between the calculation of | 14 | This means that there are no atomicity issues between the calculation of |
| 15 | the offset and the operation on the data. Therefore it is not | 15 | the offset and the operation on the data. Therefore it is not |
| 16 | necessary to disable preempt or interrupts to ensure that the | 16 | necessary to disable preemption or interrupts to ensure that the |
| 17 | processor is not changed between the calculation of the address and | 17 | processor is not changed between the calculation of the address and |
| 18 | the operation on the data. | 18 | the operation on the data. |
| 19 | 19 | ||
| 20 | Read-modify-write operations are of particular interest. Frequently | 20 | Read-modify-write operations are of particular interest. Frequently |
| 21 | processors have special lower latency instructions that can operate | 21 | processors have special lower latency instructions that can operate |
| 22 | without the typical synchronization overhead but still provide some | 22 | without the typical synchronization overhead, but still provide some |
| 23 | sort of relaxed atomicity guarantee. The x86 for example can execute | 23 | sort of relaxed atomicity guarantees. The x86, for example, can execute |
| 24 | RMV (Read Modify Write) instructions like inc/dec/cmpxchg without the | 24 | RMW (Read Modify Write) instructions like inc/dec/cmpxchg without the |
| 25 | lock prefix and the associated latency penalty. | 25 | lock prefix and the associated latency penalty. |
| 26 | 26 | ||
| 27 | Access to the variable without the lock prefix is not synchronized but | 27 | Access to the variable without the lock prefix is not synchronized but |
| @@ -30,6 +30,38 @@ data specific to the currently executing processor. Only the current | |||
| 30 | processor should be accessing that variable and therefore there are no | 30 | processor should be accessing that variable and therefore there are no |
| 31 | concurrency issues with other processors in the system. | 31 | concurrency issues with other processors in the system. |
| 32 | 32 | ||
| 33 | Please note that accesses by remote processors to a per cpu area are | ||
| 34 | exceptional situations and may impact performance and/or correctness | ||
| 35 | (remote write operations) of local RMW operations via this_cpu_*. | ||
| 36 | |||
| 37 | The main use of the this_cpu operations has been to optimize counter | ||
| 38 | operations. | ||
| 39 | |||
| 40 | The following this_cpu() operations with implied preemption protection | ||
| 41 | are defined. These operations can be used without worrying about | ||
| 42 | preemption and interrupts. | ||
| 43 | |||
| 44 | this_cpu_add() | ||
| 45 | this_cpu_read(pcp) | ||
| 46 | this_cpu_write(pcp, val) | ||
| 47 | this_cpu_add(pcp, val) | ||
| 48 | this_cpu_and(pcp, val) | ||
| 49 | this_cpu_or(pcp, val) | ||
| 50 | this_cpu_add_return(pcp, val) | ||
| 51 | this_cpu_xchg(pcp, nval) | ||
| 52 | this_cpu_cmpxchg(pcp, oval, nval) | ||
| 53 | this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2) | ||
| 54 | this_cpu_sub(pcp, val) | ||
| 55 | this_cpu_inc(pcp) | ||
| 56 | this_cpu_dec(pcp) | ||
| 57 | this_cpu_sub_return(pcp, val) | ||
| 58 | this_cpu_inc_return(pcp) | ||
| 59 | this_cpu_dec_return(pcp) | ||
| 60 | |||
| 61 | |||
| 62 | Inner working of this_cpu operations | ||
| 63 | ------------------------------------ | ||
| 64 | |||
| 33 | On x86 the fs: or the gs: segment registers contain the base of the | 65 | On x86 the fs: or the gs: segment registers contain the base of the |
| 34 | per cpu area. It is then possible to simply use the segment override | 66 | per cpu area. It is then possible to simply use the segment override |
| 35 | to relocate a per cpu relative address to the proper per cpu area for | 67 | to relocate a per cpu relative address to the proper per cpu area for |
| @@ -48,22 +80,21 @@ results in a single instruction | |||
| 48 | mov ax, gs:[x] | 80 | mov ax, gs:[x] |
| 49 | 81 | ||
| 50 | instead of a sequence of calculation of the address and then a fetch | 82 | instead of a sequence of calculation of the address and then a fetch |
| 51 | from that address which occurs with the percpu operations. Before | 83 | from that address which occurs with the per cpu operations. Before |
| 52 | this_cpu_ops such sequence also required preempt disable/enable to | 84 | this_cpu_ops such sequence also required preempt disable/enable to |
| 53 | prevent the kernel from moving the thread to a different processor | 85 | prevent the kernel from moving the thread to a different processor |
| 54 | while the calculation is performed. | 86 | while the calculation is performed. |
| 55 | 87 | ||
| 56 | The main use of the this_cpu operations has been to optimize counter | 88 | Consider the following this_cpu operation: |
| 57 | operations. | ||
| 58 | 89 | ||
| 59 | this_cpu_inc(x) | 90 | this_cpu_inc(x) |
| 60 | 91 | ||
| 61 | results in the following single instruction (no lock prefix!) | 92 | The above results in the following single instruction (no lock prefix!) |
| 62 | 93 | ||
| 63 | inc gs:[x] | 94 | inc gs:[x] |
| 64 | 95 | ||
| 65 | instead of the following operations required if there is no segment | 96 | instead of the following operations required if there is no segment |
| 66 | register. | 97 | register: |
| 67 | 98 | ||
| 68 | int *y; | 99 | int *y; |
| 69 | int cpu; | 100 | int cpu; |
| @@ -73,10 +104,10 @@ register. | |||
| 73 | (*y)++; | 104 | (*y)++; |
| 74 | put_cpu(); | 105 | put_cpu(); |
| 75 | 106 | ||
| 76 | Note that these operations can only be used on percpu data that is | 107 | Note that these operations can only be used on per cpu data that is |
| 77 | reserved for a specific processor. Without disabling preemption in the | 108 | reserved for a specific processor. Without disabling preemption in the |
| 78 | surrounding code this_cpu_inc() will only guarantee that one of the | 109 | surrounding code this_cpu_inc() will only guarantee that one of the |
| 79 | percpu counters is correctly incremented. However, there is no | 110 | per cpu counters is correctly incremented. However, there is no |
| 80 | guarantee that the OS will not move the process directly before or | 111 | guarantee that the OS will not move the process directly before or |
| 81 | after the this_cpu instruction is executed. In general this means that | 112 | after the this_cpu instruction is executed. In general this means that |
| 82 | the value of the individual counters for each processor are | 113 | the value of the individual counters for each processor are |
| @@ -86,9 +117,9 @@ that is of interest. | |||
| 86 | Per cpu variables are used for performance reasons. Bouncing cache | 117 | Per cpu variables are used for performance reasons. Bouncing cache |
| 87 | lines can be avoided if multiple processors concurrently go through | 118 | lines can be avoided if multiple processors concurrently go through |
| 88 | the same code paths. Since each processor has its own per cpu | 119 | the same code paths. Since each processor has its own per cpu |
| 89 | variables no concurrent cacheline updates take place. The price that | 120 | variables no concurrent cache line updates take place. The price that |
| 90 | has to be paid for this optimization is the need to add up the per cpu | 121 | has to be paid for this optimization is the need to add up the per cpu |
| 91 | counters when the value of the counter is needed. | 122 | counters when the value of a counter is needed. |
| 92 | 123 | ||
| 93 | 124 | ||
| 94 | Special operations: | 125 | Special operations: |
| @@ -100,33 +131,39 @@ Takes the offset of a per cpu variable (&x !) and returns the address | |||
| 100 | of the per cpu variable that belongs to the currently executing | 131 | of the per cpu variable that belongs to the currently executing |
| 101 | processor. this_cpu_ptr avoids multiple steps that the common | 132 | processor. this_cpu_ptr avoids multiple steps that the common |
| 102 | get_cpu/put_cpu sequence requires. No processor number is | 133 | get_cpu/put_cpu sequence requires. No processor number is |
| 103 | available. Instead the offset of the local per cpu area is simply | 134 | available. Instead, the offset of the local per cpu area is simply |
| 104 | added to the percpu offset. | 135 | added to the per cpu offset. |
| 105 | 136 | ||
| 137 | Note that this operation is usually used in a code segment when | ||
| 138 | preemption has been disabled. The pointer is then used to | ||
| 139 | access local per cpu data in a critical section. When preemption | ||
| 140 | is re-enabled this pointer is usually no longer useful since it may | ||
| 141 | no longer point to per cpu data of the current processor. | ||
| 106 | 142 | ||
| 107 | 143 | ||
| 108 | Per cpu variables and offsets | 144 | Per cpu variables and offsets |
| 109 | ----------------------------- | 145 | ----------------------------- |
| 110 | 146 | ||
| 111 | Per cpu variables have *offsets* to the beginning of the percpu | 147 | Per cpu variables have *offsets* to the beginning of the per cpu |
| 112 | area. They do not have addresses although they look like that in the | 148 | area. They do not have addresses although they look like that in the |
| 113 | code. Offsets cannot be directly dereferenced. The offset must be | 149 | code. Offsets cannot be directly dereferenced. The offset must be |
| 114 | added to a base pointer of a percpu area of a processor in order to | 150 | added to a base pointer of a per cpu area of a processor in order to |
| 115 | form a valid address. | 151 | form a valid address. |
| 116 | 152 | ||
| 117 | Therefore the use of x or &x outside of the context of per cpu | 153 | Therefore the use of x or &x outside of the context of per cpu |
| 118 | operations is invalid and will generally be treated like a NULL | 154 | operations is invalid and will generally be treated like a NULL |
| 119 | pointer dereference. | 155 | pointer dereference. |
| 120 | 156 | ||
| 121 | In the context of per cpu operations | 157 | DEFINE_PER_CPU(int, x); |
| 122 | 158 | ||
| 123 | x is a per cpu variable. Most this_cpu operations take a cpu | 159 | In the context of per cpu operations the above implies that x is a per |
| 124 | variable. | 160 | cpu variable. Most this_cpu operations take a cpu variable. |
| 125 | 161 | ||
| 126 | &x is the *offset* a per cpu variable. this_cpu_ptr() takes | 162 | int __percpu *p = &x; |
| 127 | the offset of a per cpu variable which makes this look a bit | ||
| 128 | strange. | ||
| 129 | 163 | ||
| 164 | &x and hence p is the *offset* of a per cpu variable. this_cpu_ptr() | ||
| 165 | takes the offset of a per cpu variable which makes this look a bit | ||
| 166 | strange. | ||
| 130 | 167 | ||
| 131 | 168 | ||
| 132 | Operations on a field of a per cpu structure | 169 | Operations on a field of a per cpu structure |
| @@ -152,7 +189,7 @@ If we have an offset to struct s: | |||
| 152 | 189 | ||
| 153 | struct s __percpu *ps = &p; | 190 | struct s __percpu *ps = &p; |
| 154 | 191 | ||
| 155 | z = this_cpu_dec(ps->m); | 192 | this_cpu_dec(ps->m); |
| 156 | 193 | ||
| 157 | z = this_cpu_inc_return(ps->n); | 194 | z = this_cpu_inc_return(ps->n); |
| 158 | 195 | ||
| @@ -172,29 +209,52 @@ if we do not make use of this_cpu ops later to manipulate fields: | |||
| 172 | Variants of this_cpu ops | 209 | Variants of this_cpu ops |
| 173 | ------------------------- | 210 | ------------------------- |
| 174 | 211 | ||
| 175 | this_cpu ops are interrupt safe. Some architecture do not support | 212 | this_cpu ops are interrupt safe. Some architectures do not support |
| 176 | these per cpu local operations. In that case the operation must be | 213 | these per cpu local operations. In that case the operation must be |
| 177 | replaced by code that disables interrupts, then does the operations | 214 | replaced by code that disables interrupts, then does the operations |
| 178 | that are guaranteed to be atomic and then reenable interrupts. Doing | 215 | that are guaranteed to be atomic and then re-enable interrupts. Doing |
| 179 | so is expensive. If there are other reasons why the scheduler cannot | 216 | so is expensive. If there are other reasons why the scheduler cannot |
| 180 | change the processor we are executing on then there is no reason to | 217 | change the processor we are executing on then there is no reason to |
| 181 | disable interrupts. For that purpose the __this_cpu operations are | 218 | disable interrupts. For that purpose the following __this_cpu operations |
| 182 | provided. For example. | 219 | are provided. |
| 183 | 220 | ||
| 184 | __this_cpu_inc(x); | 221 | These operations have no guarantee against concurrent interrupts or |
| 185 | 222 | preemption. If a per cpu variable is not used in an interrupt context | |
| 186 | Will increment x and will not fallback to code that disables | 223 | and the scheduler cannot preempt, then they are safe. If any interrupts |
| 224 | still occur while an operation is in progress and if the interrupt too | ||
| 225 | modifies the variable, then RMW actions can not be guaranteed to be | ||
| 226 | safe. | ||
| 227 | |||
| 228 | __this_cpu_add() | ||
| 229 | __this_cpu_read(pcp) | ||
| 230 | __this_cpu_write(pcp, val) | ||
| 231 | __this_cpu_add(pcp, val) | ||
| 232 | __this_cpu_and(pcp, val) | ||
| 233 | __this_cpu_or(pcp, val) | ||
| 234 | __this_cpu_add_return(pcp, val) | ||
| 235 | __this_cpu_xchg(pcp, nval) | ||
| 236 | __this_cpu_cmpxchg(pcp, oval, nval) | ||
| 237 | __this_cpu_cmpxchg_double(pcp1, pcp2, oval1, oval2, nval1, nval2) | ||
| 238 | __this_cpu_sub(pcp, val) | ||
| 239 | __this_cpu_inc(pcp) | ||
| 240 | __this_cpu_dec(pcp) | ||
| 241 | __this_cpu_sub_return(pcp, val) | ||
| 242 | __this_cpu_inc_return(pcp) | ||
| 243 | __this_cpu_dec_return(pcp) | ||
| 244 | |||
| 245 | |||
| 246 | Will increment x and will not fall-back to code that disables | ||
| 187 | interrupts on platforms that cannot accomplish atomicity through | 247 | interrupts on platforms that cannot accomplish atomicity through |
| 188 | address relocation and a Read-Modify-Write operation in the same | 248 | address relocation and a Read-Modify-Write operation in the same |
| 189 | instruction. | 249 | instruction. |
| 190 | 250 | ||
| 191 | 251 | ||
| 192 | |||
| 193 | &this_cpu_ptr(pp)->n vs this_cpu_ptr(&pp->n) | 252 | &this_cpu_ptr(pp)->n vs this_cpu_ptr(&pp->n) |
| 194 | -------------------------------------------- | 253 | -------------------------------------------- |
| 195 | 254 | ||
| 196 | The first operation takes the offset and forms an address and then | 255 | The first operation takes the offset and forms an address and then |
| 197 | adds the offset of the n field. | 256 | adds the offset of the n field. This may result in two add |
| 257 | instructions emitted by the compiler. | ||
| 198 | 258 | ||
| 199 | The second one first adds the two offsets and then does the | 259 | The second one first adds the two offsets and then does the |
| 200 | relocation. IMHO the second form looks cleaner and has an easier time | 260 | relocation. IMHO the second form looks cleaner and has an easier time |
| @@ -202,4 +262,73 @@ with (). The second form also is consistent with the way | |||
| 202 | this_cpu_read() and friends are used. | 262 | this_cpu_read() and friends are used. |
| 203 | 263 | ||
| 204 | 264 | ||
| 205 | Christoph Lameter, April 3rd, 2013 | 265 | Remote access to per cpu data |
| 266 | ------------------------------ | ||
| 267 | |||
| 268 | Per cpu data structures are designed to be used by one cpu exclusively. | ||
| 269 | If you use the variables as intended, this_cpu_ops() are guaranteed to | ||
| 270 | be "atomic" as no other CPU has access to these data structures. | ||
| 271 | |||
| 272 | There are special cases where you might need to access per cpu data | ||
| 273 | structures remotely. It is usually safe to do a remote read access | ||
| 274 | and that is frequently done to summarize counters. Remote write access | ||
| 275 | something which could be problematic because this_cpu ops do not | ||
| 276 | have lock semantics. A remote write may interfere with a this_cpu | ||
| 277 | RMW operation. | ||
| 278 | |||
| 279 | Remote write accesses to percpu data structures are highly discouraged | ||
| 280 | unless absolutely necessary. Please consider using an IPI to wake up | ||
| 281 | the remote CPU and perform the update to its per cpu area. | ||
| 282 | |||
| 283 | To access per-cpu data structure remotely, typically the per_cpu_ptr() | ||
| 284 | function is used: | ||
| 285 | |||
| 286 | |||
| 287 | DEFINE_PER_CPU(struct data, datap); | ||
| 288 | |||
| 289 | struct data *p = per_cpu_ptr(&datap, cpu); | ||
| 290 | |||
| 291 | This makes it explicit that we are getting ready to access a percpu | ||
| 292 | area remotely. | ||
| 293 | |||
| 294 | You can also do the following to convert the datap offset to an address | ||
| 295 | |||
| 296 | struct data *p = this_cpu_ptr(&datap); | ||
| 297 | |||
| 298 | but, passing of pointers calculated via this_cpu_ptr to other cpus is | ||
| 299 | unusual and should be avoided. | ||
| 300 | |||
| 301 | Remote access are typically only for reading the status of another cpus | ||
| 302 | per cpu data. Write accesses can cause unique problems due to the | ||
| 303 | relaxed synchronization requirements for this_cpu operations. | ||
| 304 | |||
| 305 | One example that illustrates some concerns with write operations is | ||
| 306 | the following scenario that occurs because two per cpu variables | ||
| 307 | share a cache-line but the relaxed synchronization is applied to | ||
| 308 | only one process updating the cache-line. | ||
| 309 | |||
| 310 | Consider the following example | ||
| 311 | |||
| 312 | |||
| 313 | struct test { | ||
| 314 | atomic_t a; | ||
| 315 | int b; | ||
| 316 | }; | ||
| 317 | |||
| 318 | DEFINE_PER_CPU(struct test, onecacheline); | ||
| 319 | |||
| 320 | There is some concern about what would happen if the field 'a' is updated | ||
| 321 | remotely from one processor and the local processor would use this_cpu ops | ||
| 322 | to update field b. Care should be taken that such simultaneous accesses to | ||
| 323 | data within the same cache line are avoided. Also costly synchronization | ||
| 324 | may be necessary. IPIs are generally recommended in such scenarios instead | ||
| 325 | of a remote write to the per cpu area of another processor. | ||
| 326 | |||
| 327 | Even in cases where the remote writes are rare, please bear in | ||
| 328 | mind that a remote write will evict the cache line from the processor | ||
| 329 | that most likely will access it. If the processor wakes up and finds a | ||
| 330 | missing local cache line of a per cpu area, its performance and hence | ||
| 331 | the wake up times will be affected. | ||
| 332 | |||
| 333 | Christoph Lameter, August 4th, 2014 | ||
| 334 | Pranith Kumar, Aug 2nd, 2014 | ||
