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authorMarc Zyngier <marc.zyngier@arm.com>2013-08-09 13:19:11 -0400
committerChristoffer Dall <christoffer.dall@linaro.org>2014-07-11 07:57:36 -0400
commitac3c3747e2db2f326ffc601651de544cdd33a8e9 (patch)
treee76478680edaf50dd89d7c9abe3cd476fa500d7b
parent1a9b13056dde7e3092304d6041ccc60a913042ea (diff)
arm64: KVM: move HCR_EL2.{IMO,FMO} manipulation into the vgic switch code
GICv3 requires the IMO and FMO bits to be tightly coupled with some of the interrupt controller's register switch. In order to have similar code paths, move the manipulation of these bits to the GICv2 switch code. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
-rw-r--r--arch/arm64/include/asm/kvm_arm.h5
-rw-r--r--arch/arm64/kvm/hyp.S17
2 files changed, 15 insertions, 7 deletions
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 3d6903006a8a..cc83520459ed 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -76,9 +76,10 @@
76 */ 76 */
77#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 77#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
78 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ 78 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
79 HCR_AMO | HCR_IMO | HCR_FMO | \ 79 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW)
80 HCR_SWIO | HCR_TIDCP | HCR_RW)
81#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) 80#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
81#define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO)
82
82 83
83/* Hyp System Control Register (SCTLR_EL2) bits */ 84/* Hyp System Control Register (SCTLR_EL2) bits */
84#define SCTLR_EL2_EE (1 << 25) 85#define SCTLR_EL2_EE (1 << 25)
diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
index 56df9a352a81..5945f3bdea7a 100644
--- a/arch/arm64/kvm/hyp.S
+++ b/arch/arm64/kvm/hyp.S
@@ -335,11 +335,8 @@
335.endm 335.endm
336 336
337.macro activate_traps 337.macro activate_traps
338 ldr x2, [x0, #VCPU_IRQ_LINES] 338 ldr x2, [x0, #VCPU_HCR_EL2]
339 ldr x1, [x0, #VCPU_HCR_EL2] 339 msr hcr_el2, x2
340 orr x2, x2, x1
341 msr hcr_el2, x2
342
343 ldr x2, =(CPTR_EL2_TTA) 340 ldr x2, =(CPTR_EL2_TTA)
344 msr cptr_el2, x2 341 msr cptr_el2, x2
345 342
@@ -382,12 +379,22 @@
382 ldr x24, [x24, VGIC_SAVE_FN] 379 ldr x24, [x24, VGIC_SAVE_FN]
383 kern_hyp_va x24 380 kern_hyp_va x24
384 blr x24 381 blr x24
382 mrs x24, hcr_el2
383 mov x25, #HCR_INT_OVERRIDE
384 neg x25, x25
385 and x24, x24, x25
386 msr hcr_el2, x24
385.endm 387.endm
386 388
387/* 389/*
388 * Call into the vgic backend for state restoring 390 * Call into the vgic backend for state restoring
389 */ 391 */
390.macro restore_vgic_state 392.macro restore_vgic_state
393 mrs x24, hcr_el2
394 ldr x25, [x0, #VCPU_IRQ_LINES]
395 orr x24, x24, #HCR_INT_OVERRIDE
396 orr x24, x24, x25
397 msr hcr_el2, x24
391 adr x24, __vgic_sr_vectors 398 adr x24, __vgic_sr_vectors
392 ldr x24, [x24, #VGIC_RESTORE_FN] 399 ldr x24, [x24, #VGIC_RESTORE_FN]
393 kern_hyp_va x24 400 kern_hyp_va x24