diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-09-14 16:17:50 -0400 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-09-19 09:11:54 -0400 |
| commit | abf2ba152f5aa31ee56a63b28b04a76d8def6366 (patch) | |
| tree | 34ca0fbf16578cbeab68b20fc9f4839175c3ccd9 | |
| parent | b7a3f8db07c1bca303dbf038f108dd84638bcd82 (diff) | |
ARM: iop13xx: use __iomem pointers for MMIO
ARM is moving to stricter checks on readl/write functions,
so we need to use the correct types everywhere.
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm/mach-iop13xx/include/mach/iop13xx.h | 20 | ||||
| -rw-r--r-- | arch/arm/mach-iop13xx/include/mach/memory.h | 14 | ||||
| -rw-r--r-- | arch/arm/mach-iop13xx/io.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-iop13xx/pci.c | 16 | ||||
| -rw-r--r-- | arch/arm/mach-iop13xx/pci.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-iop13xx/setup.c | 10 |
6 files changed, 36 insertions, 40 deletions
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h index e190dcd7d72d..01b41abce38c 100644 --- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h +++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h | |||
| @@ -148,18 +148,16 @@ extern unsigned long get_iop_tick_rate(void); | |||
| 148 | * IOP13XX chipset registers | 148 | * IOP13XX chipset registers |
| 149 | */ | 149 | */ |
| 150 | #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ | 150 | #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ |
| 151 | #define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ | 151 | #define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */ |
| 152 | #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 | 152 | #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 |
| 153 | #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ | 153 | #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ |
| 154 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) | 154 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) |
| 155 | #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ | 155 | #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ |
| 156 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) | 156 | IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) |
| 157 | #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ | 157 | #define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\ |
| 158 | (IOP13XX_PMMR_PHYS_MEM_BASE\ | 158 | + IOP13XX_PMMR_PHYS_MEM_BASE) |
| 159 | - IOP13XX_PMMR_VIRT_MEM_BASE)) | 159 | #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\ |
| 160 | #define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ | 160 | + IOP13XX_PMMR_VIRT_MEM_BASE) |
| 161 | (IOP13XX_PMMR_PHYS_MEM_BASE\ | ||
| 162 | - IOP13XX_PMMR_VIRT_MEM_BASE)) | ||
| 163 | #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | 161 | #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) |
| 164 | #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | 162 | #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) |
| 165 | #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) | 163 | #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) |
| @@ -169,10 +167,10 @@ extern unsigned long get_iop_tick_rate(void); | |||
| 169 | #define IOP13XX_PMMR_SIZE 0x00080000 | 167 | #define IOP13XX_PMMR_SIZE 0x00080000 |
| 170 | 168 | ||
| 171 | /*=================== Defines for Platform Devices =====================*/ | 169 | /*=================== Defines for Platform Devices =====================*/ |
| 172 | #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) | 170 | #define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) |
| 173 | #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) | 171 | #define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) |
| 174 | #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) | 172 | #define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) |
| 175 | #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) | 173 | #define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) |
| 176 | 174 | ||
| 177 | #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) | 175 | #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) |
| 178 | #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) | 176 | #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) |
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index 1afa99ef97fa..7c032d0ab24a 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h | |||
| @@ -16,12 +16,12 @@ | |||
| 16 | #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) | 16 | #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) |
| 17 | #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) | 17 | #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) |
| 18 | 18 | ||
| 19 | static inline dma_addr_t __virt_to_lbus(unsigned long x) | 19 | static inline dma_addr_t __virt_to_lbus(void __iomem *x) |
| 20 | { | 20 | { |
| 21 | return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; | 21 | return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static inline unsigned long __lbus_to_virt(dma_addr_t x) | 24 | static inline void __iomem *__lbus_to_virt(dma_addr_t x) |
| 25 | { | 25 | { |
| 26 | return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; | 26 | return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; |
| 27 | } | 27 | } |
| @@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) | |||
| 38 | 38 | ||
| 39 | #define __arch_dma_to_virt(dev, addr) \ | 39 | #define __arch_dma_to_virt(dev, addr) \ |
| 40 | ({ \ | 40 | ({ \ |
| 41 | unsigned long __virt; \ | 41 | void * __virt; \ |
| 42 | dma_addr_t __dma = addr; \ | 42 | dma_addr_t __dma = addr; \ |
| 43 | if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ | 43 | if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ |
| 44 | __virt = __lbus_to_virt(__dma); \ | 44 | __virt = __lbus_to_virt(__dma); \ |
| 45 | else \ | 45 | else \ |
| 46 | __virt = __phys_to_virt(__dma); \ | 46 | __virt = (void *)__phys_to_virt(__dma); \ |
| 47 | (void *)__virt; \ | 47 | __virt; \ |
| 48 | }) | 48 | }) |
| 49 | 49 | ||
| 50 | #define __arch_virt_to_dma(dev, addr) \ | 50 | #define __arch_virt_to_dma(dev, addr) \ |
| 51 | ({ \ | 51 | ({ \ |
| 52 | unsigned long __virt = (unsigned long)addr; \ | 52 | void * __virt = addr; \ |
| 53 | dma_addr_t __dma; \ | 53 | dma_addr_t __dma; \ |
| 54 | if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ | 54 | if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ |
| 55 | __dma = __virt_to_lbus(__virt); \ | 55 | __dma = __virt_to_lbus(__virt); \ |
| 56 | else \ | 56 | else \ |
| 57 | __dma = __virt_to_phys(__virt); \ | 57 | __dma = __virt_to_phys((unsigned long)__virt); \ |
| 58 | __dma; \ | 58 | __dma; \ |
| 59 | }) | 59 | }) |
| 60 | 60 | ||
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c index 3c364198db9c..b651af966b57 100644 --- a/arch/arm/mach-iop13xx/io.c +++ b/arch/arm/mach-iop13xx/io.c | |||
| @@ -52,14 +52,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, | |||
| 52 | if (unlikely(!iop13xx_atux_mem_base)) | 52 | if (unlikely(!iop13xx_atux_mem_base)) |
| 53 | retval = NULL; | 53 | retval = NULL; |
| 54 | else | 54 | else |
| 55 | retval = (void *)(iop13xx_atux_mem_base + | 55 | retval = (iop13xx_atux_mem_base + |
| 56 | (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); | 56 | (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); |
| 57 | break; | 57 | break; |
| 58 | case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: | 58 | case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: |
| 59 | if (unlikely(!iop13xx_atue_mem_base)) | 59 | if (unlikely(!iop13xx_atue_mem_base)) |
| 60 | retval = NULL; | 60 | retval = NULL; |
| 61 | else | 61 | else |
| 62 | retval = (void *)(iop13xx_atue_mem_base + | 62 | retval = (iop13xx_atue_mem_base + |
| 63 | (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); | 63 | (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); |
| 64 | break; | 64 | break; |
| 65 | case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: | 65 | case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: |
| @@ -74,7 +74,7 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, | |||
| 74 | retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); | 74 | retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); |
| 75 | break; | 75 | break; |
| 76 | case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: | 76 | case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: |
| 77 | retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); | 77 | retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie); |
| 78 | break; | 78 | break; |
| 79 | default: | 79 | default: |
| 80 | retval = __arm_ioremap_caller(cookie, size, mtype, | 80 | retval = __arm_ioremap_caller(cookie, size, mtype, |
| @@ -99,9 +99,9 @@ static void __iop13xx_iounmap(volatile void __iomem *addr) | |||
| 99 | goto skip; | 99 | goto skip; |
| 100 | 100 | ||
| 101 | switch ((u32) addr) { | 101 | switch ((u32) addr) { |
| 102 | case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: | 102 | case (u32)IOP13XX_PCIE_LOWER_IO_VA ... (u32)IOP13XX_PCIE_UPPER_IO_VA: |
| 103 | case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: | 103 | case (u32)IOP13XX_PCIX_LOWER_IO_VA ... (u32)IOP13XX_PCIX_UPPER_IO_VA: |
| 104 | case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: | 104 | case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA: |
| 105 | goto skip; | 105 | goto skip; |
| 106 | } | 106 | } |
| 107 | __iounmap(addr); | 107 | __iounmap(addr); |
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c index 861cb12ef436..b38e97c26dcb 100644 --- a/arch/arm/mach-iop13xx/pci.c +++ b/arch/arm/mach-iop13xx/pci.c | |||
| @@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ | |||
| 36 | u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ | 36 | u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ |
| 37 | static struct pci_bus *pci_bus_atux = 0; | 37 | static struct pci_bus *pci_bus_atux = 0; |
| 38 | static struct pci_bus *pci_bus_atue = 0; | 38 | static struct pci_bus *pci_bus_atue = 0; |
| 39 | u32 iop13xx_atue_mem_base; | 39 | void __iomem *iop13xx_atue_mem_base; |
| 40 | u32 iop13xx_atux_mem_base; | 40 | void __iomem *iop13xx_atux_mem_base; |
| 41 | size_t iop13xx_atue_mem_size; | 41 | size_t iop13xx_atue_mem_size; |
| 42 | size_t iop13xx_atux_mem_size; | 42 | size_t iop13xx_atux_mem_size; |
| 43 | 43 | ||
| @@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void) | |||
| 88 | } | 88 | } |
| 89 | 89 | ||
| 90 | if (end) { | 90 | if (end) { |
| 91 | iop13xx_atux_mem_base = | 91 | iop13xx_atux_mem_base = __arm_ioremap_pfn( |
| 92 | (u32) __arm_ioremap_pfn( | ||
| 93 | __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) | 92 | __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) |
| 94 | , 0, iop13xx_atux_mem_size, MT_DEVICE); | 93 | , 0, iop13xx_atux_mem_size, MT_DEVICE); |
| 95 | if (!iop13xx_atux_mem_base) { | 94 | if (!iop13xx_atux_mem_base) { |
| @@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void) | |||
| 99 | } | 98 | } |
| 100 | } else | 99 | } else |
| 101 | iop13xx_atux_mem_size = 0; | 100 | iop13xx_atux_mem_size = 0; |
| 102 | PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", | 101 | PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", |
| 103 | __func__, atu, iop13xx_atux_mem_size, | 102 | __func__, atu, iop13xx_atux_mem_size, |
| 104 | iop13xx_atux_mem_base); | 103 | iop13xx_atux_mem_base); |
| 105 | break; | 104 | break; |
| @@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void) | |||
| 114 | } | 113 | } |
| 115 | 114 | ||
| 116 | if (end) { | 115 | if (end) { |
| 117 | iop13xx_atue_mem_base = | 116 | iop13xx_atue_mem_base = __arm_ioremap_pfn( |
| 118 | (u32) __arm_ioremap_pfn( | ||
| 119 | __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) | 117 | __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) |
| 120 | , 0, iop13xx_atue_mem_size, MT_DEVICE); | 118 | , 0, iop13xx_atue_mem_size, MT_DEVICE); |
| 121 | if (!iop13xx_atue_mem_base) { | 119 | if (!iop13xx_atue_mem_base) { |
| @@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void) | |||
| 125 | } | 123 | } |
| 126 | } else | 124 | } else |
| 127 | iop13xx_atue_mem_size = 0; | 125 | iop13xx_atue_mem_size = 0; |
| 128 | PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", | 126 | PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", |
| 129 | __func__, atu, iop13xx_atue_mem_size, | 127 | __func__, atu, iop13xx_atue_mem_size, |
| 130 | iop13xx_atue_mem_base); | 128 | iop13xx_atue_mem_base); |
| 131 | break; | 129 | break; |
| 132 | } | 130 | } |
| 133 | 131 | ||
| 134 | printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", | 132 | printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n", |
| 135 | atu ? "ATUE" : "ATUX", | 133 | atu ? "ATUE" : "ATUX", |
| 136 | (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / | 134 | (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / |
| 137 | SZ_1M, | 135 | SZ_1M, |
diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h index c70cf5b41e31..d45a80b3080e 100644 --- a/arch/arm/mach-iop13xx/pci.h +++ b/arch/arm/mach-iop13xx/pci.h | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | #include <linux/types.h> | 1 | #include <linux/types.h> |
| 2 | 2 | ||
| 3 | extern u32 iop13xx_atue_mem_base; | 3 | extern void __iomem *iop13xx_atue_mem_base; |
| 4 | extern u32 iop13xx_atux_mem_base; | 4 | extern void __iomem *iop13xx_atux_mem_base; |
| 5 | extern size_t iop13xx_atue_mem_size; | 5 | extern size_t iop13xx_atue_mem_size; |
| 6 | extern size_t iop13xx_atux_mem_size; | 6 | extern size_t iop13xx_atux_mem_size; |
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c index daabb1fa6c2c..f5c2a229ce0a 100644 --- a/arch/arm/mach-iop13xx/setup.c +++ b/arch/arm/mach-iop13xx/setup.c | |||
| @@ -36,7 +36,7 @@ | |||
| 36 | */ | 36 | */ |
| 37 | static struct map_desc iop13xx_std_desc[] __initdata = { | 37 | static struct map_desc iop13xx_std_desc[] __initdata = { |
| 38 | { /* mem mapped registers */ | 38 | { /* mem mapped registers */ |
| 39 | .virtual = IOP13XX_PMMR_VIRT_MEM_BASE, | 39 | .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE, |
| 40 | .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), | 40 | .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), |
| 41 | .length = IOP13XX_PMMR_SIZE, | 41 | .length = IOP13XX_PMMR_SIZE, |
| 42 | .type = MT_DEVICE, | 42 | .type = MT_DEVICE, |
| @@ -81,8 +81,8 @@ static struct resource iop13xx_uart1_resources[] = { | |||
| 81 | 81 | ||
| 82 | static struct plat_serial8250_port iop13xx_uart0_data[] = { | 82 | static struct plat_serial8250_port iop13xx_uart0_data[] = { |
| 83 | { | 83 | { |
| 84 | .membase = (char*)(IOP13XX_UART0_VIRT), | 84 | .membase = IOP13XX_UART0_VIRT, |
| 85 | .mapbase = (IOP13XX_UART0_PHYS), | 85 | .mapbase = IOP13XX_UART0_PHYS, |
| 86 | .irq = IRQ_IOP13XX_UART0, | 86 | .irq = IRQ_IOP13XX_UART0, |
| 87 | .uartclk = IOP13XX_UART_XTAL, | 87 | .uartclk = IOP13XX_UART_XTAL, |
| 88 | .regshift = 2, | 88 | .regshift = 2, |
| @@ -94,8 +94,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = { | |||
| 94 | 94 | ||
| 95 | static struct plat_serial8250_port iop13xx_uart1_data[] = { | 95 | static struct plat_serial8250_port iop13xx_uart1_data[] = { |
| 96 | { | 96 | { |
| 97 | .membase = (char*)(IOP13XX_UART1_VIRT), | 97 | .membase = IOP13XX_UART1_VIRT, |
| 98 | .mapbase = (IOP13XX_UART1_PHYS), | 98 | .mapbase = IOP13XX_UART1_PHYS, |
| 99 | .irq = IRQ_IOP13XX_UART1, | 99 | .irq = IRQ_IOP13XX_UART1, |
| 100 | .uartclk = IOP13XX_UART_XTAL, | 100 | .uartclk = IOP13XX_UART_XTAL, |
| 101 | .regshift = 2, | 101 | .regshift = 2, |
