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authorBen Skeggs <bskeggs@redhat.com>2011-11-17 20:55:43 -0500
committerBen Skeggs <bskeggs@redhat.com>2011-12-21 04:01:43 -0500
commitabbd3f8e3bea4b2b0490260e67357067a2dc2039 (patch)
tree09674782d6f7444e0b9ad0091eb7101649aaa7d6
parentd4c2c99bdc8385a0e51ce4ef2df124d14b6b9c9d (diff)
drm/nv04/disp: handle dual-link spwg panels without needing quirks
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c12
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c11
2 files changed, 8 insertions, 15 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 1faa7d9ceb94..f8df37285ba7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -4304,18 +4304,6 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
4304 break; 4304 break;
4305 } 4305 }
4306 4306
4307 /* Dell Latitude D620 reports a too-high value for the dual-link
4308 * transition freq, causing us to program the panel incorrectly.
4309 *
4310 * It doesn't appear the VBIOS actually uses its transition freq
4311 * (90000kHz), instead it uses the "Number of LVDS channels" field
4312 * out of the panel ID structure (http://www.spwg.org/).
4313 *
4314 * For the moment, a quirk will do :)
4315 */
4316 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
4317 bios->fp.duallink_transition_clk = 80000;
4318
4319 /* set dual_link flag for EDID case */ 4307 /* set dual_link flag for EDID case */
4320 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4308 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4321 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); 4309 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index dff3ad594e0e..2258746016f8 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -341,10 +341,15 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
341 output_mode->clock > 165000) 341 output_mode->clock > 165000)
342 regp->fp_control |= (2 << 24); 342 regp->fp_control |= (2 << 24);
343 if (nv_encoder->dcb->type == OUTPUT_LVDS) { 343 if (nv_encoder->dcb->type == OUTPUT_LVDS) {
344 bool duallink, dummy; 344 bool duallink = false, dummy;
345 if (nv_connector->edid &&
346 nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
347 duallink = (((u8 *)nv_connector->edid)[121] == 2);
348 } else {
349 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
350 &duallink, &dummy);
351 }
345 352
346 nouveau_bios_parse_lvds_table(dev, output_mode->clock,
347 &duallink, &dummy);
348 if (duallink) 353 if (duallink)
349 regp->fp_control |= (8 << 28); 354 regp->fp_control |= (8 << 28);
350 } else 355 } else