diff options
| author | Heiko Carstens <heiko.carstens@de.ibm.com> | 2013-02-07 19:19:11 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-02-08 14:22:05 -0500 |
| commit | ab54ee80aa7585f9666ff4dd665441d7ce41f1e8 (patch) | |
| tree | 163b8839044b453877166608f03f904af2c813c1 | |
| parent | 9c79330d930b5774aed8eb323daebecedce2e245 (diff) | |
atm/iphase: rename fregt_t -> ffreg_t
We have conflicting type qualifiers for "freg_t" in s390's ptrace.h and the
iphase atm device driver, which causes the compile error below.
Unfortunately the s390 typedef can't be renamed, since it's a user visible api,
nor can I change the include order in s390 code to avoid the conflict.
So simply rename the iphase typedef to a new name. Fixes this compile error:
In file included from drivers/atm/iphase.c:66:0:
drivers/atm/iphase.h:639:25: error: conflicting type qualifiers for 'freg_t'
In file included from next/arch/s390/include/asm/ptrace.h:9:0,
from next/arch/s390/include/asm/lowcore.h:12,
from next/arch/s390/include/asm/thread_info.h:30,
from include/linux/thread_info.h:54,
from include/linux/preempt.h:9,
from include/linux/spinlock.h:50,
from include/linux/seqlock.h:29,
from include/linux/time.h:5,
from include/linux/stat.h:18,
from include/linux/module.h:10,
from drivers/atm/iphase.c:43:
next/arch/s390/include/uapi/asm/ptrace.h:197:3: note: previous declaration of 'freg_t' was here
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Acked-by: chas williams - CONTRACTOR <chas@cmf.nrl.navy.mil>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/atm/iphase.h | 146 |
1 files changed, 73 insertions, 73 deletions
diff --git a/drivers/atm/iphase.h b/drivers/atm/iphase.h index 6a0955e6d4fc..53ecac5a2161 100644 --- a/drivers/atm/iphase.h +++ b/drivers/atm/iphase.h | |||
| @@ -636,82 +636,82 @@ struct rx_buf_desc { | |||
| 636 | #define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE | 636 | #define SEG_BASE IPHASE5575_FRAG_CONTROL_REG_BASE |
| 637 | #define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE | 637 | #define REASS_BASE IPHASE5575_REASS_CONTROL_REG_BASE |
| 638 | 638 | ||
| 639 | typedef volatile u_int freg_t; | 639 | typedef volatile u_int ffreg_t; |
| 640 | typedef u_int rreg_t; | 640 | typedef u_int rreg_t; |
| 641 | 641 | ||
| 642 | typedef struct _ffredn_t { | 642 | typedef struct _ffredn_t { |
| 643 | freg_t idlehead_high; /* Idle cell header (high) */ | 643 | ffreg_t idlehead_high; /* Idle cell header (high) */ |
| 644 | freg_t idlehead_low; /* Idle cell header (low) */ | 644 | ffreg_t idlehead_low; /* Idle cell header (low) */ |
| 645 | freg_t maxrate; /* Maximum rate */ | 645 | ffreg_t maxrate; /* Maximum rate */ |
| 646 | freg_t stparms; /* Traffic Management Parameters */ | 646 | ffreg_t stparms; /* Traffic Management Parameters */ |
| 647 | freg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */ | 647 | ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */ |
| 648 | freg_t rm_type; /* */ | 648 | ffreg_t rm_type; /* */ |
| 649 | u_int filler5[0x17 - 0x06]; | 649 | u_int filler5[0x17 - 0x06]; |
| 650 | freg_t cmd_reg; /* Command register */ | 650 | ffreg_t cmd_reg; /* Command register */ |
| 651 | u_int filler18[0x20 - 0x18]; | 651 | u_int filler18[0x20 - 0x18]; |
| 652 | freg_t cbr_base; /* CBR Pointer Base */ | 652 | ffreg_t cbr_base; /* CBR Pointer Base */ |
| 653 | freg_t vbr_base; /* VBR Pointer Base */ | 653 | ffreg_t vbr_base; /* VBR Pointer Base */ |
| 654 | freg_t abr_base; /* ABR Pointer Base */ | 654 | ffreg_t abr_base; /* ABR Pointer Base */ |
| 655 | freg_t ubr_base; /* UBR Pointer Base */ | 655 | ffreg_t ubr_base; /* UBR Pointer Base */ |
| 656 | u_int filler24; | 656 | u_int filler24; |
| 657 | freg_t vbrwq_base; /* VBR Wait Queue Base */ | 657 | ffreg_t vbrwq_base; /* VBR Wait Queue Base */ |
| 658 | freg_t abrwq_base; /* ABR Wait Queue Base */ | 658 | ffreg_t abrwq_base; /* ABR Wait Queue Base */ |
| 659 | freg_t ubrwq_base; /* UBR Wait Queue Base */ | 659 | ffreg_t ubrwq_base; /* UBR Wait Queue Base */ |
| 660 | freg_t vct_base; /* Main VC Table Base */ | 660 | ffreg_t vct_base; /* Main VC Table Base */ |
| 661 | freg_t vcte_base; /* Extended Main VC Table Base */ | 661 | ffreg_t vcte_base; /* Extended Main VC Table Base */ |
| 662 | u_int filler2a[0x2C - 0x2A]; | 662 | u_int filler2a[0x2C - 0x2A]; |
| 663 | freg_t cbr_tab_beg; /* CBR Table Begin */ | 663 | ffreg_t cbr_tab_beg; /* CBR Table Begin */ |
| 664 | freg_t cbr_tab_end; /* CBR Table End */ | 664 | ffreg_t cbr_tab_end; /* CBR Table End */ |
| 665 | freg_t cbr_pointer; /* CBR Pointer */ | 665 | ffreg_t cbr_pointer; /* CBR Pointer */ |
| 666 | u_int filler2f[0x30 - 0x2F]; | 666 | u_int filler2f[0x30 - 0x2F]; |
| 667 | freg_t prq_st_adr; /* Packet Ready Queue Start Address */ | 667 | ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */ |
| 668 | freg_t prq_ed_adr; /* Packet Ready Queue End Address */ | 668 | ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */ |
| 669 | freg_t prq_rd_ptr; /* Packet Ready Queue read pointer */ | 669 | ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */ |
| 670 | freg_t prq_wr_ptr; /* Packet Ready Queue write pointer */ | 670 | ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */ |
| 671 | freg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/ | 671 | ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/ |
| 672 | freg_t tcq_ed_adr; /* Transmit Complete Queue End Address */ | 672 | ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */ |
| 673 | freg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */ | 673 | ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */ |
| 674 | freg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/ | 674 | ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/ |
| 675 | u_int filler38[0x40 - 0x38]; | 675 | u_int filler38[0x40 - 0x38]; |
| 676 | freg_t queue_base; /* Base address for PRQ and TCQ */ | 676 | ffreg_t queue_base; /* Base address for PRQ and TCQ */ |
| 677 | freg_t desc_base; /* Base address of descriptor table */ | 677 | ffreg_t desc_base; /* Base address of descriptor table */ |
| 678 | u_int filler42[0x45 - 0x42]; | 678 | u_int filler42[0x45 - 0x42]; |
| 679 | freg_t mode_reg_0; /* Mode register 0 */ | 679 | ffreg_t mode_reg_0; /* Mode register 0 */ |
| 680 | freg_t mode_reg_1; /* Mode register 1 */ | 680 | ffreg_t mode_reg_1; /* Mode register 1 */ |
| 681 | freg_t intr_status_reg;/* Interrupt Status register */ | 681 | ffreg_t intr_status_reg;/* Interrupt Status register */ |
| 682 | freg_t mask_reg; /* Mask Register */ | 682 | ffreg_t mask_reg; /* Mask Register */ |
| 683 | freg_t cell_ctr_high1; /* Total cell transfer count (high) */ | 683 | ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */ |
| 684 | freg_t cell_ctr_lo1; /* Total cell transfer count (low) */ | 684 | ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */ |
| 685 | freg_t state_reg; /* Status register */ | 685 | ffreg_t state_reg; /* Status register */ |
| 686 | u_int filler4c[0x58 - 0x4c]; | 686 | u_int filler4c[0x58 - 0x4c]; |
| 687 | freg_t curr_desc_num; /* Contains the current descriptor num */ | 687 | ffreg_t curr_desc_num; /* Contains the current descriptor num */ |
| 688 | freg_t next_desc; /* Next descriptor */ | 688 | ffreg_t next_desc; /* Next descriptor */ |
| 689 | freg_t next_vc; /* Next VC */ | 689 | ffreg_t next_vc; /* Next VC */ |
| 690 | u_int filler5b[0x5d - 0x5b]; | 690 | u_int filler5b[0x5d - 0x5b]; |
| 691 | freg_t present_slot_cnt;/* Present slot count */ | 691 | ffreg_t present_slot_cnt;/* Present slot count */ |
| 692 | u_int filler5e[0x6a - 0x5e]; | 692 | u_int filler5e[0x6a - 0x5e]; |
| 693 | freg_t new_desc_num; /* New descriptor number */ | 693 | ffreg_t new_desc_num; /* New descriptor number */ |
| 694 | freg_t new_vc; /* New VC */ | 694 | ffreg_t new_vc; /* New VC */ |
| 695 | freg_t sched_tbl_ptr; /* Schedule table pointer */ | 695 | ffreg_t sched_tbl_ptr; /* Schedule table pointer */ |
| 696 | freg_t vbrwq_wptr; /* VBR wait queue write pointer */ | 696 | ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */ |
| 697 | freg_t vbrwq_rptr; /* VBR wait queue read pointer */ | 697 | ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */ |
| 698 | freg_t abrwq_wptr; /* ABR wait queue write pointer */ | 698 | ffreg_t abrwq_wptr; /* ABR wait queue write pointer */ |
| 699 | freg_t abrwq_rptr; /* ABR wait queue read pointer */ | 699 | ffreg_t abrwq_rptr; /* ABR wait queue read pointer */ |
| 700 | freg_t ubrwq_wptr; /* UBR wait queue write pointer */ | 700 | ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */ |
| 701 | freg_t ubrwq_rptr; /* UBR wait queue read pointer */ | 701 | ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */ |
| 702 | freg_t cbr_vc; /* CBR VC */ | 702 | ffreg_t cbr_vc; /* CBR VC */ |
| 703 | freg_t vbr_sb_vc; /* VBR SB VC */ | 703 | ffreg_t vbr_sb_vc; /* VBR SB VC */ |
| 704 | freg_t abr_sb_vc; /* ABR SB VC */ | 704 | ffreg_t abr_sb_vc; /* ABR SB VC */ |
| 705 | freg_t ubr_sb_vc; /* UBR SB VC */ | 705 | ffreg_t ubr_sb_vc; /* UBR SB VC */ |
| 706 | freg_t vbr_next_link; /* VBR next link */ | 706 | ffreg_t vbr_next_link; /* VBR next link */ |
| 707 | freg_t abr_next_link; /* ABR next link */ | 707 | ffreg_t abr_next_link; /* ABR next link */ |
| 708 | freg_t ubr_next_link; /* UBR next link */ | 708 | ffreg_t ubr_next_link; /* UBR next link */ |
| 709 | u_int filler7a[0x7c-0x7a]; | 709 | u_int filler7a[0x7c-0x7a]; |
| 710 | freg_t out_rate_head; /* Out of rate head */ | 710 | ffreg_t out_rate_head; /* Out of rate head */ |
| 711 | u_int filler7d[0xca-0x7d]; /* pad out to full address space */ | 711 | u_int filler7d[0xca-0x7d]; /* pad out to full address space */ |
| 712 | freg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */ | 712 | ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */ |
| 713 | freg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */ | 713 | ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */ |
| 714 | u_int fillercc[0x100-0xcc]; /* pad out to full address space */ | 714 | u_int fillercc[0x100-0xcc]; /* pad out to full address space */ |
| 715 | } ffredn_t; | 715 | } ffredn_t; |
| 716 | 716 | ||
| 717 | typedef struct _rfredn_t { | 717 | typedef struct _rfredn_t { |