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authorBen Hutchings <bhutchings@solarflare.com>2012-09-12 20:11:31 -0400
committerBen Hutchings <bhutchings@solarflare.com>2013-08-21 11:35:20 -0400
commitab0115fc7dc429300fc6b728ab04ee832fbb945d (patch)
tree5a646c3db604ee6bab45cfdcafaa8785961e1944
parent9dd3a13b885fef7dca0d2f27517a50b5fb5097c6 (diff)
sfc: Move more Falcon-specific code and definitions into falcon.c
In particular, fold in the whole of falcon_xmac.c. Drop some entirely unused definitions. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Diffstat
-rw-r--r--drivers/net/ethernet/sfc/Makefile2
-rw-r--r--drivers/net/ethernet/sfc/falcon.c537
-rw-r--r--drivers/net/ethernet/sfc/falcon_xmac.c362
-rw-r--r--drivers/net/ethernet/sfc/nic.h43
-rw-r--r--drivers/net/ethernet/sfc/regs.h260
5 files changed, 538 insertions, 666 deletions
diff --git a/drivers/net/ethernet/sfc/Makefile b/drivers/net/ethernet/sfc/Makefile
index 945bf06e69ef..84f9c9642b7a 100644
--- a/drivers/net/ethernet/sfc/Makefile
+++ b/drivers/net/ethernet/sfc/Makefile
@@ -1,5 +1,5 @@
1sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \ 1sfc-y += efx.o nic.o falcon.o siena.o tx.o rx.o filter.o \
2 falcon_xmac.o mcdi_mac.o \ 2 mcdi_mac.o \
3 selftest.o ethtool.o qt202x_phy.o mdio_10g.o \ 3 selftest.o ethtool.o qt202x_phy.o mdio_10g.o \
4 tenxpress.o txc43128_phy.o falcon_boards.o \ 4 tenxpress.o txc43128_phy.o falcon_boards.o \
5 mcdi.o mcdi_phy.o mcdi_mon.o ptp.o 5 mcdi.o mcdi_phy.o mcdi_mon.o ptp.o
diff --git a/drivers/net/ethernet/sfc/falcon.c b/drivers/net/ethernet/sfc/falcon.c
index 6b6ac6d174aa..522850036c9b 100644
--- a/drivers/net/ethernet/sfc/falcon.c
+++ b/drivers/net/ethernet/sfc/falcon.c
@@ -26,10 +26,200 @@
26#include "phy.h" 26#include "phy.h"
27#include "workarounds.h" 27#include "workarounds.h"
28#include "selftest.h" 28#include "selftest.h"
29#include "mdio_10g.h"
29 30
30/* Hardware control for SFC4000 (aka Falcon). */ 31/* Hardware control for SFC4000 (aka Falcon). */
31 32
33/**************************************************************************
34 *
35 * MAC stats DMA format
36 *
37 **************************************************************************
38 */
39
40#define FALCON_MAC_STATS_SIZE 0x100
41
42#define XgRxOctets_offset 0x0
43#define XgRxOctets_WIDTH 48
44#define XgRxOctetsOK_offset 0x8
45#define XgRxOctetsOK_WIDTH 48
46#define XgRxPkts_offset 0x10
47#define XgRxPkts_WIDTH 32
48#define XgRxPktsOK_offset 0x14
49#define XgRxPktsOK_WIDTH 32
50#define XgRxBroadcastPkts_offset 0x18
51#define XgRxBroadcastPkts_WIDTH 32
52#define XgRxMulticastPkts_offset 0x1C
53#define XgRxMulticastPkts_WIDTH 32
54#define XgRxUnicastPkts_offset 0x20
55#define XgRxUnicastPkts_WIDTH 32
56#define XgRxUndersizePkts_offset 0x24
57#define XgRxUndersizePkts_WIDTH 32
58#define XgRxOversizePkts_offset 0x28
59#define XgRxOversizePkts_WIDTH 32
60#define XgRxJabberPkts_offset 0x2C
61#define XgRxJabberPkts_WIDTH 32
62#define XgRxUndersizeFCSerrorPkts_offset 0x30
63#define XgRxUndersizeFCSerrorPkts_WIDTH 32
64#define XgRxDropEvents_offset 0x34
65#define XgRxDropEvents_WIDTH 32
66#define XgRxFCSerrorPkts_offset 0x38
67#define XgRxFCSerrorPkts_WIDTH 32
68#define XgRxAlignError_offset 0x3C
69#define XgRxAlignError_WIDTH 32
70#define XgRxSymbolError_offset 0x40
71#define XgRxSymbolError_WIDTH 32
72#define XgRxInternalMACError_offset 0x44
73#define XgRxInternalMACError_WIDTH 32
74#define XgRxControlPkts_offset 0x48
75#define XgRxControlPkts_WIDTH 32
76#define XgRxPausePkts_offset 0x4C
77#define XgRxPausePkts_WIDTH 32
78#define XgRxPkts64Octets_offset 0x50
79#define XgRxPkts64Octets_WIDTH 32
80#define XgRxPkts65to127Octets_offset 0x54
81#define XgRxPkts65to127Octets_WIDTH 32
82#define XgRxPkts128to255Octets_offset 0x58
83#define XgRxPkts128to255Octets_WIDTH 32
84#define XgRxPkts256to511Octets_offset 0x5C
85#define XgRxPkts256to511Octets_WIDTH 32
86#define XgRxPkts512to1023Octets_offset 0x60
87#define XgRxPkts512to1023Octets_WIDTH 32
88#define XgRxPkts1024to15xxOctets_offset 0x64
89#define XgRxPkts1024to15xxOctets_WIDTH 32
90#define XgRxPkts15xxtoMaxOctets_offset 0x68
91#define XgRxPkts15xxtoMaxOctets_WIDTH 32
92#define XgRxLengthError_offset 0x6C
93#define XgRxLengthError_WIDTH 32
94#define XgTxPkts_offset 0x80
95#define XgTxPkts_WIDTH 32
96#define XgTxOctets_offset 0x88
97#define XgTxOctets_WIDTH 48
98#define XgTxMulticastPkts_offset 0x90
99#define XgTxMulticastPkts_WIDTH 32
100#define XgTxBroadcastPkts_offset 0x94
101#define XgTxBroadcastPkts_WIDTH 32
102#define XgTxUnicastPkts_offset 0x98
103#define XgTxUnicastPkts_WIDTH 32
104#define XgTxControlPkts_offset 0x9C
105#define XgTxControlPkts_WIDTH 32
106#define XgTxPausePkts_offset 0xA0
107#define XgTxPausePkts_WIDTH 32
108#define XgTxPkts64Octets_offset 0xA4
109#define XgTxPkts64Octets_WIDTH 32
110#define XgTxPkts65to127Octets_offset 0xA8
111#define XgTxPkts65to127Octets_WIDTH 32
112#define XgTxPkts128to255Octets_offset 0xAC
113#define XgTxPkts128to255Octets_WIDTH 32
114#define XgTxPkts256to511Octets_offset 0xB0
115#define XgTxPkts256to511Octets_WIDTH 32
116#define XgTxPkts512to1023Octets_offset 0xB4
117#define XgTxPkts512to1023Octets_WIDTH 32
118#define XgTxPkts1024to15xxOctets_offset 0xB8
119#define XgTxPkts1024to15xxOctets_WIDTH 32
120#define XgTxPkts1519toMaxOctets_offset 0xBC
121#define XgTxPkts1519toMaxOctets_WIDTH 32
122#define XgTxUndersizePkts_offset 0xC0
123#define XgTxUndersizePkts_WIDTH 32
124#define XgTxOversizePkts_offset 0xC4
125#define XgTxOversizePkts_WIDTH 32
126#define XgTxNonTcpUdpPkt_offset 0xC8
127#define XgTxNonTcpUdpPkt_WIDTH 16
128#define XgTxMacSrcErrPkt_offset 0xCC
129#define XgTxMacSrcErrPkt_WIDTH 16
130#define XgTxIpSrcErrPkt_offset 0xD0
131#define XgTxIpSrcErrPkt_WIDTH 16
132#define XgDmaDone_offset 0xD4
133#define XgDmaDone_WIDTH 32
134
135#define FALCON_STATS_NOT_DONE 0x00000000
136#define FALCON_STATS_DONE 0xffffffff
137
138#define FALCON_STAT_OFFSET(falcon_stat) EFX_VAL(falcon_stat, offset)
139#define FALCON_STAT_WIDTH(falcon_stat) EFX_VAL(falcon_stat, WIDTH)
140
141/* Retrieve statistic from statistics block */
142#define FALCON_STAT(efx, falcon_stat, efx_stat) do { \
143 if (FALCON_STAT_WIDTH(falcon_stat) == 16) \
144 (efx)->mac_stats.efx_stat += le16_to_cpu( \
145 *((__force __le16 *) \
146 (efx->stats_buffer.addr + \
147 FALCON_STAT_OFFSET(falcon_stat)))); \
148 else if (FALCON_STAT_WIDTH(falcon_stat) == 32) \
149 (efx)->mac_stats.efx_stat += le32_to_cpu( \
150 *((__force __le32 *) \
151 (efx->stats_buffer.addr + \
152 FALCON_STAT_OFFSET(falcon_stat)))); \
153 else \
154 (efx)->mac_stats.efx_stat += le64_to_cpu( \
155 *((__force __le64 *) \
156 (efx->stats_buffer.addr + \
157 FALCON_STAT_OFFSET(falcon_stat)))); \
158 } while (0)
159
160/**************************************************************************
161 *
162 * Non-volatile configuration
163 *
164 **************************************************************************
165 */
166
167/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
168struct falcon_nvconfig_board_v2 {
169 __le16 nports;
170 u8 port0_phy_addr;
171 u8 port0_phy_type;
172 u8 port1_phy_addr;
173 u8 port1_phy_type;
174 __le16 asic_sub_revision;
175 __le16 board_revision;
176} __packed;
177
178/* Board configuration v3 extra information */
179struct falcon_nvconfig_board_v3 {
180 __le32 spi_device_type[2];
181} __packed;
182
183/* Bit numbers for spi_device_type */
184#define SPI_DEV_TYPE_SIZE_LBN 0
185#define SPI_DEV_TYPE_SIZE_WIDTH 5
186#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
187#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
188#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
189#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
190#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
191#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
192#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
193#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
194#define SPI_DEV_TYPE_FIELD(type, field) \
195 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
196
197#define FALCON_NVCONFIG_OFFSET 0x300
198
199#define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
200struct falcon_nvconfig {
201 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
202 u8 mac_address[2][8]; /* 0x310 */
203 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
204 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
205 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
206 efx_oword_t hw_init_reg; /* 0x350 */
207 efx_oword_t nic_stat_reg; /* 0x360 */
208 efx_oword_t glb_ctl_reg; /* 0x370 */
209 efx_oword_t srm_cfg_reg; /* 0x380 */
210 efx_oword_t spare_reg; /* 0x390 */
211 __le16 board_magic_num; /* 0x3A0 */
212 __le16 board_struct_ver;
213 __le16 board_checksum;
214 struct falcon_nvconfig_board_v2 board_v2;
215 efx_oword_t ee_base_page_reg; /* 0x3B0 */
216 struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */
217} __packed;
218
219/*************************************************************************/
220
32static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method); 221static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method);
222static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
33 223
34static const unsigned int 224static const unsigned int
35/* "Large" EEPROM device: Atmel AT25640 or similar 225/* "Large" EEPROM device: Atmel AT25640 or similar
@@ -418,6 +608,351 @@ falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
418 608
419/************************************************************************** 609/**************************************************************************
420 * 610 *
611 * XMAC operations
612 *
613 **************************************************************************
614 */
615
616/* Configure the XAUI driver that is an output from Falcon */
617static void falcon_setup_xaui(struct efx_nic *efx)
618{
619 efx_oword_t sdctl, txdrv;
620
621 /* Move the XAUI into low power, unless there is no PHY, in
622 * which case the XAUI will have to drive a cable. */
623 if (efx->phy_type == PHY_TYPE_NONE)
624 return;
625
626 efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
627 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
628 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
629 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
630 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
631 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
632 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
633 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
634 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
635 efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
636
637 EFX_POPULATE_OWORD_8(txdrv,
638 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
639 FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
640 FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
641 FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
642 FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
643 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
644 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
645 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
646 efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
647}
648
649int falcon_reset_xaui(struct efx_nic *efx)
650{
651 struct falcon_nic_data *nic_data = efx->nic_data;
652 efx_oword_t reg;
653 int count;
654
655 /* Don't fetch MAC statistics over an XMAC reset */
656 WARN_ON(nic_data->stats_disable_count == 0);
657
658 /* Start reset sequence */
659 EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
660 efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
661
662 /* Wait up to 10 ms for completion, then reinitialise */
663 for (count = 0; count < 1000; count++) {
664 efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
665 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
666 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
667 falcon_setup_xaui(efx);
668 return 0;
669 }
670 udelay(10);
671 }
672 netif_err(efx, hw, efx->net_dev,
673 "timed out waiting for XAUI/XGXS reset\n");
674 return -ETIMEDOUT;
675}
676
677static void falcon_ack_status_intr(struct efx_nic *efx)
678{
679 struct falcon_nic_data *nic_data = efx->nic_data;
680 efx_oword_t reg;
681
682 if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
683 return;
684
685 /* We expect xgmii faults if the wireside link is down */
686 if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
687 return;
688
689 /* We can only use this interrupt to signal the negative edge of
690 * xaui_align [we have to poll the positive edge]. */
691 if (nic_data->xmac_poll_required)
692 return;
693
694 efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
695}
696
697static bool falcon_xgxs_link_ok(struct efx_nic *efx)
698{
699 efx_oword_t reg;
700 bool align_done, link_ok = false;
701 int sync_status;
702
703 /* Read link status */
704 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
705
706 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
707 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
708 if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
709 link_ok = true;
710
711 /* Clear link status ready for next read */
712 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
713 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
714 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
715 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
716
717 return link_ok;
718}
719
720static bool falcon_xmac_link_ok(struct efx_nic *efx)
721{
722 /*
723 * Check MAC's XGXS link status except when using XGMII loopback
724 * which bypasses the XGXS block.
725 * If possible, check PHY's XGXS link status except when using
726 * MAC loopback.
727 */
728 return (efx->loopback_mode == LOOPBACK_XGMII ||
729 falcon_xgxs_link_ok(efx)) &&
730 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
731 LOOPBACK_INTERNAL(efx) ||
732 efx_mdio_phyxgxs_lane_sync(efx));
733}
734
735static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
736{
737 unsigned int max_frame_len;
738 efx_oword_t reg;
739 bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
740 bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
741
742 /* Configure MAC - cut-thru mode is hard wired on */
743 EFX_POPULATE_OWORD_3(reg,
744 FRF_AB_XM_RX_JUMBO_MODE, 1,
745 FRF_AB_XM_TX_STAT_EN, 1,
746 FRF_AB_XM_RX_STAT_EN, 1);
747 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
748
749 /* Configure TX */
750 EFX_POPULATE_OWORD_6(reg,
751 FRF_AB_XM_TXEN, 1,
752 FRF_AB_XM_TX_PRMBL, 1,
753 FRF_AB_XM_AUTO_PAD, 1,
754 FRF_AB_XM_TXCRC, 1,
755 FRF_AB_XM_FCNTL, tx_fc,
756 FRF_AB_XM_IPG, 0x3);
757 efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
758
759 /* Configure RX */
760 EFX_POPULATE_OWORD_5(reg,
761 FRF_AB_XM_RXEN, 1,
762 FRF_AB_XM_AUTO_DEPAD, 0,
763 FRF_AB_XM_ACPT_ALL_MCAST, 1,
764 FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
765 FRF_AB_XM_PASS_CRC_ERR, 1);
766 efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
767
768 /* Set frame length */
769 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
770 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
771 efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
772 EFX_POPULATE_OWORD_2(reg,
773 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
774 FRF_AB_XM_TX_JUMBO_MODE, 1);
775 efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
776
777 EFX_POPULATE_OWORD_2(reg,
778 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
779 FRF_AB_XM_DIS_FCNTL, !rx_fc);
780 efx_writeo(efx, &reg, FR_AB_XM_FC);
781
782 /* Set MAC address */
783 memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
784 efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
785 memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
786 efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
787}
788
789static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
790{
791 efx_oword_t reg;
792 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
793 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
794 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
795
796 /* XGXS block is flaky and will need to be reset if moving
797 * into our out of XGMII, XGXS or XAUI loopbacks. */
798 if (EFX_WORKAROUND_5147(efx)) {
799 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
800 bool reset_xgxs;
801
802 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
803 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
804 old_xgmii_loopback =
805 EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
806
807 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
808 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
809
810 /* The PHY driver may have turned XAUI off */
811 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
812 (xaui_loopback != old_xaui_loopback) ||
813 (xgmii_loopback != old_xgmii_loopback));
814
815 if (reset_xgxs)
816 falcon_reset_xaui(efx);
817 }
818
819 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
820 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
821 (xgxs_loopback || xaui_loopback) ?
822 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
823 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
824 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
825 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
826
827 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
828 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
829 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
830 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
831 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
832 efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
833}
834
835
836/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
837static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
838{
839 bool mac_up = falcon_xmac_link_ok(efx);
840
841 if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
842 efx_phy_mode_disabled(efx->phy_mode))
843 /* XAUI link is expected to be down */
844 return mac_up;
845
846 falcon_stop_nic_stats(efx);
847
848 while (!mac_up && tries) {
849 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
850 falcon_reset_xaui(efx);
851 udelay(200);
852
853 mac_up = falcon_xmac_link_ok(efx);
854 --tries;
855 }
856
857 falcon_start_nic_stats(efx);
858
859 return mac_up;
860}
861
862static bool falcon_xmac_check_fault(struct efx_nic *efx)
863{
864 return !falcon_xmac_link_ok_retry(efx, 5);
865}
866
867static int falcon_reconfigure_xmac(struct efx_nic *efx)
868{
869 struct falcon_nic_data *nic_data = efx->nic_data;
870
871 falcon_reconfigure_xgxs_core(efx);
872 falcon_reconfigure_xmac_core(efx);
873
874 falcon_reconfigure_mac_wrapper(efx);
875
876 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
877 falcon_ack_status_intr(efx);
878
879 return 0;
880}
881
882static void falcon_update_stats_xmac(struct efx_nic *efx)
883{
884 struct efx_mac_stats *mac_stats = &efx->mac_stats;
885
886 /* Update MAC stats from DMAed values */
887 FALCON_STAT(efx, XgRxOctets, rx_bytes);
888 FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
889 FALCON_STAT(efx, XgRxPkts, rx_packets);
890 FALCON_STAT(efx, XgRxPktsOK, rx_good);
891 FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
892 FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
893 FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
894 FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
895 FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
896 FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
897 FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
898 FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
899 FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
900 FALCON_STAT(efx, XgRxAlignError, rx_align_error);
901 FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
902 FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
903 FALCON_STAT(efx, XgRxControlPkts, rx_control);
904 FALCON_STAT(efx, XgRxPausePkts, rx_pause);
905 FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
906 FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
907 FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
908 FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
909 FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
910 FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
911 FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
912 FALCON_STAT(efx, XgRxLengthError, rx_length_error);
913 FALCON_STAT(efx, XgTxPkts, tx_packets);
914 FALCON_STAT(efx, XgTxOctets, tx_bytes);
915 FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
916 FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
917 FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
918 FALCON_STAT(efx, XgTxControlPkts, tx_control);
919 FALCON_STAT(efx, XgTxPausePkts, tx_pause);
920 FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
921 FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
922 FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
923 FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
924 FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
925 FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
926 FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
927 FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
928 FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
929 FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
930 FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
931 FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
932
933 /* Update derived statistics */
934 efx_update_diff_stat(&mac_stats->tx_good_bytes,
935 mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
936 mac_stats->tx_control * 64);
937 efx_update_diff_stat(&mac_stats->rx_bad_bytes,
938 mac_stats->rx_bytes - mac_stats->rx_good_bytes -
939 mac_stats->rx_control * 64);
940}
941
942static void falcon_poll_xmac(struct efx_nic *efx)
943{
944 struct falcon_nic_data *nic_data = efx->nic_data;
945
946 if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
947 !nic_data->xmac_poll_required)
948 return;
949
950 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
951 falcon_ack_status_intr(efx);
952}
953
954/**************************************************************************
955 *
421 * MAC wrapper 956 * MAC wrapper
422 * 957 *
423 ************************************************************************** 958 **************************************************************************
@@ -529,7 +1064,7 @@ static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
529 falcon_drain_tx_fifo(efx); 1064 falcon_drain_tx_fifo(efx);
530} 1065}
531 1066
532void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) 1067static void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
533{ 1068{
534 struct efx_link_state *link_state = &efx->link_state; 1069 struct efx_link_state *link_state = &efx->link_state;
535 efx_oword_t reg; 1070 efx_oword_t reg;
diff --git a/drivers/net/ethernet/sfc/falcon_xmac.c b/drivers/net/ethernet/sfc/falcon_xmac.c
deleted file mode 100644
index 8333865d4c95..000000000000
--- a/drivers/net/ethernet/sfc/falcon_xmac.c
+++ /dev/null
@@ -1,362 +0,0 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2010 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/delay.h>
12#include "net_driver.h"
13#include "efx.h"
14#include "nic.h"
15#include "regs.h"
16#include "io.h"
17#include "mdio_10g.h"
18#include "workarounds.h"
19
20/**************************************************************************
21 *
22 * MAC operations
23 *
24 *************************************************************************/
25
26/* Configure the XAUI driver that is an output from Falcon */
27void falcon_setup_xaui(struct efx_nic *efx)
28{
29 efx_oword_t sdctl, txdrv;
30
31 /* Move the XAUI into low power, unless there is no PHY, in
32 * which case the XAUI will have to drive a cable. */
33 if (efx->phy_type == PHY_TYPE_NONE)
34 return;
35
36 efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
37 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
38 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
39 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
40 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
41 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
42 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
43 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
44 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
45 efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
46
47 EFX_POPULATE_OWORD_8(txdrv,
48 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
49 FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
50 FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
51 FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
52 FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
53 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
54 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
55 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
56 efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
57}
58
59int falcon_reset_xaui(struct efx_nic *efx)
60{
61 struct falcon_nic_data *nic_data = efx->nic_data;
62 efx_oword_t reg;
63 int count;
64
65 /* Don't fetch MAC statistics over an XMAC reset */
66 WARN_ON(nic_data->stats_disable_count == 0);
67
68 /* Start reset sequence */
69 EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
70 efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
71
72 /* Wait up to 10 ms for completion, then reinitialise */
73 for (count = 0; count < 1000; count++) {
74 efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
75 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
76 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
77 falcon_setup_xaui(efx);
78 return 0;
79 }
80 udelay(10);
81 }
82 netif_err(efx, hw, efx->net_dev,
83 "timed out waiting for XAUI/XGXS reset\n");
84 return -ETIMEDOUT;
85}
86
87static void falcon_ack_status_intr(struct efx_nic *efx)
88{
89 struct falcon_nic_data *nic_data = efx->nic_data;
90 efx_oword_t reg;
91
92 if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
93 return;
94
95 /* We expect xgmii faults if the wireside link is down */
96 if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
97 return;
98
99 /* We can only use this interrupt to signal the negative edge of
100 * xaui_align [we have to poll the positive edge]. */
101 if (nic_data->xmac_poll_required)
102 return;
103
104 efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
105}
106
107static bool falcon_xgxs_link_ok(struct efx_nic *efx)
108{
109 efx_oword_t reg;
110 bool align_done, link_ok = false;
111 int sync_status;
112
113 /* Read link status */
114 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
115
116 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
117 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
118 if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
119 link_ok = true;
120
121 /* Clear link status ready for next read */
122 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
123 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
124 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
125 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
126
127 return link_ok;
128}
129
130static bool falcon_xmac_link_ok(struct efx_nic *efx)
131{
132 /*
133 * Check MAC's XGXS link status except when using XGMII loopback
134 * which bypasses the XGXS block.
135 * If possible, check PHY's XGXS link status except when using
136 * MAC loopback.
137 */
138 return (efx->loopback_mode == LOOPBACK_XGMII ||
139 falcon_xgxs_link_ok(efx)) &&
140 (!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
141 LOOPBACK_INTERNAL(efx) ||
142 efx_mdio_phyxgxs_lane_sync(efx));
143}
144
145static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
146{
147 unsigned int max_frame_len;
148 efx_oword_t reg;
149 bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
150 bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
151
152 /* Configure MAC - cut-thru mode is hard wired on */
153 EFX_POPULATE_OWORD_3(reg,
154 FRF_AB_XM_RX_JUMBO_MODE, 1,
155 FRF_AB_XM_TX_STAT_EN, 1,
156 FRF_AB_XM_RX_STAT_EN, 1);
157 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
158
159 /* Configure TX */
160 EFX_POPULATE_OWORD_6(reg,
161 FRF_AB_XM_TXEN, 1,
162 FRF_AB_XM_TX_PRMBL, 1,
163 FRF_AB_XM_AUTO_PAD, 1,
164 FRF_AB_XM_TXCRC, 1,
165 FRF_AB_XM_FCNTL, tx_fc,
166 FRF_AB_XM_IPG, 0x3);
167 efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
168
169 /* Configure RX */
170 EFX_POPULATE_OWORD_5(reg,
171 FRF_AB_XM_RXEN, 1,
172 FRF_AB_XM_AUTO_DEPAD, 0,
173 FRF_AB_XM_ACPT_ALL_MCAST, 1,
174 FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
175 FRF_AB_XM_PASS_CRC_ERR, 1);
176 efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
177
178 /* Set frame length */
179 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
180 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
181 efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
182 EFX_POPULATE_OWORD_2(reg,
183 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
184 FRF_AB_XM_TX_JUMBO_MODE, 1);
185 efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
186
187 EFX_POPULATE_OWORD_2(reg,
188 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
189 FRF_AB_XM_DIS_FCNTL, !rx_fc);
190 efx_writeo(efx, &reg, FR_AB_XM_FC);
191
192 /* Set MAC address */
193 memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
194 efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
195 memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
196 efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
197}
198
199static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
200{
201 efx_oword_t reg;
202 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
203 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
204 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
205
206 /* XGXS block is flaky and will need to be reset if moving
207 * into our out of XGMII, XGXS or XAUI loopbacks. */
208 if (EFX_WORKAROUND_5147(efx)) {
209 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
210 bool reset_xgxs;
211
212 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
213 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
214 old_xgmii_loopback =
215 EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
216
217 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
218 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
219
220 /* The PHY driver may have turned XAUI off */
221 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
222 (xaui_loopback != old_xaui_loopback) ||
223 (xgmii_loopback != old_xgmii_loopback));
224
225 if (reset_xgxs)
226 falcon_reset_xaui(efx);
227 }
228
229 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
230 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
231 (xgxs_loopback || xaui_loopback) ?
232 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
233 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
234 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
235 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
236
237 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
238 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
239 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
240 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
241 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
242 efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
243}
244
245
246/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
247static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
248{
249 bool mac_up = falcon_xmac_link_ok(efx);
250
251 if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
252 efx_phy_mode_disabled(efx->phy_mode))
253 /* XAUI link is expected to be down */
254 return mac_up;
255
256 falcon_stop_nic_stats(efx);
257
258 while (!mac_up && tries) {
259 netif_dbg(efx, hw, efx->net_dev, "bashing xaui\n");
260 falcon_reset_xaui(efx);
261 udelay(200);
262
263 mac_up = falcon_xmac_link_ok(efx);
264 --tries;
265 }
266
267 falcon_start_nic_stats(efx);
268
269 return mac_up;
270}
271
272bool falcon_xmac_check_fault(struct efx_nic *efx)
273{
274 return !falcon_xmac_link_ok_retry(efx, 5);
275}
276
277int falcon_reconfigure_xmac(struct efx_nic *efx)
278{
279 struct falcon_nic_data *nic_data = efx->nic_data;
280
281 falcon_reconfigure_xgxs_core(efx);
282 falcon_reconfigure_xmac_core(efx);
283
284 falcon_reconfigure_mac_wrapper(efx);
285
286 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
287 falcon_ack_status_intr(efx);
288
289 return 0;
290}
291
292void falcon_update_stats_xmac(struct efx_nic *efx)
293{
294 struct efx_mac_stats *mac_stats = &efx->mac_stats;
295
296 /* Update MAC stats from DMAed values */
297 FALCON_STAT(efx, XgRxOctets, rx_bytes);
298 FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
299 FALCON_STAT(efx, XgRxPkts, rx_packets);
300 FALCON_STAT(efx, XgRxPktsOK, rx_good);
301 FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
302 FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
303 FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
304 FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
305 FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
306 FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
307 FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
308 FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
309 FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
310 FALCON_STAT(efx, XgRxAlignError, rx_align_error);
311 FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
312 FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
313 FALCON_STAT(efx, XgRxControlPkts, rx_control);
314 FALCON_STAT(efx, XgRxPausePkts, rx_pause);
315 FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
316 FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
317 FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
318 FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
319 FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
320 FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
321 FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
322 FALCON_STAT(efx, XgRxLengthError, rx_length_error);
323 FALCON_STAT(efx, XgTxPkts, tx_packets);
324 FALCON_STAT(efx, XgTxOctets, tx_bytes);
325 FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
326 FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
327 FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
328 FALCON_STAT(efx, XgTxControlPkts, tx_control);
329 FALCON_STAT(efx, XgTxPausePkts, tx_pause);
330 FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
331 FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
332 FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
333 FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
334 FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
335 FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
336 FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
337 FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
338 FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
339 FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
340 FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
341 FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
342
343 /* Update derived statistics */
344 efx_update_diff_stat(&mac_stats->tx_good_bytes,
345 mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
346 mac_stats->tx_control * 64);
347 efx_update_diff_stat(&mac_stats->rx_bad_bytes,
348 mac_stats->rx_bytes - mac_stats->rx_good_bytes -
349 mac_stats->rx_control * 64);
350}
351
352void falcon_poll_xmac(struct efx_nic *efx)
353{
354 struct falcon_nic_data *nic_data = efx->nic_data;
355
356 if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
357 !nic_data->xmac_poll_required)
358 return;
359
360 nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
361 falcon_ack_status_intr(efx);
362}
diff --git a/drivers/net/ethernet/sfc/nic.h b/drivers/net/ethernet/sfc/nic.h
index a78436320ab2..0d38cc2e96aa 100644
--- a/drivers/net/ethernet/sfc/nic.h
+++ b/drivers/net/ethernet/sfc/nic.h
@@ -297,12 +297,6 @@ extern int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota);
297extern void efx_nic_eventq_read_ack(struct efx_channel *channel); 297extern void efx_nic_eventq_read_ack(struct efx_channel *channel);
298extern bool efx_nic_event_present(struct efx_channel *channel); 298extern bool efx_nic_event_present(struct efx_channel *channel);
299 299
300/* MAC/PHY */
301extern void falcon_reconfigure_mac_wrapper(struct efx_nic *efx);
302extern bool falcon_xmac_check_fault(struct efx_nic *efx);
303extern int falcon_reconfigure_xmac(struct efx_nic *efx);
304extern void falcon_update_stats_xmac(struct efx_nic *efx);
305
306/* Some statistics are computed as A - B where A and B each increase 300/* Some statistics are computed as A - B where A and B each increase
307 * linearly with some hardware counter(s) and the counters are read 301 * linearly with some hardware counter(s) and the counters are read
308 * asynchronously. If the counters contributing to B are always read 302 * asynchronously. If the counters contributing to B are always read
@@ -347,7 +341,6 @@ extern void siena_prepare_flush(struct efx_nic *efx);
347extern void siena_finish_flush(struct efx_nic *efx); 341extern void siena_finish_flush(struct efx_nic *efx);
348extern void falcon_start_nic_stats(struct efx_nic *efx); 342extern void falcon_start_nic_stats(struct efx_nic *efx);
349extern void falcon_stop_nic_stats(struct efx_nic *efx); 343extern void falcon_stop_nic_stats(struct efx_nic *efx);
350extern void falcon_setup_xaui(struct efx_nic *efx);
351extern int falcon_reset_xaui(struct efx_nic *efx); 344extern int falcon_reset_xaui(struct efx_nic *efx);
352extern void 345extern void
353efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw); 346efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
@@ -370,43 +363,9 @@ extern int efx_nic_test_registers(struct efx_nic *efx,
370extern size_t efx_nic_get_regs_len(struct efx_nic *efx); 363extern size_t efx_nic_get_regs_len(struct efx_nic *efx);
371extern void efx_nic_get_regs(struct efx_nic *efx, void *buf); 364extern void efx_nic_get_regs(struct efx_nic *efx, void *buf);
372 365
373/************************************************************************** 366#define EFX_MAX_FLUSH_TIME 5000
374 *
375 * Falcon MAC stats
376 *
377 **************************************************************************
378 */
379
380#define FALCON_STAT_OFFSET(falcon_stat) EFX_VAL(falcon_stat, offset)
381#define FALCON_STAT_WIDTH(falcon_stat) EFX_VAL(falcon_stat, WIDTH)
382
383/* Retrieve statistic from statistics block */
384#define FALCON_STAT(efx, falcon_stat, efx_stat) do { \
385 if (FALCON_STAT_WIDTH(falcon_stat) == 16) \
386 (efx)->mac_stats.efx_stat += le16_to_cpu( \
387 *((__force __le16 *) \
388 (efx->stats_buffer.addr + \
389 FALCON_STAT_OFFSET(falcon_stat)))); \
390 else if (FALCON_STAT_WIDTH(falcon_stat) == 32) \
391 (efx)->mac_stats.efx_stat += le32_to_cpu( \
392 *((__force __le32 *) \
393 (efx->stats_buffer.addr + \
394 FALCON_STAT_OFFSET(falcon_stat)))); \
395 else \
396 (efx)->mac_stats.efx_stat += le64_to_cpu( \
397 *((__force __le64 *) \
398 (efx->stats_buffer.addr + \
399 FALCON_STAT_OFFSET(falcon_stat)))); \
400 } while (0)
401
402#define FALCON_MAC_STATS_SIZE 0x100
403
404#define MAC_DATA_LBN 0
405#define MAC_DATA_WIDTH 32
406 367
407extern void efx_generate_event(struct efx_nic *efx, unsigned int evq, 368extern void efx_generate_event(struct efx_nic *efx, unsigned int evq,
408 efx_qword_t *event); 369 efx_qword_t *event);
409 370
410extern void falcon_poll_xmac(struct efx_nic *efx);
411
412#endif /* EFX_NIC_H */ 371#endif /* EFX_NIC_H */
diff --git a/drivers/net/ethernet/sfc/regs.h b/drivers/net/ethernet/sfc/regs.h
index ade4c4dc56ca..27ad348d5c01 100644
--- a/drivers/net/ethernet/sfc/regs.h
+++ b/drivers/net/ethernet/sfc/regs.h
@@ -2925,264 +2925,4 @@
2925#define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 0 2925#define FSF_AZ_DRV_GEN_EV_MAGIC_LBN 0
2926#define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 32 2926#define FSF_AZ_DRV_GEN_EV_MAGIC_WIDTH 32
2927 2927
2928/**************************************************************************
2929 *
2930 * Falcon MAC stats
2931 *
2932 **************************************************************************
2933 *
2934 */
2935
2936#define GRxGoodOct_offset 0x0
2937#define GRxGoodOct_WIDTH 48
2938#define GRxBadOct_offset 0x8
2939#define GRxBadOct_WIDTH 48
2940#define GRxMissPkt_offset 0x10
2941#define GRxMissPkt_WIDTH 32
2942#define GRxFalseCRS_offset 0x14
2943#define GRxFalseCRS_WIDTH 32
2944#define GRxPausePkt_offset 0x18
2945#define GRxPausePkt_WIDTH 32
2946#define GRxBadPkt_offset 0x1C
2947#define GRxBadPkt_WIDTH 32
2948#define GRxUcastPkt_offset 0x20
2949#define GRxUcastPkt_WIDTH 32
2950#define GRxMcastPkt_offset 0x24
2951#define GRxMcastPkt_WIDTH 32
2952#define GRxBcastPkt_offset 0x28
2953#define GRxBcastPkt_WIDTH 32
2954#define GRxGoodLt64Pkt_offset 0x2C
2955#define GRxGoodLt64Pkt_WIDTH 32
2956#define GRxBadLt64Pkt_offset 0x30
2957#define GRxBadLt64Pkt_WIDTH 32
2958#define GRx64Pkt_offset 0x34
2959#define GRx64Pkt_WIDTH 32
2960#define GRx65to127Pkt_offset 0x38
2961#define GRx65to127Pkt_WIDTH 32
2962#define GRx128to255Pkt_offset 0x3C
2963#define GRx128to255Pkt_WIDTH 32
2964#define GRx256to511Pkt_offset 0x40
2965#define GRx256to511Pkt_WIDTH 32
2966#define GRx512to1023Pkt_offset 0x44
2967#define GRx512to1023Pkt_WIDTH 32
2968#define GRx1024to15xxPkt_offset 0x48
2969#define GRx1024to15xxPkt_WIDTH 32
2970#define GRx15xxtoJumboPkt_offset 0x4C
2971#define GRx15xxtoJumboPkt_WIDTH 32
2972#define GRxGtJumboPkt_offset 0x50
2973#define GRxGtJumboPkt_WIDTH 32
2974#define GRxFcsErr64to15xxPkt_offset 0x54
2975#define GRxFcsErr64to15xxPkt_WIDTH 32
2976#define GRxFcsErr15xxtoJumboPkt_offset 0x58
2977#define GRxFcsErr15xxtoJumboPkt_WIDTH 32
2978#define GRxFcsErrGtJumboPkt_offset 0x5C
2979#define GRxFcsErrGtJumboPkt_WIDTH 32
2980#define GTxGoodBadOct_offset 0x80
2981#define GTxGoodBadOct_WIDTH 48
2982#define GTxGoodOct_offset 0x88
2983#define GTxGoodOct_WIDTH 48
2984#define GTxSglColPkt_offset 0x90
2985#define GTxSglColPkt_WIDTH 32
2986#define GTxMultColPkt_offset 0x94
2987#define GTxMultColPkt_WIDTH 32
2988#define GTxExColPkt_offset 0x98
2989#define GTxExColPkt_WIDTH 32
2990#define GTxDefPkt_offset 0x9C
2991#define GTxDefPkt_WIDTH 32
2992#define GTxLateCol_offset 0xA0
2993#define GTxLateCol_WIDTH 32
2994#define GTxExDefPkt_offset 0xA4
2995#define GTxExDefPkt_WIDTH 32
2996#define GTxPausePkt_offset 0xA8
2997#define GTxPausePkt_WIDTH 32
2998#define GTxBadPkt_offset 0xAC
2999#define GTxBadPkt_WIDTH 32
3000#define GTxUcastPkt_offset 0xB0
3001#define GTxUcastPkt_WIDTH 32
3002#define GTxMcastPkt_offset 0xB4
3003#define GTxMcastPkt_WIDTH 32
3004#define GTxBcastPkt_offset 0xB8
3005#define GTxBcastPkt_WIDTH 32
3006#define GTxLt64Pkt_offset 0xBC
3007#define GTxLt64Pkt_WIDTH 32
3008#define GTx64Pkt_offset 0xC0
3009#define GTx64Pkt_WIDTH 32
3010#define GTx65to127Pkt_offset 0xC4
3011#define GTx65to127Pkt_WIDTH 32
3012#define GTx128to255Pkt_offset 0xC8
3013#define GTx128to255Pkt_WIDTH 32
3014#define GTx256to511Pkt_offset 0xCC
3015#define GTx256to511Pkt_WIDTH 32
3016#define GTx512to1023Pkt_offset 0xD0
3017#define GTx512to1023Pkt_WIDTH 32
3018#define GTx1024to15xxPkt_offset 0xD4
3019#define GTx1024to15xxPkt_WIDTH 32
3020#define GTx15xxtoJumboPkt_offset 0xD8
3021#define GTx15xxtoJumboPkt_WIDTH 32
3022#define GTxGtJumboPkt_offset 0xDC
3023#define GTxGtJumboPkt_WIDTH 32
3024#define GTxNonTcpUdpPkt_offset 0xE0
3025#define GTxNonTcpUdpPkt_WIDTH 16
3026#define GTxMacSrcErrPkt_offset 0xE4
3027#define GTxMacSrcErrPkt_WIDTH 16
3028#define GTxIpSrcErrPkt_offset 0xE8
3029#define GTxIpSrcErrPkt_WIDTH 16
3030#define GDmaDone_offset 0xEC
3031#define GDmaDone_WIDTH 32
3032
3033#define XgRxOctets_offset 0x0
3034#define XgRxOctets_WIDTH 48
3035#define XgRxOctetsOK_offset 0x8
3036#define XgRxOctetsOK_WIDTH 48
3037#define XgRxPkts_offset 0x10
3038#define XgRxPkts_WIDTH 32
3039#define XgRxPktsOK_offset 0x14
3040#define XgRxPktsOK_WIDTH 32
3041#define XgRxBroadcastPkts_offset 0x18
3042#define XgRxBroadcastPkts_WIDTH 32
3043#define XgRxMulticastPkts_offset 0x1C
3044#define XgRxMulticastPkts_WIDTH 32
3045#define XgRxUnicastPkts_offset 0x20
3046#define XgRxUnicastPkts_WIDTH 32
3047#define XgRxUndersizePkts_offset 0x24
3048#define XgRxUndersizePkts_WIDTH 32
3049#define XgRxOversizePkts_offset 0x28
3050#define XgRxOversizePkts_WIDTH 32
3051#define XgRxJabberPkts_offset 0x2C
3052#define XgRxJabberPkts_WIDTH 32
3053#define XgRxUndersizeFCSerrorPkts_offset 0x30
3054#define XgRxUndersizeFCSerrorPkts_WIDTH 32
3055#define XgRxDropEvents_offset 0x34
3056#define XgRxDropEvents_WIDTH 32
3057#define XgRxFCSerrorPkts_offset 0x38
3058#define XgRxFCSerrorPkts_WIDTH 32
3059#define XgRxAlignError_offset 0x3C
3060#define XgRxAlignError_WIDTH 32
3061#define XgRxSymbolError_offset 0x40
3062#define XgRxSymbolError_WIDTH 32
3063#define XgRxInternalMACError_offset 0x44
3064#define XgRxInternalMACError_WIDTH 32
3065#define XgRxControlPkts_offset 0x48
3066#define XgRxControlPkts_WIDTH 32
3067#define XgRxPausePkts_offset 0x4C
3068#define XgRxPausePkts_WIDTH 32
3069#define XgRxPkts64Octets_offset 0x50
3070#define XgRxPkts64Octets_WIDTH 32
3071#define XgRxPkts65to127Octets_offset 0x54
3072#define XgRxPkts65to127Octets_WIDTH 32
3073#define XgRxPkts128to255Octets_offset 0x58
3074#define XgRxPkts128to255Octets_WIDTH 32
3075#define XgRxPkts256to511Octets_offset 0x5C
3076#define XgRxPkts256to511Octets_WIDTH 32
3077#define XgRxPkts512to1023Octets_offset 0x60
3078#define XgRxPkts512to1023Octets_WIDTH 32
3079#define XgRxPkts1024to15xxOctets_offset 0x64
3080#define XgRxPkts1024to15xxOctets_WIDTH 32
3081#define XgRxPkts15xxtoMaxOctets_offset 0x68
3082#define XgRxPkts15xxtoMaxOctets_WIDTH 32
3083#define XgRxLengthError_offset 0x6C
3084#define XgRxLengthError_WIDTH 32
3085#define XgTxPkts_offset 0x80
3086#define XgTxPkts_WIDTH 32
3087#define XgTxOctets_offset 0x88
3088#define XgTxOctets_WIDTH 48
3089#define XgTxMulticastPkts_offset 0x90
3090#define XgTxMulticastPkts_WIDTH 32
3091#define XgTxBroadcastPkts_offset 0x94
3092#define XgTxBroadcastPkts_WIDTH 32
3093#define XgTxUnicastPkts_offset 0x98
3094#define XgTxUnicastPkts_WIDTH 32
3095#define XgTxControlPkts_offset 0x9C
3096#define XgTxControlPkts_WIDTH 32
3097#define XgTxPausePkts_offset 0xA0
3098#define XgTxPausePkts_WIDTH 32
3099#define XgTxPkts64Octets_offset 0xA4
3100#define XgTxPkts64Octets_WIDTH 32
3101#define XgTxPkts65to127Octets_offset 0xA8
3102#define XgTxPkts65to127Octets_WIDTH 32
3103#define XgTxPkts128to255Octets_offset 0xAC
3104#define XgTxPkts128to255Octets_WIDTH 32
3105#define XgTxPkts256to511Octets_offset 0xB0
3106#define XgTxPkts256to511Octets_WIDTH 32
3107#define XgTxPkts512to1023Octets_offset 0xB4
3108#define XgTxPkts512to1023Octets_WIDTH 32
3109#define XgTxPkts1024to15xxOctets_offset 0xB8
3110#define XgTxPkts1024to15xxOctets_WIDTH 32
3111#define XgTxPkts1519toMaxOctets_offset 0xBC
3112#define XgTxPkts1519toMaxOctets_WIDTH 32
3113#define XgTxUndersizePkts_offset 0xC0
3114#define XgTxUndersizePkts_WIDTH 32
3115#define XgTxOversizePkts_offset 0xC4
3116#define XgTxOversizePkts_WIDTH 32
3117#define XgTxNonTcpUdpPkt_offset 0xC8
3118#define XgTxNonTcpUdpPkt_WIDTH 16
3119#define XgTxMacSrcErrPkt_offset 0xCC
3120#define XgTxMacSrcErrPkt_WIDTH 16
3121#define XgTxIpSrcErrPkt_offset 0xD0
3122#define XgTxIpSrcErrPkt_WIDTH 16
3123#define XgDmaDone_offset 0xD4
3124#define XgDmaDone_WIDTH 32
3125
3126#define FALCON_STATS_NOT_DONE 0x00000000
3127#define FALCON_STATS_DONE 0xffffffff
3128
3129/**************************************************************************
3130 *
3131 * Falcon non-volatile configuration
3132 *
3133 **************************************************************************
3134 */
3135
3136/* Board configuration v2 (v1 is obsolete; later versions are compatible) */
3137struct falcon_nvconfig_board_v2 {
3138 __le16 nports;
3139 u8 port0_phy_addr;
3140 u8 port0_phy_type;
3141 u8 port1_phy_addr;
3142 u8 port1_phy_type;
3143 __le16 asic_sub_revision;
3144 __le16 board_revision;
3145} __packed;
3146
3147/* Board configuration v3 extra information */
3148struct falcon_nvconfig_board_v3 {
3149 __le32 spi_device_type[2];
3150} __packed;
3151
3152/* Bit numbers for spi_device_type */
3153#define SPI_DEV_TYPE_SIZE_LBN 0
3154#define SPI_DEV_TYPE_SIZE_WIDTH 5
3155#define SPI_DEV_TYPE_ADDR_LEN_LBN 6
3156#define SPI_DEV_TYPE_ADDR_LEN_WIDTH 2
3157#define SPI_DEV_TYPE_ERASE_CMD_LBN 8
3158#define SPI_DEV_TYPE_ERASE_CMD_WIDTH 8
3159#define SPI_DEV_TYPE_ERASE_SIZE_LBN 16
3160#define SPI_DEV_TYPE_ERASE_SIZE_WIDTH 5
3161#define SPI_DEV_TYPE_BLOCK_SIZE_LBN 24
3162#define SPI_DEV_TYPE_BLOCK_SIZE_WIDTH 5
3163#define SPI_DEV_TYPE_FIELD(type, field) \
3164 (((type) >> EFX_LOW_BIT(field)) & EFX_MASK32(EFX_WIDTH(field)))
3165
3166#define FALCON_NVCONFIG_OFFSET 0x300
3167
3168#define FALCON_NVCONFIG_BOARD_MAGIC_NUM 0xFA1C
3169struct falcon_nvconfig {
3170 efx_oword_t ee_vpd_cfg_reg; /* 0x300 */
3171 u8 mac_address[2][8]; /* 0x310 */
3172 efx_oword_t pcie_sd_ctl0123_reg; /* 0x320 */
3173 efx_oword_t pcie_sd_ctl45_reg; /* 0x330 */
3174 efx_oword_t pcie_pcs_ctl_stat_reg; /* 0x340 */
3175 efx_oword_t hw_init_reg; /* 0x350 */
3176 efx_oword_t nic_stat_reg; /* 0x360 */
3177 efx_oword_t glb_ctl_reg; /* 0x370 */
3178 efx_oword_t srm_cfg_reg; /* 0x380 */
3179 efx_oword_t spare_reg; /* 0x390 */
3180 __le16 board_magic_num; /* 0x3A0 */
3181 __le16 board_struct_ver;
3182 __le16 board_checksum;
3183 struct falcon_nvconfig_board_v2 board_v2;
3184 efx_oword_t ee_base_page_reg; /* 0x3B0 */
3185 struct falcon_nvconfig_board_v3 board_v3; /* 0x3C0 */
3186} __packed;
3187
3188#endif /* EFX_REGS_H */ 2928#endif /* EFX_REGS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 14:38:15 -0400