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authorLinus Torvalds <torvalds@linux-foundation.org>2013-04-01 18:06:34 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-04-01 18:06:34 -0400
commitaae92db9f0f67559198f6ecde922f15e2aeea7e0 (patch)
treeba3fea6f911409367dc6ba1ad4339f69de4f160d
parentdc543f9e2de1a5c9e48c800439db84f95d365c77 (diff)
parent0f1bc12e9eddaba2baf52d020d37670dbabe3702 (diff)
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull tegra clock driver fix from Mike Turquette: "Missing base address in Tegra clock driver results in non-operational PCIe. On some devices this means that Ethernet will go uninitialized and other devices will fail. This pull request fixes it with a single patch to pass the proper base address in the Tegra clock driver." * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux: clk: tegra: Allow PLLE training to succeed
-rw-r--r--drivers/clk/tegra/clk-tegra20.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 1e2de7305362..f873dcefe0de 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -703,7 +703,7 @@ static void tegra20_pll_init(void)
703 clks[pll_a_out0] = clk; 703 clks[pll_a_out0] = clk;
704 704
705 /* PLLE */ 705 /* PLLE */
706 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL, 706 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
707 0, 100000000, &pll_e_params, 707 0, 100000000, &pll_e_params,
708 0, pll_e_freq_table, NULL); 708 0, pll_e_freq_table, NULL);
709 clk_register_clkdev(clk, "pll_e", NULL); 709 clk_register_clkdev(clk, "pll_e", NULL);