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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-04-24 16:36:01 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-06-07 01:24:50 -0400
commitaa9c185bbcd9cffdb0cda1ad24edd801f70178c5 (patch)
treee071551bc84c37fe9496ddf96da05f7757bfff85
parent72378a4ab7fc30e1ad6a5266218ccc7933d60370 (diff)
ARM: shmobile: r8a7790: add TPU PWM support
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bedd20ca3987..b393592edc83 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -48,6 +48,7 @@
48#define CPG_LEN 0x1000 48#define CPG_LEN 0x1000
49 49
50#define SMSTPCR2 0xe6150138 50#define SMSTPCR2 0xe6150138
51#define SMSTPCR3 0xe615013c
51#define SMSTPCR7 0xe615014c 52#define SMSTPCR7 0xe615014c
52 53
53#define MODEMR 0xE6160060 54#define MODEMR 0xE6160060
@@ -178,11 +179,17 @@ static struct clk div6_clks[DIV6_NR] = {
178}; 179};
179 180
180/* MSTP */ 181/* MSTP */
181enum { MSTP721, MSTP720, 182enum {
182 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR }; 183 MSTP721, MSTP720,
184 MSTP304,
185 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
186 MSTP_NR
187};
188
183static struct clk mstp_clks[MSTP_NR] = { 189static struct clk mstp_clks[MSTP_NR] = {
184 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 190 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
185 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 191 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
192 [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
186 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 193 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
187 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 194 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
188 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 195 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */