i2c-intel-mid: support for Moorestown and Medfield platform

(Updated to address Ben's comments. With regard to the message segment
 restriction it's not something we hit on the actual platform so while
 I will investigate that further I don't think its a blocker to submission.
 At worst its a spot over-restrictive)

From: Wen Wang <wen.w.wang@intel.com>

Initial release of the driver. Updated and verified on hardware.

Cleaned up as follows

Alan Cox:
   Squash down the switches into tables, and use the PCI ident field. We
   could perhaps take this further and put the platform and port number into
   this.
   uint32t -> u32
   bracketing of case statements
   spacing and '!' usage
   Check the speed (which is now 0/1/2) is valid and ignore otherwise.
   Fix remaining problems/suggestions from Jean's review
   Fix items from Ben's review

Arjan van de Ven:
   Initial power management hooks

Yong Wang <youg.y.wang@intel.com>:
   Shared IRQ support

Wen Wang <wen.w.wang@intel.com>:
   D3 support
   Fixes for OCT test runs
   Interrupt optimisations

Hong Liu <hong.liu@intel.com>
   The runtime PM code is working on the wrong device (i2c_adapter->dev).
   The correct one should be pci_dev->dev. This breaks attached i2c
   slave devices with runtime PM enabled. Slave device needs to runtime
   resume parent device before runtime resuming itself, but we always get
   error since we don't have pm_runtime callback for i2c_adapter->dev.

Bin Yang <bin.yang@intel.com>:
   Update speed table

Saadi Maalem <saadi.maalem@intel.com>:
   Clear all interrupts in the hardware init

Celine Chotard <celinex.chotard@intel.com>:
   Correct ordering of clear/disable of IRQs

Signed-off-by: Wen Wang <wen.w.wang@intel.com>
Signed-off-by: Yong Wang <yong.y.wang@intel.com>
Signed-off-by: Hong Liu <hong.liu@intel.com>
Signed-off-by: Bin Yang <bin.yang@intel.com>
Signed-off-by: Arjan van de Ven <arjan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>

3 files changed, 1145 insertions, 0 deletions

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 6539ac2907e9..8fcdfbae64bd 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -396,6 +396,15 @@ config I2C_IMX
           This driver can also be built as a module.  If so, the module
           will be called i2c-imx.
 
+config I2C_INTEL_MID
+        tristate "Intel Moorestown/Medfield Platform I2C controller"
+        help
+          Say Y here if you have an Intel Moorestown/Medfield platform I2C
+          controller.
+
+          This support is also available as a module. If so, the module
+          will be called i2c-intel-mid.
+
 config I2C_IOP3XX
         tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
         depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 033ad413f328..84cb16ae6f9e 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_I2C_GPIO)		+= i2c-gpio.o
 obj-$(CONFIG_I2C_HIGHLANDER)    += i2c-highlander.o
 obj-$(CONFIG_I2C_IBM_IIC)       += i2c-ibm_iic.o
 obj-$(CONFIG_I2C_IMX)           += i2c-imx.o
+obj-$(CONFIG_I2C_INTEL_MID)     += i2c-intel-mid.o
 obj-$(CONFIG_I2C_IOP3XX)        += i2c-iop3xx.o
 obj-$(CONFIG_I2C_IXP2000)       += i2c-ixp2000.o
 obj-$(CONFIG_I2C_MPC)           += i2c-mpc.o
diff --git a/drivers/i2c/busses/i2c-intel-mid.c b/drivers/i2c/busses/i2c-intel-mid.c
new file mode 100644
index 000000000000..80f70d3a744d
--- /dev/null
+++ b/drivers/i2c/busses/i2c-intel-mid.c
@@ -0,0 +1,1135 @@
+/*
+ * Support for Moorestown/Medfield I2C chip
+ *
+ * Copyright (c) 2009 Intel Corporation.
+ * Copyright (c) 2009 Synopsys. Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License, version
+ * 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT ANY
+ * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc., 51
+ * Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/stat.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/pm_runtime.h>
+#include <linux/io.h>
+
+#define DRIVER_NAME     "i2c-intel-mid"
+#define VERSION         "Version 0.5ac2"
+#define PLATFORM        "Moorestown/Medfield"
+
+/* Tables use: 0 Moorestown, 1 Medfield */
+#define NUM_PLATFORMS   2
+enum platform_enum {
+        MOORESTOWN = 0,
+        MEDFIELD = 1,
+};
+
+enum mid_i2c_status {
+        STATUS_IDLE = 0,
+        STATUS_READ_START,
+        STATUS_READ_IN_PROGRESS,
+        STATUS_READ_SUCCESS,
+        STATUS_WRITE_START,
+        STATUS_WRITE_SUCCESS,
+        STATUS_XFER_ABORT,
+        STATUS_STANDBY
+};
+
+/**
+ * struct intel_mid_i2c_private - per device I²C context
+ * @adap: core i2c layer adapter information
+ * @dev: device reference for power management
+ * @base: register base
+ * @speed: speed mode for this port
+ * @complete: completion object for transaction wait
+ * @abort: reason for last abort
+ * @rx_buf: pointer into working receive buffer
+ * @rx_buf_len: receive buffer length
+ * @status: adapter state machine
+ * @msg: the message we are currently processing
+ * @platform: the MID device type we are part of
+ * @lock: transaction serialization
+ *
+ * We allocate one of these per device we discover, it holds the core
+ * i2c layer objects and the data we need to track privately.
+ */
+struct intel_mid_i2c_private {
+        struct i2c_adapter adap;
+        struct device *dev;
+        void __iomem *base;
+        int speed;
+        struct completion complete;
+        int abort;
+        u8 *rx_buf;
+        int rx_buf_len;
+        enum mid_i2c_status status;
+        struct i2c_msg *msg;
+        enum platform_enum platform;
+        struct mutex lock;
+};
+
+#define NUM_SPEEDS              3
+
+#define ACTIVE                  0
+#define STANDBY                 1
+
+
+/* Control register */
+#define IC_CON                  0x00
+#define SLV_DIS                 (1 << 6)        /* Disable slave mode */
+#define RESTART                 (1 << 5)        /* Send a Restart condition */
+#define ADDR_10BIT              (1 << 4)        /* 10-bit addressing */
+#define STANDARD_MODE           (1 << 1)        /* standard mode */
+#define FAST_MODE               (2 << 1)        /* fast mode */
+#define HIGH_MODE               (3 << 1)        /* high speed mode */
+#define MASTER_EN               (1 << 0)        /* Master mode */
+
+/* Target address register */
+#define IC_TAR                  0x04
+#define IC_TAR_10BIT_ADDR       (1 << 12)       /* 10-bit addressing */
+#define IC_TAR_SPECIAL          (1 << 11)       /* Perform special I2C cmd */
+#define IC_TAR_GC_OR_START      (1 << 10)       /* 0: Gerneral Call Address */
+                                                /* 1: START BYTE */
+/* Slave Address Register */
+#define IC_SAR                  0x08            /* Not used in Master mode */
+
+/* High Speed Master Mode Code Address Register */
+#define IC_HS_MADDR             0x0c
+
+/* Rx/Tx Data Buffer and Command Register */
+#define IC_DATA_CMD             0x10
+#define IC_RD                   (1 << 8)        /* 1: Read 0: Write */
+
+/* Standard Speed Clock SCL High Count Register */
+#define IC_SS_SCL_HCNT          0x14
+
+/* Standard Speed Clock SCL Low Count Register */
+#define IC_SS_SCL_LCNT          0x18
+
+/* Fast Speed Clock SCL High Count Register */
+#define IC_FS_SCL_HCNT          0x1c
+
+/* Fast Spedd Clock SCL Low Count Register */
+#define IC_FS_SCL_LCNT          0x20
+
+/* High Speed Clock SCL High Count Register */
+#define IC_HS_SCL_HCNT          0x24
+
+/* High Speed Clock SCL Low Count Register */
+#define IC_HS_SCL_LCNT          0x28
+
+/* Interrupt Status Register */
+#define IC_INTR_STAT            0x2c            /* Read only */
+#define R_GEN_CALL              (1 << 11)
+#define R_START_DET             (1 << 10)
+#define R_STOP_DET              (1 << 9)
+#define R_ACTIVITY              (1 << 8)
+#define R_RX_DONE               (1 << 7)
+#define R_TX_ABRT               (1 << 6)
+#define R_RD_REQ                (1 << 5)