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authorLinus Walleij <linus.walleij@linaro.org>2014-03-03 00:40:22 -0500
committerLinus Walleij <linus.walleij@linaro.org>2014-03-03 00:40:22 -0500
commita9ea2ed45a221edf8fff4b505a2d5e1d4fcf2c78 (patch)
treeac3d8ba59d6ed07bd6aa05ad7f1990aedf92e12d
parent6787141361dc77b5d55bf58760029f846244ba3a (diff)
parentcdfe3175eb90f9793391a116d38b3545ecc820b5 (diff)
Merge branch 'pinctrl-mvebu' into devel
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/marvell,dove.txt22
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt82
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt80
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt2
-rw-r--r--drivers/pinctrl/mvebu/Kconfig9
-rw-r--r--drivers/pinctrl/mvebu/Makefile2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-370.c20
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-375.c459
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-38x.c462
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-xp.c24
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-dove.c403
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-kirkwood.c25
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c122
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.h55
18 files changed, 1480 insertions, 291 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell,dove.txt
new file mode 100644
index 000000000000..aaaf64c56e44
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell,dove.txt
@@ -0,0 +1,22 @@
1Marvell Dove Platforms Device Tree Bindings
2-----------------------------------------------
3
4Boards with a Marvell Dove SoC shall have the following properties:
5
6Required root node property:
7- compatible: must contain "marvell,dove";
8
9* Global Configuration registers
10
11Global Configuration registers of Dove SoC are shared by a syscon node.
12
13Required properties:
14- compatible: must contain "marvell,dove-global-config" and "syscon".
15- reg: base address and size of the Global Configuration registers.
16
17Example:
18
19gconf: global-config@e802c {
20 compatible = "marvell,dove-global-config", "syscon";
21 reg = <0xe802c 0x14>;
22};
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
index 01ef408e205f..adda2a8d1d52 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -5,6 +5,7 @@ part and usage.
5 5
6Required properties: 6Required properties:
7- compatible: "marvell,88f6710-pinctrl" 7- compatible: "marvell,88f6710-pinctrl"
8- reg: register specifier of MPP registers
8 9
9Available mpp pins/groups and functions: 10Available mpp pins/groups and functions:
10Note: brackets (x) are not part of the mpp name for marvell,function and given 11Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
new file mode 100644
index 000000000000..7de0cda4a379
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt
@@ -0,0 +1,82 @@
1* Marvell Armada 375 SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6720-pinctrl"
8- reg: register specifier of MPP registers
9
10Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given
12only for more detailed description in this document.
13
14name pins functions
15================================================================================
16mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1)
17mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
18mpp2 2 gpio, dev(ad4), ptp(eventreq), led(c0), audio(sdi)
19mpp3 3 gpio, dev(ad5), ptp(triggen), led(p3), audio(mclk)
20mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
21mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
22mpp6 6 gpio, dev(ad0), led(p1), audio(rclk)
23mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk)
24mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0)
25mpp9 9 gpio, nf(wen), spi0(sck), spi1(sck)
26mpp10 10 gpio, nf(ren), dram(vttctrl), led(c1)
27mpp11 11 gpio, dev(a0), led(c2), audio(sdo)
28mpp12 12 gpio, dev(a1), audio(bclk)
29mpp13 13 gpio, dev(readyn), pcie0(rstoutn), pcie1(rstoutn)
30mpp14 14 gpio, i2c0(sda), uart1(txd)
31mpp15 15 gpio, i2c0(sck), uart1(rxd)
32mpp16 16 gpio, uart0(txd)
33mpp17 17 gpio, uart0(rxd)
34mpp18 18 gpio, tdm(intn)
35mpp19 19 gpio, tdm(rstn)
36mpp20 20 gpio, tdm(pclk)
37mpp21 21 gpio, tdm(fsync)
38mpp22 22 gpio, tdm(drx)
39mpp23 23 gpio, tdm(dtx)
40mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts)
41mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts)
42mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts)
43mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts)
44mpp28 28 gpio, led(p3), ge1(txctl), sd(clk)
45mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3)
46mpp30 30 gpio, ge1(txd0), spi1(cs0)
47mpp31 31 gpio, ge1(txd1), spi1(mosi)
48mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(triggen)
49mpp33 33 gpio, ge1(txd3), spi1(miso)
50mpp34 34 gpio, ge1(txclkout), spi1(sck)
51mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
52mpp36 36 gpio, pcie0(clkreq)
53mpp37 37 gpio, pcie0(clkreq), tdm(intn), ge(mdc)
54mpp38 38 gpio, pcie1(clkreq), ge(mdio)
55mpp39 39 gpio, ref(clkout)
56mpp40 40 gpio, uart1(txd)
57mpp41 41 gpio, uart1(rxd)
58mpp42 42 gpio, spi1(cs2), led(c0)
59mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
60mpp44 44 gpio, sata0(prsnt)
61mpp45 45 gpio, spi0(cs2), pcie0(rstoutn)
62mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0)
63mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1)
64mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2)
65mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3)
66mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0)
67mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1)
68mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2)
69mpp53 53 gpio, pcie1(rstoutn), ge0(rxd3), ge1(rxd3)
70mpp54 54 gpio, pcie0(rstoutn), ge0(rxctl), ge1(rxctl)
71mpp55 55 gpio, ge0(rxclk), ge1(rxclk)
72mpp56 56 gpio, ge0(txclkout), ge1(txclkout)
73mpp57 57 gpio, ge0(txctl), ge1(txctl)
74mpp58 58 gpio, led(c0)
75mpp59 59 gpio, led(c1)
76mpp60 60 gpio, uart1(txd), led(c2)
77mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
78mpp62 62 gpio, i2c1(sck), led(p1)
79mpp63 63 gpio, ptp(triggen), led(p2)
80mpp64 64 gpio, dram(vttctrl), led(p3)
81mpp65 65 gpio, sata1(prsnt)
82mpp66 66 gpio, ptp(eventreq), spi1(cs3)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
new file mode 100644
index 000000000000..b17c96849fc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt
@@ -0,0 +1,80 @@
1* Marvell Armada 380/385 SoC pinctrl driver for mpp
2
3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4part and usage.
5
6Required properties:
7- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
9 SoC being used.
10- reg: register specifier of MPP registers
11
12Available mpp pins/groups and functions:
13Note: brackets (x) are not part of the mpp name for marvell,function and given
14only for more detailed description in this document.
15
16name pins functions
17================================================================================
18mpp0 0 gpio, ua0(rxd)
19mpp1 1 gpio, ua0(txd)
20mpp2 2 gpio, i2c0(sck)
21mpp3 3 gpio, i2c0(sda)
22mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
23mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts)
24mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3)
25mpp7 7 gpio, ge0(txd0), dev(ad9)
26mpp8 8 gpio, ge0(txd1), dev(ad10)
27mpp9 9 gpio, ge0(txd2), dev(ad11)
28mpp10 10 gpio, ge0(txd3), dev(ad12)
29mpp11 11 gpio, ge0(txctl), dev(ad13)
30mpp12 12 gpio, ge0(rxd0), pcie0(rstout), pcie1(rstout) [1], spi0(cs1), dev(ad14)
31mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15)
32mpp14 14 gpio, ge0(rxd2), ptp(clk), m(vtt_ctrl), spi0(cs3), dev(wen1)
33mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi), pcie1(rstout) [1]
34mpp16 16 gpio, ge0(rxctl), ge(mdio slave), m(decc_err), spi0(miso), pcie0(clkreq)
35mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt)
36mpp18 18 gpio, ge0(rxerr), ptp(trig_gen), ua1(txd), spi0(cs0), pcie1(rstout) [1]
37mpp19 19 gpio, ge0(col), ptp(event_req), pcie0(clkreq), sata1(prsnt), ua0(cts)
38mpp20 20 gpio, ge0(txclk), ptp(clk), pcie1(rstout) [1], sata0(prsnt), ua0(rts)
39mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs)
40mpp22 22 gpio, spi0(mosi), dev(ad0)
41mpp23 23 gpio, spi0(sck), dev(ad2)
42mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
43mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0)
44mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
45mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
46mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5)
47mpp29 29 gpio, ge1(txd1), dev(ale0)
48mpp30 30 gpio, ge1(txd2), dev(oen)
49mpp31 31 gpio, ge1(txd3), dev(ale1)
50mpp32 32 gpio, ge1(txctl), dev(wen0)
51mpp33 33 gpio, m(decc_err), dev(ad3)
52mpp34 34 gpio, dev(ad1)
53mpp35 35 gpio, ref(clk_out1), dev(a1)
54mpp36 36 gpio, ptp(trig_gen), dev(a0)
55mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8)
56mpp38 38 gpio, ptp(event_req), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4)
57mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2)
58mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6)
59mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last)
60mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7)
61mpp43 43 gpio, pcie0(clkreq), m(vtt_ctrl), m(decc_err), pcie0(rstout), dev(clkout)
62mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3], pcie0(rstout)
63mpp45 45 gpio, ref(clk_out0), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
64mpp46 46 gpio, ref(clk_out1), pcie0(rstout), pcie1(rstout) [1], pcie2(rstout), pcie3(rstout)
65mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], spi1(cs2), sata3(prsnt) [2]
66mpp48 48 gpio, sata0(prsnt), m(vtt_ctrl), tdm2c(pclk), audio(mclk), sd0(d4)
67mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm2c(fsync), audio(lrclk), sd0(d5)
68mpp50 50 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(drx), audio(extclk), sd0(cmd)
69mpp51 51 gpio, tdm2c(dtx), audio(sdo), m(decc_err)
70mpp52 52 gpio, pcie0(rstout), pcie1(rstout) [1], tdm2c(intn), audio(sdi), sd0(d6)
71mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm2c(rstn), audio(bclk), sd0(d7)
72mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), pcie1(rstout) [1], sd0(d3)
73mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0)
74mpp56 56 gpio, ua1(rts), ge(mdc), m(decc_err), spi1(mosi)
75mpp57 57 gpio, spi1(sck), sd0(clk)
76mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1)
77mpp59 59 gpio, pcie0(rstout), i2c1(sda), pcie1(rstout) [1], spi1(cs0), sd0(d2)
78
79[1]: only available on 88F6820 and 88F6828
80[2]: only available on 88F6828
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
index bfa0a2e5e0cb..373dbccd7ab0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
6Required properties: 6Required properties:
7- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", 7- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl" 8 "marvell,mv78460-pinctrl"
9- reg: register specifier of MPP registers
9 10
10This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. 11This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
11 12
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
index 50ec3512a292..cf52477cc7ee 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -6,6 +6,7 @@ part and usage.
6Required properties: 6Required properties:
7- compatible: "marvell,dove-pinctrl" 7- compatible: "marvell,dove-pinctrl"
8- clocks: (optional) phandle of pdma clock 8- clocks: (optional) phandle of pdma clock
9- reg: register specifiers of MPP, MPP4, and PMU MPP registers
9 10
10Available mpp pins/groups and functions: 11Available mpp pins/groups and functions:
11Note: brackets (x) are not part of the mpp name for marvell,function and given 12Note: brackets (x) are not part of the mpp name for marvell,function and given
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
index 95daf6335c37..730444a9a4de 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -8,6 +8,7 @@ Required properties:
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", 8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl" 9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
10 "marvell,98dx4122-pinctrl" 10 "marvell,98dx4122-pinctrl"
11- reg: register specifier of MPP registers
11 12
12This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. 13This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
13It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. 14It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
index 0a26c3aa4e6d..0c09f4eb2af0 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -37,7 +37,7 @@ uart1: serial@12100 {
37 37
38pinctrl: pinctrl@d0200 { 38pinctrl: pinctrl@d0200 {
39 compatible = "marvell,dove-pinctrl"; 39 compatible = "marvell,dove-pinctrl";
40 reg = <0xd0200 0x20>; 40 reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>;
41 41
42 pmx_uart1_sw: pmx-uart1-sw { 42 pmx_uart1_sw: pmx-uart1-sw {
43 marvell,pins = "mpp_uart1"; 43 marvell,pins = "mpp_uart1";
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index 366fa541ee91..cc298fade93a 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -8,6 +8,7 @@ config PINCTRL_MVEBU
8config PINCTRL_DOVE 8config PINCTRL_DOVE
9 bool 9 bool
10 select PINCTRL_MVEBU 10 select PINCTRL_MVEBU
11 select MFD_SYSCON
11 12
12config PINCTRL_KIRKWOOD 13config PINCTRL_KIRKWOOD
13 bool 14 bool
@@ -17,6 +18,14 @@ config PINCTRL_ARMADA_370
17 bool 18 bool
18 select PINCTRL_MVEBU 19 select PINCTRL_MVEBU
19 20
21config PINCTRL_ARMADA_375
22 bool
23 select PINCTRL_MVEBU
24
25config PINCTRL_ARMADA_38X
26 bool
27 select PINCTRL_MVEBU
28
20config PINCTRL_ARMADA_XP 29config PINCTRL_ARMADA_XP
21 bool 30 bool
22 select PINCTRL_MVEBU 31 select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index 37c253297af0..bc1b9f14f539 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -2,4 +2,6 @@ obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
2obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o 2obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
3obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o 3obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
4obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o 4obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
5obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
6obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
5obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o 7obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
index ae1f760cbdd2..670e5b01c678 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
@@ -23,6 +23,18 @@
23 23
24#include "pinctrl-mvebu.h" 24#include "pinctrl-mvebu.h"
25 25
26static void __iomem *mpp_base;
27
28static int armada_370_mpp_ctrl_get(unsigned pid, unsigned long *config)
29{
30 return default_mpp_ctrl_get(mpp_base, pid, config);
31}
32
33static int armada_370_mpp_ctrl_set(unsigned pid, unsigned long config)
34{
35 return default_mpp_ctrl_set(mpp_base, pid, config);
36}
37
26static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = { 38static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
27 MPP_MODE(0, 39 MPP_MODE(0,
28 MPP_FUNCTION(0x0, "gpio", NULL), 40 MPP_FUNCTION(0x0, "gpio", NULL),
@@ -373,7 +385,7 @@ static struct of_device_id armada_370_pinctrl_of_match[] = {
373}; 385};
374 386
375static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = { 387static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
376 MPP_REG_CTRL(0, 65), 388 MPP_FUNC_CTRL(0, 65, NULL, armada_370_mpp_ctrl),
377}; 389};
378 390
379static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = { 391static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
@@ -385,6 +397,12 @@ static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
385static int armada_370_pinctrl_probe(struct platform_device *pdev) 397static int armada_370_pinctrl_probe(struct platform_device *pdev)
386{ 398{
387 struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info; 399 struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
400 struct resource *res;
401
402 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 mpp_base = devm_ioremap_resource(&pdev->dev, res);
404 if (IS_ERR(mpp_base))
405 return PTR_ERR(mpp_base);
388 406
389 soc->variant = 0; /* no variants for Armada 370 */ 407 soc->variant = 0; /* no variants for Armada 370 */
390 soc->controls = mv88f6710_mpp_controls; 408 soc->controls = mv88f6710_mpp_controls;
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c
new file mode 100644
index 000000000000..db078fe7ace6
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c
@@ -0,0 +1,459 @@
1/*
2 * Marvell Armada 375 pinctrl driver based on mvebu pinctrl core
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/clk.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22#include <linux/pinctrl/pinctrl.h>
23
24#include "pinctrl-mvebu.h"
25
26static void __iomem *mpp_base;
27
28static int armada_375_mpp_ctrl_get(unsigned pid, unsigned long *config)
29{
30 return default_mpp_ctrl_get(mpp_base, pid, config);
31}
32
33static int armada_375_mpp_ctrl_set(unsigned pid, unsigned long config)
34{
35 return default_mpp_ctrl_set(mpp_base, pid, config);
36}
37
38static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
39 MPP_MODE(0,
40 MPP_FUNCTION(0x0, "gpio", NULL),
41 MPP_FUNCTION(0x1, "dev", "ad2"),
42 MPP_FUNCTION(0x2, "spi0", "cs1"),
43 MPP_FUNCTION(0x3, "spi1", "cs1"),
44 MPP_FUNCTION(0x5, "nand", "io2")),
45 MPP_MODE(1,
46 MPP_FUNCTION(0x0, "gpio", NULL),
47 MPP_FUNCTION(0x1, "dev", "ad3"),
48 MPP_FUNCTION(0x2, "spi0", "mosi"),
49 MPP_FUNCTION(0x3, "spi1", "mosi"),
50 MPP_FUNCTION(0x5, "nand", "io3")),
51 MPP_MODE(2,
52 MPP_FUNCTION(0x0, "gpio", NULL),
53 MPP_FUNCTION(0x1, "dev", "ad4"),
54 MPP_FUNCTION(0x2, "ptp", "eventreq"),
55 MPP_FUNCTION(0x3, "led", "c0"),
56 MPP_FUNCTION(0x4, "audio", "sdi"),
57 MPP_FUNCTION(0x5, "nand", "io4"),
58 MPP_FUNCTION(0x6, "spi1", "mosi")),
59 MPP_MODE(3,
60 MPP_FUNCTION(0x0, "gpio", NULL),
61 MPP_FUNCTION(0x1, "dev", "ad5"),
62 MPP_FUNCTION(0x2, "ptp", "triggen"),
63 MPP_FUNCTION(0x3, "led", "p3"),
64 MPP_FUNCTION(0x4, "audio", "mclk"),
65 MPP_FUNCTION(0x5, "nand", "io5"),
66 MPP_FUNCTION(0x6, "spi1", "miso")),
67 MPP_MODE(4,
68 MPP_FUNCTION(0x0, "gpio", NULL),
69 MPP_FUNCTION(0x1, "dev", "ad6"),
70 MPP_FUNCTION(0x2, "spi0", "miso"),
71 MPP_FUNCTION(0x3, "spi1", "miso"),
72 MPP_FUNCTION(0x5, "nand", "io6")),
73 MPP_MODE(5,
74 MPP_FUNCTION(0x0, "gpio", NULL),
75 MPP_FUNCTION(0x1, "dev", "ad7"),
76 MPP_FUNCTION(0x2, "spi0", "cs2"),
77 MPP_FUNCTION(0x3, "spi1", "cs2"),
78 MPP_FUNCTION(0x5, "nand", "io7"),
79 MPP_FUNCTION(0x6, "spi1", "miso")),
80 MPP_MODE(6,
81 MPP_FUNCTION(0x0, "gpio", NULL),
82 MPP_FUNCTION(0x1, "dev", "ad0"),
83 MPP_FUNCTION(0x3, "led", "p1"),
84 MPP_FUNCTION(0x4, "audio", "rclk"),
85 MPP_FUNCTION(0x5, "nand", "io0")),
86 MPP_MODE(7,
87 MPP_FUNCTION(0x0, "gpio", NULL),
88 MPP_FUNCTION(0x1, "dev", "ad1"),
89 MPP_FUNCTION(0x2, "ptp", "clk"),
90 MPP_FUNCTION(0x3, "led", "p2"),
91 MPP_FUNCTION(0x4, "audio", "extclk"),
92 MPP_FUNCTION(0x5, "nand", "io1")),
93 MPP_MODE(8,
94 MPP_FUNCTION(0x0, "gpio", NULL),
95 MPP_FUNCTION(0x1, "dev ", "bootcs"),
96 MPP_FUNCTION(0x2, "spi0", "cs0"),
97 MPP_FUNCTION(0x3, "spi1", "cs0"),
98 MPP_FUNCTION(0x5, "nand", "ce")),
99 MPP_MODE(9,
100 MPP_FUNCTION(0x0, "gpio", NULL),
101 MPP_FUNCTION(0x1, "nf", "wen"),
102 MPP_FUNCTION(0x2, "spi0", "sck"),
103 MPP_FUNCTION(0x3, "spi1", "sck"),
104 MPP_FUNCTION(0x5, "nand", "we")),
105 MPP_MODE(10,
106 MPP_FUNCTION(0x0, "gpio", NULL),
107 MPP_FUNCTION(0x1, "nf", "ren"),
108 MPP_FUNCTION(0x2, "dram", "vttctrl"),
109 MPP_FUNCTION(0x3, "led", "c1"),
110 MPP_FUNCTION(0x5, "nand", "re"),
111 MPP_FUNCTION(0x6, "spi1", "sck")),
112 MPP_MODE(11,
113 MPP_FUNCTION(0x0, "gpio", NULL),
114 MPP_FUNCTION(0x1, "dev", "a0"),
115 MPP_FUNCTION(0x3, "led", "c2"),
116 MPP_FUNCTION(0x4, "audio", "sdo"),
117 MPP_FUNCTION(0x5, "nand", "cle")),
118 MPP_MODE(12,
119 MPP_FUNCTION(0x0, "gpio", NULL),
120 MPP_FUNCTION(0x1, "dev", "a1"),
121 MPP_FUNCTION(0x4, "audio", "bclk"),
122 MPP_FUNCTION(0x5, "nand", "ale")),
123 MPP_MODE(13,
124 MPP_FUNCTION(0x0, "gpio", NULL),
125 MPP_FUNCTION(0x1, "dev", "readyn"),
126 MPP_FUNCTION(0x2, "pcie0", "rstoutn"),
127 MPP_FUNCTION(0x3, "pcie1", "rstoutn"),
128 MPP_FUNCTION(0x5, "nand", "rb"),
129 MPP_FUNCTION(0x6, "spi1", "mosi")),
130 MPP_MODE(14,
131 MPP_FUNCTION(0x0, "gpio", NULL),
132 MPP_FUNCTION(0x2, "i2c0", "sda"),
133 MPP_FUNCTION(0x3, "uart1", "txd")),
134 MPP_MODE(15,
135 MPP_FUNCTION(0x0, "gpio", NULL),
136 MPP_FUNCTION(0x2, "i2c0", "sck"),
137 MPP_FUNCTION(0x3, "uart1", "rxd")),
138 MPP_MODE(16,
139 MPP_FUNCTION(0x0, "gpio", NULL),
140 MPP_FUNCTION(0x2, "uart0", "txd")),
141 MPP_MODE(17,
142 MPP_FUNCTION(0x0, "gpio", NULL),
143 MPP_FUNCTION(0x2, "uart0", "rxd")),
144 MPP_MODE(18,
145 MPP_FUNCTION(0x0, "gpio", NULL),
146 MPP_FUNCTION(0x2, "tdm", "intn")),
147 MPP_MODE(19,
148 MPP_FUNCTION(0x0, "gpio", NULL),
149 MPP_FUNCTION(0x2, "tdm", "rstn")),
150 MPP_MODE(20,
151 MPP_FUNCTION(0x0, "gpio", NULL),
152 MPP_FUNCTION(0x2, "tdm", "pclk")),
153 MPP_MODE(21,
154 MPP_FUNCTION(0x0, "gpio", NULL),
155 MPP_FUNCTION(0x2, "tdm", "fsync")),
156 MPP_MODE(22,
157 MPP_FUNCTION(0x0, "gpio", NULL),
158 MPP_FUNCTION(0x2, "tdm", "drx")),
159 MPP_MODE(23,
160 MPP_FUNCTION(0x0, "gpio", NULL),
161 MPP_FUNCTION(0x2, "tdm", "dtx")),
162 MPP_MODE(24,
163 MPP_FUNCTION(0x0, "gpio", NULL),
164 MPP_FUNCTION(0x1, "led", "p0"),
165 MPP_FUNCTION(0x2, "ge1", "rxd0"),
166 MPP_FUNCTION(0x3, "sd", "cmd"),
167 MPP_FUNCTION(0x4, "uart0", "rts"),
168 MPP_FUNCTION(0x5, "spi0", "cs0"),
169 MPP_FUNCTION(0x6, "dev", "cs1")),
170 MPP_MODE(25,
171 MPP_FUNCTION(0x0, "gpio", NULL),
172 MPP_FUNCTION(0x1, "led", "p2"),
173 MPP_FUNCTION(0x2, "ge1", "rxd1"),
174 MPP_FUNCTION(0x3, "sd", "d0"),
175 MPP_FUNCTION(0x4, "uart0", "cts"),
176 MPP_FUNCTION(0x5, "spi0", "mosi"),
177 MPP_FUNCTION(0x6, "dev", "cs2")),
178 MPP_MODE(26,
179 MPP_FUNCTION(0x0, "gpio", NULL),
180 MPP_FUNCTION(0x1, "pcie0", "clkreq"),
181 MPP_FUNCTION(0x2, "ge1", "rxd2"),
182 MPP_FUNCTION(0x3, "sd", "d2"),
183 MPP_FUNCTION(0x4, "uart1", "rts"),
184 MPP_FUNCTION(0x5, "spi0", "cs1"),
185 MPP_FUNCTION(0x6, "led", "c1")),
186 MPP_MODE(27,
187 MPP_FUNCTION(0x0, "gpio", NULL),
188 MPP_FUNCTION(0x1, "pcie1", "clkreq"),
189 MPP_FUNCTION(0x2, "ge1", "rxd3"),
190 MPP_FUNCTION(0x3, "sd", "d1"),
191 MPP_FUNCTION(0x4, "uart1", "cts"),
192 MPP_FUNCTION(0x5, "spi0", "miso"),
193 MPP_FUNCTION(0x6, "led", "c2")),
194 MPP_MODE(28,
195 MPP_FUNCTION(0x0, "gpio", NULL),
196 MPP_FUNCTION(0x1, "led", "p3"),
197 MPP_FUNCTION(0x2, "ge1", "txctl"),
198 MPP_FUNCTION(0x3, "sd", "clk"),
199 MPP_FUNCTION(0x5, "dram", "vttctrl")),
200 MPP_MODE(29,
201 MPP_FUNCTION(0x0, "gpio", NULL),
202 MPP_FUNCTION(0x1, "pcie1", "clkreq"),
203 MPP_FUNCTION(0x2, "ge1", "rxclk"),
204 MPP_FUNCTION(0x3, "sd", "d3"),
205 MPP_FUNCTION(0x5, "spi0", "sck"),
206 MPP_FUNCTION(0x6, "pcie0", "rstoutn")),
207 MPP_MODE(30,
208 MPP_FUNCTION(0x0, "gpio", NULL),
209 MPP_FUNCTION(0x2, "ge1", "txd0"),
210 MPP_FUNCTION(0x3, "spi1", "cs0"),
211 MPP_FUNCTION(0x5, "led", "p3"),
212 MPP_FUNCTION(0x6, "ptp", "eventreq")),
213 MPP_MODE(31,
214 MPP_FUNCTION(0x0, "gpio", NULL),
215 MPP_FUNCTION(0x2, "ge1", "txd1"),
216 MPP_FUNCTION(0x3, "spi1", "mosi"),
217 MPP_FUNCTION(0x5, "led", "p0")),
218 MPP_MODE(32,
219 MPP_FUNCTION(0x0, "gpio", NULL),
220 MPP_FUNCTION(0x2, "ge1", "txd2"),
221 MPP_FUNCTION(0x3, "spi1", "sck"),
222 MPP_FUNCTION(0x4, "ptp", "triggen"),
223 MPP_FUNCTION(0x5, "led", "c0")),
224 MPP_MODE(33,
225 MPP_FUNCTION(0x0, "gpio", NULL),
226 MPP_FUNCTION(0x2, "ge1", "txd3"),
227 MPP_FUNCTION(0x3, "spi1", "miso"),
228 MPP_FUNCTION(0x5, "led", "p2")),
229 MPP_MODE(34,
230 MPP_FUNCTION(0x0, "gpio", NULL),
231 MPP_FUNCTION(0x2, "ge1", "txclkout"),
232 MPP_FUNCTION(0x3, "spi1", "sck"),
233 MPP_FUNCTION(0x5, "led", "c1")),
234 MPP_MODE(35,
235 MPP_FUNCTION(0x0, "gpio", NULL),
236 MPP_FUNCTION(0x2, "ge1", "rxctl"),
237 MPP_FUNCTION(0x3, "spi1", "cs1"),
238 MPP_FUNCTION(0x4, "spi0", "cs2"),
239 MPP_FUNCTION(0x5, "led", "p1")),
240 MPP_MODE(36,
241 MPP_FUNCTION(0x0, "gpio", NULL),
242 MPP_FUNCTION(0x1, "pcie0", "clkreq"),
243 MPP_FUNCTION(0x5, "led", "c2")),
244 MPP_MODE(37,
245 MPP_FUNCTION(0x0, "gpio", NULL),
246 MPP_FUNCTION(0x1, "pcie0", "clkreq"),
247 MPP_FUNCTION(0x2, "tdm", "intn"),
248 MPP_FUNCTION(0x4, "ge", "mdc")),
249 MPP_MODE(38,
250 MPP_FUNCTION(0x0, "gpio", NULL),
251 MPP_FUNCTION(0x1, "pcie1", "clkreq"),
252 MPP_FUNCTION(0x4, "ge", "mdio")),
253 MPP_MODE(39,
254 MPP_FUNCTION(0x0, "gpio", NULL),
255 MPP_FUNCTION(0x4, "ref", "clkout"),
256 MPP_FUNCTION(0x5, "led", "p3")),
257 MPP_MODE(40,
258 MPP_FUNCTION(0x0, "gpio", NULL),
259 MPP_FUNCTION(0x4, "uart1", "txd"),
260 MPP_FUNCTION(0x5, "led", "p0")),
261 MPP_MODE(41,
262 MPP_FUNCTION(0x0, "gpio", NULL),
263 MPP_FUNCTION(0x4, "uart1", "rxd"),
264 MPP_FUNCTION(0x5, "led", "p1")),
265 MPP_MODE(42,
266 MPP_FUNCTION(0x0, "gpio", NULL),
267 MPP_FUNCTION(0x3, "spi1", "cs2"),
268 MPP_FUNCTION(0x4, "led", "c0"),
269 MPP_FUNCTION(0x6, "ptp", "clk")),
270 MPP_MODE(43,
271 MPP_FUNCTION(0x0, "gpio", NULL),
272 MPP_FUNCTION(0x2, "sata0", "prsnt"),
273 MPP_FUNCTION(0x4, "dram", "vttctrl"),
274 MPP_FUNCTION(0x5, "led", "c1")),
275 MPP_MODE(44,
276 MPP_FUNCTION(0x0, "gpio", NULL),
277 MPP_FUNCTION(0x4, "sata0", "prsnt")),
278 MPP_MODE(45,
279 MPP_FUNCTION(0x0, "gpio", NULL),
280 MPP_FUNCTION(0x2, "spi0", "cs2"),
281 MPP_FUNCTION(0x4, "pcie0", "rstoutn"),
282 MPP_FUNCTION(0x5, "led", "c2"),
283 MPP_FUNCTION(0x6, "spi1", "cs2")),
284 MPP_MODE(46,
285 MPP_FUNCTION(0x0, "gpio", NULL),
286 MPP_FUNCTION(0x1, "led", "p0"),
287 MPP_FUNCTION(0x2, "ge0", "txd0"),
288 MPP_FUNCTION(0x3, "ge1", "txd0"),
289 MPP_FUNCTION(0x6, "dev", "wen1")),
290 MPP_MODE(47,
291 MPP_FUNCTION(0x0, "gpio", NULL),
292 MPP_FUNCTION(0x1, "led", "p1"),
293 MPP_FUNCTION(0x2, "ge0", "txd1"),
294 MPP_FUNCTION(0x3, "ge1", "txd1"),
295 MPP_FUNCTION(0x5, "ptp", "triggen"),
296 MPP_FUNCTION(0x6, "dev", "ale0")),
297 MPP_MODE(48,
298 MPP_FUNCTION(0x0, "gpio", NULL),
299 MPP_FUNCTION(0x1, "led", "p2"),
300 MPP_FUNCTION(0x2, "ge0", "txd2"),
301 MPP_FUNCTION(0x3, "ge1", "txd2"),
302 MPP_FUNCTION(0x6, "dev", "ale1")),
303 MPP_MODE(49,
304 MPP_FUNCTION(0x0, "gpio", NULL),
305 MPP_FUNCTION(0x1, "led", "p3"),
306 MPP_FUNCTION(0x2, "ge0", "txd3"),
307 MPP_FUNCTION(0x3, "ge1", "txd3"),
308 MPP_FUNCTION(0x6, "dev", "a2")),
309 MPP_MODE(50,
310 MPP_FUNCTION(0x0, "gpio", NULL),
311 MPP_FUNCTION(0x1, "led", "c0"),
312 MPP_FUNCTION(0x2, "ge0", "rxd0"),
313 MPP_FUNCTION(0x3, "ge1", "rxd0"),
314 MPP_FUNCTION(0x5, "ptp", "eventreq"),
315 MPP_FUNCTION(0x6, "dev", "ad12")),
316 MPP_MODE(51,
317 MPP_FUNCTION(0x0, "gpio", NULL),
318 MPP_FUNCTION(0x1, "led", "c1"),
319 MPP_FUNCTION(0x2, "ge0", "rxd1"),
320 MPP_FUNCTION(0x3, "ge1", "rxd1"),
321 MPP_FUNCTION(0x6, "dev", "ad8")),
322 MPP_MODE(52,
323 MPP_FUNCTION(0x0, "gpio", NULL),
324 MPP_FUNCTION(0x1, "led", "c2"),
325 MPP_FUNCTION(0x2, "ge0", "rxd2"),
326 MPP_FUNCTION(0x3, "ge1", "rxd2"),
327 MPP_FUNCTION(0x5, "i2c0", "sda"),
328 MPP_FUNCTION(0x6, "dev", "ad9")),
329 MPP_MODE(53,
330 MPP_FUNCTION(0x0, "gpio", NULL),
331 MPP_FUNCTION(0x1, "pcie1", "rstoutn"),
332 MPP_FUNCTION(0x2, "ge0", "rxd3"),
333 MPP_FUNCTION(0x3, "ge1", "rxd3"),
334 MPP_FUNCTION(0x5, "i2c0", "sck"),
335 MPP_FUNCTION(0x6, "dev", "ad10")),
336 MPP_MODE(54,
337 MPP_FUNCTION(0x0, "gpio", NULL),
338 MPP_FUNCTION(0x1, "pcie0", "rstoutn"),
339 MPP_FUNCTION(0x2, "ge0", "rxctl"),
340 MPP_FUNCTION(0x3, "ge1", "rxctl"),
341 MPP_FUNCTION(0x6, "dev", "ad11")),
342 MPP_MODE(55,
343 MPP_FUNCTION(0x0, "gpio", NULL),
344 MPP_FUNCTION(0x2, "ge0", "rxclk"),
345 MPP_FUNCTION(0x3, "ge1", "rxclk"),
346 MPP_FUNCTION(0x6, "dev", "cs0")),
347 MPP_MODE(56,
348 MPP_FUNCTION(0x0, "gpio", NULL),
349 MPP_FUNCTION(0x2, "ge0", "txclkout"),
350 MPP_FUNCTION(0x3, "ge1", "txclkout"),
351 MPP_FUNCTION(0x6, "dev", "oe")),
352 MPP_MODE(57,
353 MPP_FUNCTION(0x0, "gpio", NULL),
354 MPP_FUNCTION(0x2, "ge0", "txctl"),
355 MPP_FUNCTION(0x3, "ge1", "txctl"),
356 MPP_FUNCTION(0x6, "dev", "wen0")),
357 MPP_MODE(58,
358 MPP_FUNCTION(0x0, "gpio", NULL),
359 MPP_FUNCTION(0x4, "led", "c0")),
360 MPP_MODE(59,
361 MPP_FUNCTION(0x0, "gpio", NULL),
362 MPP_FUNCTION(0x4, "led", "c1")),
363 MPP_MODE(60,
364 MPP_FUNCTION(0x0, "gpio", NULL),
365 MPP_FUNCTION(0x2, "uart1", "txd"),
366 MPP_FUNCTION(0x4, "led", "c2"),
367 MPP_FUNCTION(0x6, "dev", "ad13")),
368 MPP_MODE(61,
369 MPP_FUNCTION(0x0, "gpio", NULL),
370 MPP_FUNCTION(0x1, "i2c1", "sda"),
371 MPP_FUNCTION(0x2, "uart1", "rxd"),
372 MPP_FUNCTION(0x3, "spi1", "cs2"),
373 MPP_FUNCTION(0x4, "led", "p0"),
374 MPP_FUNCTION(0x6, "dev", "ad14")),
375 MPP_MODE(62,
376 MPP_FUNCTION(0x0, "gpio", NULL),
377 MPP_FUNCTION(0x1, "i2c1", "sck"),
378 MPP_FUNCTION(0x4, "led", "p1"),
379 MPP_FUNCTION(0x6, "dev", "ad15")),
380 MPP_MODE(63,
381 MPP_FUNCTION(0x0, "gpio", NULL),
382 MPP_FUNCTION(0x2, "ptp", "triggen"),
383 MPP_FUNCTION(0x4, "led", "p2"),
384 MPP_FUNCTION(0x6, "dev", "burst")),
385 MPP_MODE(64,
386 MPP_FUNCTION(0x0, "gpio", NULL),
387 MPP_FUNCTION(0x2, "dram", "vttctrl"),
388 MPP_FUNCTION(0x4, "led", "p3")),
389 MPP_MODE(65,
390 MPP_FUNCTION(0x0, "gpio", NULL),
391 MPP_FUNCTION(0x1, "sata1", "prsnt")),
392 MPP_MODE(66,
393 MPP_FUNCTION(0x0, "gpio", NULL),
394 MPP_FUNCTION(0x2, "ptp", "eventreq"),
395 MPP_FUNCTION(0x4, "spi1", "cs3"),
396 MPP_FUNCTION(0x5, "pcie0", "rstoutn"),
397 MPP_FUNCTION(0x6, "dev", "cs3")),
398};
399
400static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info;
401
402static struct of_device_id armada_375_pinctrl_of_match[] = {
403 { .compatible = "marvell,mv88f6720-pinctrl" },
404 { },
405};
406
407static struct mvebu_mpp_ctrl mv88f6720_mpp_controls[] = {
408 MPP_FUNC_CTRL(0, 69, NULL, armada_375_mpp_ctrl),
409};
410
411static struct pinctrl_gpio_range mv88f6720_mpp_gpio_ranges[] = {
412 MPP_GPIO_RANGE(0, 0, 0, 32),
413 MPP_GPIO_RANGE(1, 32, 32, 32),
414 MPP_GPIO_RANGE(2, 64, 64, 3),
415};
416
417static int armada_375_pinctrl_probe(struct platform_device *pdev)
418{
419 struct mvebu_pinctrl_soc_info *soc = &armada_375_pinctrl_info;
420 struct resource *res;
421
422 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423 mpp_base = devm_ioremap_resource(&pdev->dev, res);
424 if (IS_ERR(mpp_base))
425 return PTR_ERR(mpp_base);
426
427 soc->variant = 0; /* no variants for Armada 375 */
428 soc->controls = mv88f6720_mpp_controls;
429 soc->ncontrols = ARRAY_SIZE(mv88f6720_mpp_controls);
430 soc->modes = mv88f6720_mpp_modes;
431 soc->nmodes = ARRAY_SIZE(mv88f6720_mpp_modes);
432 soc->gpioranges = mv88f6720_mpp_gpio_ranges;
433 soc->ngpioranges = ARRAY_SIZE(mv88f6720_mpp_gpio_ranges);
434
435 pdev->dev.platform_data = soc;
436
437 return mvebu_pinctrl_probe(pdev);
438}
439
440static int armada_375_pinctrl_remove(struct platform_device *pdev)
441{
442 return mvebu_pinctrl_remove(pdev);
443}
444
445static struct platform_driver armada_375_pinctrl_driver = {
446 .driver = {
447 .name = "armada-375-pinctrl",
448 .owner = THIS_MODULE,
449 .of_match_table = of_match_ptr(armada_375_pinctrl_of_match),
450 },
451 .probe = armada_375_pinctrl_probe,
452 .remove = armada_375_pinctrl_remove,
453};
454
455module_platform_driver(armada_375_pinctrl_driver);
456
457MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
458MODULE_DESCRIPTION("Marvell Armada 375 pinctrl driver");
459MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
new file mode 100644
index 000000000000..1049f82fb62f
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
@@ -0,0 +1,462 @@
1/*
2 * Marvell Armada 380/385 pinctrl driver based on mvebu pinctrl core
3 *
4 * Copyright (C) 2013 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-mvebu.h"
24
25static void __iomem *mpp_base;
26
27static int armada_38x_mpp_ctrl_get(unsigned pid, unsigned long *config)
28{
29 return default_mpp_ctrl_get(mpp_base, pid, config);
30}
31
32static int armada_38x_mpp_ctrl_set(unsigned pid, unsigned long config)
33{
34 return default_mpp_ctrl_set(mpp_base, pid, config);
35}
36
37enum {
38 V_88F6810 = BIT(0),
39 V_88F6820 = BIT(1),
40 V_88F6828 = BIT(2),
41 V_88F6810_PLUS = (V_88F6810 | V_88F6820 | V_88F6828),
42 V_88F6820_PLUS = (V_88F6820 | V_88F6828),
43};
44
45static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
46 MPP_MODE(0,
47 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
48 MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6810_PLUS)),
49 MPP_MODE(1,
50 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
51 MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6810_PLUS)),
52 MPP_MODE(2,
53 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
54 MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6810_PLUS)),
55 MPP_MODE(3,
56 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
57 MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6810_PLUS)),
58 MPP_MODE(4,
59 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
60 MPP_VAR_FUNCTION(1, "ge", "mdc", V_88F6810_PLUS),
61 MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6810_PLUS),
62 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS)),
63 MPP_MODE(5,
64 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
65 MPP_VAR_FUNCTION(1, "ge", "mdio", V_88F6810_PLUS),
66 MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6810_PLUS),
67 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS)),
68 MPP_MODE(6,
69 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
70 MPP_VAR_FUNCTION(1, "ge0", "txclkout", V_88F6810_PLUS),
71 MPP_VAR_FUNCTION(2, "ge0", "crs", V_88F6810_PLUS),
72 MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6810_PLUS)),
73 MPP_MODE(7,
74 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
75 MPP_VAR_FUNCTION(1, "ge0", "txd0", V_88F6810_PLUS),
76 MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6810_PLUS)),
77 MPP_MODE(8,
78 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
79 MPP_VAR_FUNCTION(1, "ge0", "txd1", V_88F6810_PLUS),
80 MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6810_PLUS)),
81 MPP_MODE(9,
82 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
83 MPP_VAR_FUNCTION(1, "ge0", "txd2", V_88F6810_PLUS),
84 MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6810_PLUS)),
85 MPP_MODE(10,
86 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
87 MPP_VAR_FUNCTION(1, "ge0", "txd3", V_88F6810_PLUS),
88 MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6810_PLUS)),
89 MPP_MODE(11,
90 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
91 MPP_VAR_FUNCTION(1, "ge0", "txctl", V_88F6810_PLUS),
92 MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6810_PLUS)),
93 MPP_MODE(12,
94 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
95 MPP_VAR_FUNCTION(1, "ge0", "rxd0", V_88F6810_PLUS),
96 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
97 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
98 MPP_VAR_FUNCTION(4, "spi0", "cs1", V_88F6810_PLUS),
99 MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6810_PLUS)),
100 MPP_MODE(13,
101 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
102 MPP_VAR_FUNCTION(1, "ge0", "rxd1", V_88F6810_PLUS),
103 MPP_VAR_FUNCTION(2, "pcie0", "clkreq", V_88F6810_PLUS),
104 MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
105 MPP_VAR_FUNCTION(4, "spi0", "cs2", V_88F6810_PLUS),
106 MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6810_PLUS)),
107 MPP_MODE(14,
108 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
109 MPP_VAR_FUNCTION(1, "ge0", "rxd2", V_88F6810_PLUS),
110 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
111 MPP_VAR_FUNCTION(3, "m", "vtt_ctrl", V_88F6810_PLUS),
112 MPP_VAR_FUNCTION(4, "spi0", "cs3", V_88F6810_PLUS),
113 MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6810_PLUS)),
114 MPP_MODE(15,
115 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
116 MPP_VAR_FUNCTION(1, "ge0", "rxd3", V_88F6810_PLUS),
117 MPP_VAR_FUNCTION(2, "ge", "mdc slave", V_88F6810_PLUS),
118 MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
119 MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6810_PLUS),
120 MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)),
121 MPP_MODE(16,
122 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
123 MPP_VAR_FUNCTION(1, "ge0", "rxctl", V_88F6810_PLUS),
124 MPP_VAR_FUNCTION(2, "ge", "mdio slave", V_88F6810_PLUS),
125 MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
126 MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6810_PLUS),
127 MPP_VAR_FUNCTION(5, "pcie0", "clkreq", V_88F6810_PLUS)),
128 MPP_MODE(17,
129 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
130 MPP_VAR_FUNCTION(1, "ge0", "rxclk", V_88F6810_PLUS),
131 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
132 MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
133 MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6810_PLUS),
134 MPP_VAR_FUNCTION(5, "sata1", "prsnt", V_88F6810_PLUS)),
135 MPP_MODE(18,
136 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
137 MPP_VAR_FUNCTION(1, "ge0", "rxerr", V_88F6810_PLUS),
138 MPP_VAR_FUNCTION(2, "ptp", "trig_gen", V_88F6810_PLUS),
139 MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
140 MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6810_PLUS),
141 MPP_VAR_FUNCTION(5, "pcie1", "rstout", V_88F6820_PLUS)),
142 MPP_MODE(19,
143 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
144 MPP_VAR_FUNCTION(1, "ge0", "col", V_88F6810_PLUS),
145 MPP_VAR_FUNCTION(2, "ptp", "event_req", V_88F6810_PLUS),
146 MPP_VAR_FUNCTION(3, "pcie0", "clkreq", V_88F6810_PLUS),
147 MPP_VAR_FUNCTION(4, "sata1", "prsnt", V_88F6810_PLUS),
148 MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6810_PLUS)),
149 MPP_MODE(20,
150 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
151 MPP_VAR_FUNCTION(1, "ge0", "txclk", V_88F6810_PLUS),
152 MPP_VAR_FUNCTION(2, "ptp", "clk", V_88F6810_PLUS),
153 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
154 MPP_VAR_FUNCTION(4, "sata0", "prsnt", V_88F6810_PLUS),
155 MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6810_PLUS)),
156 MPP_MODE(21,
157 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
158 MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6810_PLUS),
159 MPP_VAR_FUNCTION(2, "ge1", "rxd0", V_88F6810_PLUS),
160 MPP_VAR_FUNCTION(3, "sata0", "prsnt", V_88F6810_PLUS),
161 MPP_VAR_FUNCTION(4, "sd0", "cmd", V_88F6810_PLUS),
162 MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6810_PLUS)),
163 MPP_MODE(22,
164 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
165 MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6810_PLUS),
166 MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6810_PLUS)),
167 MPP_MODE(23,
168 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
169 MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6810_PLUS),
170 MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6810_PLUS)),
171 MPP_MODE(24,
172 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
173 MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6810_PLUS),
174 MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6810_PLUS),
175 MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6810_PLUS),
176 MPP_VAR_FUNCTION(4, "sd0", "d4", V_88F6810_PLUS),
177 MPP_VAR_FUNCTION(5, "dev", "ready", V_88F6810_PLUS)),
178 MPP_MODE(25,
179 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
180 MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6810_PLUS),
181 MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6810_PLUS),
182 MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6810_PLUS),
183 MPP_VAR_FUNCTION(4, "sd0", "d5", V_88F6810_PLUS),
184 MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6810_PLUS)),
185 MPP_MODE(26,
186 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
187 MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6810_PLUS),
188 MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6810_PLUS),
189 MPP_VAR_FUNCTION(4, "sd0", "d6", V_88F6810_PLUS),
190 MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6810_PLUS)),
191 MPP_MODE(27,
192 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
193 MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6810_PLUS),
194 MPP_VAR_FUNCTION(2, "ge1", "txclkout", V_88F6810_PLUS),
195 MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6810_PLUS),
196 MPP_VAR_FUNCTION(4, "sd0", "d7", V_88F6810_PLUS),
197 MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6810_PLUS)),
198 MPP_MODE(28,
199 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
200 MPP_VAR_FUNCTION(2, "ge1", "txd0", V_88F6810_PLUS),
201 MPP_VAR_FUNCTION(4, "sd0", "clk", V_88F6810_PLUS),
202 MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6810_PLUS)),
203 MPP_MODE(29,
204 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
205 MPP_VAR_FUNCTION(2, "ge1", "txd1", V_88F6810_PLUS),
206 MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6810_PLUS)),
207 MPP_MODE(30,
208 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
209 MPP_VAR_FUNCTION(2, "ge1", "txd2", V_88F6810_PLUS),
210 MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6810_PLUS)),
211 MPP_MODE(31,
212 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
213 MPP_VAR_FUNCTION(2, "ge1", "txd3", V_88F6810_PLUS),
214 MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6810_PLUS)),
215 MPP_MODE(32,
216 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
217 MPP_VAR_FUNCTION(2, "ge1", "txctl", V_88F6810_PLUS),
218 MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6810_PLUS)),
219 MPP_MODE(33,
220 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
221 MPP_VAR_FUNCTION(1, "m", "decc_err", V_88F6810_PLUS),
222 MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6810_PLUS)),
223 MPP_MODE(34,
224 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
225 MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6810_PLUS)),
226 MPP_MODE(35,
227 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
228 MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
229 MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6810_PLUS)),
230 MPP_MODE(36,
231 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
232 MPP_VAR_FUNCTION(1, "ptp", "trig_gen", V_88F6810_PLUS),
233 MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6810_PLUS)),
234 MPP_MODE(37,
235 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
236 MPP_VAR_FUNCTION(1, "ptp", "clk", V_88F6810_PLUS),
237 MPP_VAR_FUNCTION(2, "ge1", "rxclk", V_88F6810_PLUS),
238 MPP_VAR_FUNCTION(4, "sd0", "d3", V_88F6810_PLUS),
239 MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6810_PLUS)),
240 MPP_MODE(38,
241 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
242 MPP_VAR_FUNCTION(1, "ptp", "event_req", V_88F6810_PLUS),
243 MPP_VAR_FUNCTION(2, "ge1", "rxd1", V_88F6810_PLUS),
244 MPP_VAR_FUNCTION(3, "ref", "clk_out0", V_88F6810_PLUS),
245 MPP_VAR_FUNCTION(4, "sd0", "d0", V_88F6810_PLUS),
246 MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6810_PLUS)),
247 MPP_MODE(39,
248 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
249 MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6810_PLUS),
250 MPP_VAR_FUNCTION(2, "ge1", "rxd2", V_88F6810_PLUS),
251 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
252 MPP_VAR_FUNCTION(4, "sd0", "d1", V_88F6810_PLUS),
253 MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6810_PLUS)),
254 MPP_MODE(40,
255 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
256 MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6810_PLUS),
257 MPP_VAR_FUNCTION(2, "ge1", "rxd3", V_88F6810_PLUS),
258 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
259 MPP_VAR_FUNCTION(4, "sd0", "d2", V_88F6810_PLUS),
260 MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6810_PLUS)),
261 MPP_MODE(41,
262 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
263 MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6810_PLUS),
264 MPP_VAR_FUNCTION(2, "ge1", "rxctl", V_88F6810_PLUS),
265 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6810_PLUS),
266 MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6810_PLUS),
267 MPP_VAR_FUNCTION(5, "dev", "burst/last", V_88F6810_PLUS)),
268 MPP_MODE(42,
269 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
270 MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6810_PLUS),
271 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6810_PLUS),
272 MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6810_PLUS)),
273 MPP_MODE(43,
274 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
275 MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6810_PLUS),
276 MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS),
277 MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
278 MPP_VAR_FUNCTION(4, "pcie0", "rstout", V_88F6810_PLUS),
279 MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6810_PLUS)),
280 MPP_MODE(44,
281 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
282 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
283 MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
284 MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
285 MPP_VAR_FUNCTION(4, "sata3", "prsnt", V_88F6828),
286 MPP_VAR_FUNCTION(5, "pcie0", "rstout", V_88F6810_PLUS)),
287 MPP_MODE(45,
288 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
289 MPP_VAR_FUNCTION(1, "ref", "clk_out0", V_88F6810_PLUS),
290 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
291 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
292 MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS),
293 MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)),
294 MPP_MODE(46,
295 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
296 MPP_VAR_FUNCTION(1, "ref", "clk_out1", V_88F6810_PLUS),
297 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6810_PLUS),
298 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
299 MPP_VAR_FUNCTION(4, "pcie2", "rstout", V_88F6810_PLUS),
300 MPP_VAR_FUNCTION(5, "pcie3", "rstout", V_88F6810_PLUS)),
301 MPP_MODE(47,
302 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
303 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
304 MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
305 MPP_VAR_FUNCTION(3, "sata2", "prsnt", V_88F6828),
306 MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6810_PLUS),
307 MPP_VAR_FUNCTION(5, "sata3", "prsnt", V_88F6828)),
308 MPP_MODE(48,
309 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
310 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
311 MPP_VAR_FUNCTION(2, "m", "vtt_ctrl", V_88F6810_PLUS),
312 MPP_VAR_FUNCTION(3, "tdm2c", "pclk", V_88F6810_PLUS),
313 MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6810_PLUS),
314 MPP_VAR_FUNCTION(5, "sd0", "d4", V_88F6810_PLUS)),
315 MPP_MODE(49,
316 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
317 MPP_VAR_FUNCTION(1, "sata2", "prsnt", V_88F6828),
318 MPP_VAR_FUNCTION(2, "sata3", "prsnt", V_88F6828),
319 MPP_VAR_FUNCTION(3, "tdm2c", "fsync", V_88F6810_PLUS),
320 MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6810_PLUS),
321 MPP_VAR_FUNCTION(5, "sd0", "d5", V_88F6810_PLUS)),
322 MPP_MODE(50,
323 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
324 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
325 MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS),
326 MPP_VAR_FUNCTION(3, "tdm2c", "drx", V_88F6810_PLUS),
327 MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6810_PLUS),
328 MPP_VAR_FUNCTION(5, "sd0", "cmd", V_88F6810_PLUS)),
329 MPP_MODE(51,
330 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
331 MPP_VAR_FUNCTION(3, "tdm2c", "dtx", V_88F6810_PLUS),
332 MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6810_PLUS),
333 MPP_VAR_FUNCTION(5, "m", "decc_err", V_88F6810_PLUS)),
334 MPP_MODE(52,
335 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
336 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
337 MPP_VAR_FUNCTION(2, "pcie1", "rstout", V_88F6820_PLUS),
338 MPP_VAR_FUNCTION(3, "tdm2c", "intn", V_88F6810_PLUS),
339 MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6810_PLUS),
340 MPP_VAR_FUNCTION(5, "sd0", "d6", V_88F6810_PLUS)),
341 MPP_MODE(53,
342 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
343 MPP_VAR_FUNCTION(1, "sata1", "prsnt", V_88F6810_PLUS),
344 MPP_VAR_FUNCTION(2, "sata0", "prsnt", V_88F6810_PLUS),
345 MPP_VAR_FUNCTION(3, "tdm2c", "rstn", V_88F6810_PLUS),
346 MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6810_PLUS),
347 MPP_VAR_FUNCTION(5, "sd0", "d7", V_88F6810_PLUS)),
348 MPP_MODE(54,
349 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
350 MPP_VAR_FUNCTION(1, "sata0", "prsnt", V_88F6810_PLUS),
351 MPP_VAR_FUNCTION(2, "sata1", "prsnt", V_88F6810_PLUS),
352 MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6810_PLUS),
353 MPP_VAR_FUNCTION(4, "pcie1", "rstout", V_88F6820_PLUS),
354 MPP_VAR_FUNCTION(5, "sd0", "d3", V_88F6810_PLUS)),
355 MPP_MODE(55,
356 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
357 MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6810_PLUS),
358 MPP_VAR_FUNCTION(2, "ge", "mdio", V_88F6810_PLUS),
359 MPP_VAR_FUNCTION(3, "pcie1", "clkreq", V_88F6820_PLUS),
360 MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6810_PLUS),
361 MPP_VAR_FUNCTION(5, "sd0", "d0", V_88F6810_PLUS)),
362 MPP_MODE(56,
363 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
364 MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6810_PLUS),
365 MPP_VAR_FUNCTION(2, "ge", "mdc", V_88F6810_PLUS),
366 MPP_VAR_FUNCTION(3, "m", "decc_err", V_88F6810_PLUS),
367 MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6810_PLUS)),
368 MPP_MODE(57,
369 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
370 MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6810_PLUS),
371 MPP_VAR_FUNCTION(5, "sd0", "clk", V_88F6810_PLUS)),
372 MPP_MODE(58,
373 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
374 MPP_VAR_FUNCTION(1, "pcie1", "clkreq", V_88F6820_PLUS),
375 MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6810_PLUS),
376 MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6810_PLUS),
377 MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6810_PLUS),
378 MPP_VAR_FUNCTION(5, "sd0", "d1", V_88F6810_PLUS)),
379 MPP_MODE(59,
380 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6810_PLUS),
381 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6810_PLUS),
382 MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6810_PLUS),
383 MPP_VAR_FUNCTION(3, "pcie1", "rstout", V_88F6820_PLUS),
384 MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6810_PLUS),
385 MPP_VAR_FUNCTION(5, "sd0", "d2", V_88F6810_PLUS)),
386};
387
388static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info;
389
390static struct of_device_id armada_38x_pinctrl_of_match[] = {
391 {
392 .compatible = "marvell,mv88f6810-pinctrl",
393 .data = (void *) V_88F6810,
394 },
395 {
396 .compatible = "marvell,mv88f6820-pinctrl",
397 .data = (void *) V_88F6820,
398 },
399 {
400 .compatible = "marvell,mv88f6828-pinctrl",
401 .data = (void *) V_88F6828,
402 },
403 { },
404};
405
406static struct mvebu_mpp_ctrl armada_38x_mpp_controls[] = {
407 MPP_FUNC_CTRL(0, 59, NULL, armada_38x_mpp_ctrl),
408};
409
410static struct pinctrl_gpio_range armada_38x_mpp_gpio_ranges[] = {
411 MPP_GPIO_RANGE(0, 0, 0, 32),
412 MPP_GPIO_RANGE(1, 32, 32, 27),
413};
414
415static int armada_38x_pinctrl_probe(struct platform_device *pdev)
416{
417 struct mvebu_pinctrl_soc_info *soc = &armada_38x_pinctrl_info;
418 const struct of_device_id *match =
419 of_match_device(armada_38x_pinctrl_of_match, &pdev->dev);
420 struct resource *res;
421
422 if (!match)
423 return -ENODEV;
424
425 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
426 mpp_base = devm_ioremap_resource(&pdev->dev, res);
427 if (IS_ERR(mpp_base))
428 return PTR_ERR(mpp_base);
429
430 soc->variant = (unsigned) match->data & 0xff;
431 soc->controls = armada_38x_mpp_controls;
432 soc->ncontrols = ARRAY_SIZE(armada_38x_mpp_controls);
433 soc->gpioranges = armada_38x_mpp_gpio_ranges;
434 soc->ngpioranges = ARRAY_SIZE(armada_38x_mpp_gpio_ranges);
435 soc->modes = armada_38x_mpp_modes;
436 soc->nmodes = armada_38x_mpp_controls[0].npins;
437
438 pdev->dev.platform_data = soc;
439
440 return mvebu_pinctrl_probe(pdev);
441}
442
443static int armada_38x_pinctrl_remove(struct platform_device *pdev)
444{
445 return mvebu_pinctrl_remove(pdev);
446}
447
448static struct platform_driver armada_38x_pinctrl_driver = {
449 .driver = {
450 .name = "armada-38x-pinctrl",
451 .owner = THIS_MODULE,
452 .of_match_table = of_match_ptr(armada_38x_pinctrl_of_match),
453 },
454 .probe = armada_38x_pinctrl_probe,
455 .remove = armada_38x_pinctrl_remove,
456};
457
458module_platform_driver(armada_38x_pinctrl_driver);
459
460MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
461MODULE_DESCRIPTION("Marvell Armada 38x pinctrl driver");
462MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index 843a51f9d129..de311129f7a0 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -33,6 +33,18 @@
33 33
34#include "pinctrl-mvebu.h" 34#include "pinctrl-mvebu.h"
35 35
36static void __iomem *mpp_base;
37
38static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config)
39{
40 return default_mpp_ctrl_get(mpp_base, pid, config);
41}
42
43static int armada_xp_mpp_ctrl_set(unsigned pid, unsigned long config)
44{
45 return default_mpp_ctrl_set(mpp_base, pid, config);
46}
47
36enum armada_xp_variant { 48enum armada_xp_variant {
37 V_MV78230 = BIT(0), 49 V_MV78230 = BIT(0),
38 V_MV78260 = BIT(1), 50 V_MV78260 = BIT(1),
@@ -366,7 +378,7 @@ static struct of_device_id armada_xp_pinctrl_of_match[] = {
366}; 378};
367 379
368static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = { 380static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
369 MPP_REG_CTRL(0, 48), 381 MPP_FUNC_CTRL(0, 48, NULL, armada_xp_mpp_ctrl),
370}; 382};
371 383
372static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = { 384static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
@@ -375,7 +387,7 @@ static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
375}; 387};
376 388
377static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = { 389static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
378 MPP_REG_CTRL(0, 66), 390 MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl),
379}; 391};
380 392
381static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = { 393static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
@@ -385,7 +397,7 @@ static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
385}; 397};
386 398
387static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = { 399static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
388 MPP_REG_CTRL(0, 66), 400 MPP_FUNC_CTRL(0, 66, NULL, armada_xp_mpp_ctrl),
389}; 401};
390 402
391static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { 403static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
@@ -399,10 +411,16 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev)
399 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; 411 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
400 const struct of_device_id *match = 412 const struct of_device_id *match =
401 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev); 413 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
414 struct resource *res;
402 415
403 if (!match) 416 if (!match)
404 return -ENODEV; 417 return -ENODEV;
405 418
419 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
420 mpp_base = devm_ioremap_resource(&pdev->dev, res);
421 if (IS_ERR(mpp_base))
422 return PTR_ERR(mpp_base);
423
406 soc->variant = (unsigned) match->data & 0xff; 424 soc->variant = (unsigned) match->data & 0xff;
407 425
408 switch (soc->variant) { 426 switch (soc->variant) {
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index 47268393af34..9e7ff651c018 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -18,107 +18,122 @@
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/of_device.h> 20#include <linux/of_device.h>
21#include <linux/mfd/syscon.h>
21#include <linux/pinctrl/pinctrl.h> 22#include <linux/pinctrl/pinctrl.h>
23#include <linux/regmap.h>
22 24
23#include "pinctrl-mvebu.h" 25#include "pinctrl-mvebu.h"
24 26
25#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000) 27/* Internal registers can be configured at any 1 MiB aligned address */
26#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) 28#define INT_REGS_MASK ~(SZ_1M - 1)
27#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 29#define MPP4_REGS_OFFS 0xd0440
28#define DOVE_AU0_AC97_SEL BIT(16) 30#define PMU_REGS_OFFS 0xd802c
29#define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C) 31#define GC_REGS_OFFS 0xe802c
30#define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030) 32
31#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 33/* MPP Base registers */
32#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) 34#define PMU_MPP_GENERAL_CTRL 0x10
33#define DOVE_TWSI_ENABLE_OPTION1 BIT(7) 35#define AU0_AC97_SEL BIT(16)
34#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) 36
35#define DOVE_TWSI_ENABLE_OPTION2 BIT(20) 37/* MPP Control 4 register */
36#define DOVE_TWSI_ENABLE_OPTION3 BIT(21) 38#define SPI_GPIO_SEL BIT(5)
37#define DOVE_TWSI_OPTION3_GPIO BIT(22) 39#define UART1_GPIO_SEL BIT(4)
38#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) 40#define AU1_GPIO_SEL BIT(3)
39#define DOVE_SSP_ON_AU1 BIT(0) 41#define CAM_GPIO_SEL BIT(2)
40#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) 42#define SD1_GPIO_SEL BIT(1)
41#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1) 43#define SD0_GPIO_SEL BIT(0)
42#define DOVE_NAND_GPIO_EN BIT(0) 44
43#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) 45/* PMU Signal Select registers */
44#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 46#define PMU_SIGNAL_SELECT_0 0x00
45#define DOVE_SPI_GPIO_SEL BIT(5) 47#define PMU_SIGNAL_SELECT_1 0x04
46#define DOVE_UART1_GPIO_SEL BIT(4) 48
47#define DOVE_AU1_GPIO_SEL BIT(3) 49/* Global Config regmap registers */
48#define DOVE_CAM_GPIO_SEL BIT(2) 50#define GLOBAL_CONFIG_1 0x00
49#define DOVE_SD1_GPIO_SEL BIT(1) 51#define TWSI_ENABLE_OPTION1 BIT(7)
50#define DOVE_SD0_GPIO_SEL BIT(0) 52#define GLOBAL_CONFIG_2 0x04
51 53#define TWSI_ENABLE_OPTION2 BIT(20)
52#define MPPS_PER_REG 8 54#define TWSI_ENABLE_OPTION3 BIT(21)
53#define MPP_BITS 4 55#define TWSI_OPTION3_GPIO BIT(22)
54#define MPP_MASK 0xf 56#define SSP_CTRL_STATUS_1 0x08
57#define SSP_ON_AU1 BIT(0)
58#define MPP_GENERAL_CONFIG 0x10
59#define AU1_SPDIFO_GPIO_EN BIT(1)
60#define NAND_GPIO_EN BIT(0)
55 61
56#define CONFIG_PMU BIT(4) 62#define CONFIG_PMU BIT(4)
57 63
58static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 64static void __iomem *mpp_base;
59 unsigned long *config) 65static void __iomem *mpp4_base;
66static void __iomem *pmu_base;
67static struct regmap *gconfmap;
68
69static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config)
70{
71 return default_mpp_ctrl_get(mpp_base, pid, config);
72}
73
74static int dove_mpp_ctrl_set(unsigned pid, unsigned long config)
60{ 75{
61 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 76 return default_mpp_ctrl_set(mpp_base, pid, config);
62 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 77}
63 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 78
79static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config)
80{
81 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
82 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
83 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
64 unsigned long func; 84 unsigned long func;
65 85
66 if (pmu & (1 << ctrl->pid)) { 86 if ((pmu & BIT(pid)) == 0)
67 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 87 return default_mpp_ctrl_get(mpp_base, pid, config);
68 *config = (func >> shift) & MPP_MASK; 88
69 *config |= CONFIG_PMU; 89 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
70 } else { 90 *config = (func >> shift) & MVEBU_MPP_MASK;
71 func = readl(DOVE_MPP_VIRT_BASE + off); 91 *config |= CONFIG_PMU;
72 *config = (func >> shift) & MPP_MASK; 92
73 }
74 return 0; 93 return 0;
75} 94}
76 95
77static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 96static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config)
78 unsigned long config)
79{ 97{
80 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS; 98 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
81 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS; 99 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
82 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 100 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
83 unsigned long func; 101 unsigned long func;
84 102
85 if (config & CONFIG_PMU) { 103 if ((config & CONFIG_PMU) == 0) {
86 writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL); 104 writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
87 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off); 105 return default_mpp_ctrl_set(mpp_base, pid, config);
88 func &= ~(MPP_MASK << shift);
89 func |= (config & MPP_MASK) << shift;
90 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off);
91 } else {
92 writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
93 func = readl(DOVE_MPP_VIRT_BASE + off);
94 func &= ~(MPP_MASK << shift);
95 func |= (config & MPP_MASK) << shift;
96 writel(func, DOVE_MPP_VIRT_BASE + off);
97 } 106 }
107
108 writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
109 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
110 func &= ~(MVEBU_MPP_MASK << shift);
111 func |= (config & MVEBU_MPP_MASK) << shift;
112 writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
113
98 return 0; 114 return 0;
99} 115}
100 116
101static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 117static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config)
102 unsigned long *config)
103{ 118{
104 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 119 unsigned long mpp4 = readl(mpp4_base);
105 unsigned long mask; 120 unsigned long mask;
106 121
107 switch (ctrl->pid) { 122 switch (pid) {
108 case 24: /* mpp_camera */ 123 case 24: /* mpp_camera */
109 mask = DOVE_CAM_GPIO_SEL; 124 mask = CAM_GPIO_SEL;
110 break; 125 break;
111 case 40: /* mpp_sdio0 */ 126 case 40: /* mpp_sdio0 */
112 mask = DOVE_SD0_GPIO_SEL; 127 mask = SD0_GPIO_SEL;
113 break; 128 break;
114 case 46: /* mpp_sdio1 */ 129 case 46: /* mpp_sdio1 */
115 mask = DOVE_SD1_GPIO_SEL; 130 mask = SD1_GPIO_SEL;
116 break; 131 break;
117 case 58: /* mpp_spi0 */ 132 case 58: /* mpp_spi0 */
118 mask = DOVE_SPI_GPIO_SEL; 133 mask = SPI_GPIO_SEL;
119 break; 134 break;
120 case 62: /* mpp_uart1 */ 135 case 62: /* mpp_uart1 */
121 mask = DOVE_UART1_GPIO_SEL; 136 mask = UART1_GPIO_SEL;
122 break; 137 break;
123 default: 138 default:
124 return -EINVAL; 139 return -EINVAL;
@@ -129,27 +144,26 @@ static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
129 return 0; 144 return 0;
130} 145}
131 146
132static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 147static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config)
133 unsigned long config)
134{ 148{
135 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 149 unsigned long mpp4 = readl(mpp4_base);
136 unsigned long mask; 150 unsigned long mask;
137 151
138 switch (ctrl->pid) { 152 switch (pid) {
139 case 24: /* mpp_camera */ 153 case 24: /* mpp_camera */
140 mask = DOVE_CAM_GPIO_SEL; 154 mask = CAM_GPIO_SEL;
141 break; 155 break;
142 case 40: /* mpp_sdio0 */ 156 case 40: /* mpp_sdio0 */
143 mask = DOVE_SD0_GPIO_SEL; 157 mask = SD0_GPIO_SEL;
144 break; 158 break;
145 case 46: /* mpp_sdio1 */ 159 case 46: /* mpp_sdio1 */
146 mask = DOVE_SD1_GPIO_SEL; 160 mask = SD1_GPIO_SEL;
147 break; 161 break;
148 case 58: /* mpp_spi0 */ 162 case 58: /* mpp_spi0 */
149 mask = DOVE_SPI_GPIO_SEL; 163 mask = SPI_GPIO_SEL;
150 break; 164 break;
151 case 62: /* mpp_uart1 */ 165 case 62: /* mpp_uart1 */
152 mask = DOVE_UART1_GPIO_SEL; 166 mask = UART1_GPIO_SEL;
153 break; 167 break;
154 default: 168 default:
155 return -EINVAL; 169 return -EINVAL;
@@ -159,74 +173,69 @@ static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
159 if (config) 173 if (config)
160 mpp4 |= mask; 174 mpp4 |= mask;
161 175
162 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 176 writel(mpp4, mpp4_base);
163 177
164 return 0; 178 return 0;
165} 179}
166 180
167static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 181static int dove_nand_ctrl_get(unsigned pid, unsigned long *config)
168 unsigned long *config)
169{ 182{
170 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 183 unsigned int gmpp;
171 184
172 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0); 185 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
186 *config = ((gmpp & NAND_GPIO_EN) != 0);
173 187
174 return 0; 188 return 0;
175} 189}
176 190
177static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 191static int dove_nand_ctrl_set(unsigned pid, unsigned long config)
178 unsigned long config)
179{ 192{
180 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 193 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
181 194 NAND_GPIO_EN,
182 gmpp &= ~DOVE_NAND_GPIO_EN; 195 (config) ? NAND_GPIO_EN : 0);
183 if (config)
184 gmpp |= DOVE_NAND_GPIO_EN;
185
186 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
187
188 return 0; 196 return 0;
189} 197}
190 198
191static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 199static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config)
192 unsigned long *config)
193{ 200{
194 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 201 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
195 202
196 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0); 203 *config = ((pmu & AU0_AC97_SEL) != 0);
197 204
198 return 0; 205 return 0;
199} 206}
200 207
201static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 208static int dove_audio0_ctrl_set(unsigned pid, unsigned long config)
202 unsigned long config)
203{ 209{
204 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL); 210 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
205 211
206 pmu &= ~DOVE_AU0_AC97_SEL; 212 pmu &= ~AU0_AC97_SEL;
207 if (config) 213 if (config)
208 pmu |= DOVE_AU0_AC97_SEL; 214 pmu |= AU0_AC97_SEL;
209 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL); 215 writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL);
210 216
211 return 0; 217 return 0;
212} 218}
213 219
214static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 220static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config)
215 unsigned long *config)
216{ 221{
217 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 222 unsigned int mpp4 = readl(mpp4_base);
218 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1); 223 unsigned int sspc1;
219 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE); 224 unsigned int gmpp;
220 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 225 unsigned int gcfg2;
226
227 regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
228 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
229 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
221 230
222 *config = 0; 231 *config = 0;
223 if (mpp4 & DOVE_AU1_GPIO_SEL) 232 if (mpp4 & AU1_GPIO_SEL)
224 *config |= BIT(3); 233 *config |= BIT(3);
225 if (sspc1 & DOVE_SSP_ON_AU1) 234 if (sspc1 & SSP_ON_AU1)
226 *config |= BIT(2); 235 *config |= BIT(2);
227 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN) 236 if (gmpp & AU1_SPDIFO_GPIO_EN)
228 *config |= BIT(1); 237 *config |= BIT(1);
229 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO) 238 if (gcfg2 & TWSI_OPTION3_GPIO)
230 *config |= BIT(0); 239 *config |= BIT(0);
231 240
232 /* SSP/TWSI only if I2S1 not set*/ 241 /* SSP/TWSI only if I2S1 not set*/
@@ -238,35 +247,24 @@ static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
238 return 0; 247 return 0;
239} 248}
240 249
241static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 250static int dove_audio1_ctrl_set(unsigned pid, unsigned long config)
242 unsigned long config)
243{ 251{
244 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE); 252 unsigned int mpp4 = readl(mpp4_base);
245 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
246 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
247 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
248 253
249 /* 254 mpp4 &= ~AU1_GPIO_SEL;
250 * clear all audio1 related bits before configure
251 */
252 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO;
253 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN;
254 sspc1 &= ~DOVE_SSP_ON_AU1;
255 mpp4 &= ~DOVE_AU1_GPIO_SEL;
256
257 if (config & BIT(0))
258 gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
259 if (config & BIT(1))
260 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
261 if (config & BIT(2))
262 sspc1 |= DOVE_SSP_ON_AU1;
263 if (config & BIT(3)) 255 if (config & BIT(3))
264 mpp4 |= DOVE_AU1_GPIO_SEL; 256 mpp4 |= AU1_GPIO_SEL;
265 257 writel(mpp4, mpp4_base);
266 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE); 258
267 writel(sspc1, DOVE_SSP_CTRL_STATUS_1); 259 regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
268 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE); 260 SSP_ON_AU1,
269 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 261 (config & BIT(2)) ? SSP_ON_AU1 : 0);
262 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
263 AU1_SPDIFO_GPIO_EN,
264 (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
265 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
266 TWSI_OPTION3_GPIO,
267 (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
270 268
271 return 0; 269 return 0;
272} 270}
@@ -276,11 +274,11 @@ static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
276 * break other functions. If you require all mpps as gpio 274 * break other functions. If you require all mpps as gpio
277 * enforce gpio setting by pinctrl mapping. 275 * enforce gpio setting by pinctrl mapping.
278 */ 276 */
279static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid) 277static int dove_audio1_ctrl_gpio_req(unsigned pid)
280{ 278{
281 unsigned long config; 279 unsigned long config;
282 280
283 dove_audio1_ctrl_get(ctrl, &config); 281 dove_audio1_ctrl_get(pid, &config);
284 282
285 switch (config) { 283 switch (config) {
286 case 0x02: /* i2s1 : gpio[56:57] */ 284 case 0x02: /* i2s1 : gpio[56:57] */
@@ -303,76 +301,62 @@ static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
303} 301}
304 302
305/* mpp[52:57] has gpio pins capable of in and out */ 303/* mpp[52:57] has gpio pins capable of in and out */
306static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid, 304static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input)
307 bool input)
308{ 305{
309 if (pid < 52 || pid > 57) 306 if (pid < 52 || pid > 57)
310 return -ENOTSUPP; 307 return -ENOTSUPP;
311 return 0; 308 return 0;
312} 309}
313 310
314static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl, 311static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config)
315 unsigned long *config)
316{ 312{
317 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 313 unsigned int gcfg1;
318 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 314 unsigned int gcfg2;
315
316 regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
317 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
319 318
320 *config = 0; 319 *config = 0;
321 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1) 320 if (gcfg1 & TWSI_ENABLE_OPTION1)
322 *config = 1; 321 *config = 1;
323 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2) 322 else if (gcfg2 & TWSI_ENABLE_OPTION2)
324 *config = 2; 323 *config = 2;
325 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3) 324 else if (gcfg2 & TWSI_ENABLE_OPTION3)
326 *config = 3; 325 *config = 3;
327 326
328 return 0; 327 return 0;
329} 328}
330 329
331static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl, 330static int dove_twsi_ctrl_set(unsigned pid, unsigned long config)
332 unsigned long config)
333{ 331{
334 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1); 332 unsigned int gcfg1 = 0;
335 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 333 unsigned int gcfg2 = 0;
336
337 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
338 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3);
339 334
340 switch (config) { 335 switch (config) {
341 case 1: 336 case 1:
342 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1; 337 gcfg1 = TWSI_ENABLE_OPTION1;
343 break; 338 break;
344 case 2: 339 case 2:
345 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2; 340 gcfg2 = TWSI_ENABLE_OPTION2;
346 break; 341 break;
347 case 3: 342 case 3:
348 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3; 343 gcfg2 = TWSI_ENABLE_OPTION3;
349 break; 344 break;
350 } 345 }
351 346
352 writel(gcfg1, DOVE_GLOBAL_CONFIG_1); 347 regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
353 writel(gcfg2, DOVE_GLOBAL_CONFIG_2); 348 TWSI_ENABLE_OPTION1,
349 gcfg1);
350 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
351 TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
352 gcfg2);
354 353
355 return 0; 354 return 0;
356} 355}
357 356
358static struct mvebu_mpp_ctrl dove_mpp_controls[] = { 357static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
359 MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl), 358 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
360 MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl), 359 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl),
361 MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
362 MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
363 MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
364 MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
365 MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
366 MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
367 MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
368 MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
369 MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
370 MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
371 MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
372 MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
373 MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
374 MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
375 MPP_REG_CTRL(16, 23),
376 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl), 360 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
377 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl), 361 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
378 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl), 362 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
@@ -772,8 +756,17 @@ static struct of_device_id dove_pinctrl_of_match[] = {
772 { } 756 { }
773}; 757};
774 758
759static struct regmap_config gc_regmap_config = {
760 .reg_bits = 32,
761 .val_bits = 32,
762 .reg_stride = 4,
763 .max_register = 5,
764};
765
775static int dove_pinctrl_probe(struct platform_device *pdev) 766static int dove_pinctrl_probe(struct platform_device *pdev)
776{ 767{
768 struct resource *res, *mpp_res;
769 struct resource fb_res;
777 const struct of_device_id *match = 770 const struct of_device_id *match =
778 of_match_device(dove_pinctrl_of_match, &pdev->dev); 771 of_match_device(dove_pinctrl_of_match, &pdev->dev);
779 pdev->dev.platform_data = (void *)match->data; 772 pdev->dev.platform_data = (void *)match->data;
@@ -789,6 +782,58 @@ static int dove_pinctrl_probe(struct platform_device *pdev)
789 } 782 }
790 clk_prepare_enable(clk); 783 clk_prepare_enable(clk);
791 784
785 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res);
787 if (IS_ERR(mpp_base))
788 return PTR_ERR(mpp_base);
789
790 /* prepare fallback resource */
791 memcpy(&fb_res, mpp_res, sizeof(struct resource));
792 fb_res.start = 0;
793
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
795 if (!res) {
796 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
797 adjust_resource(&fb_res,
798 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
799 res = &fb_res;
800 }
801
802 mpp4_base = devm_ioremap_resource(&pdev->dev, res);
803 if (IS_ERR(mpp4_base))
804 return PTR_ERR(mpp4_base);
805
806 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
807 if (!res) {
808 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
809 adjust_resource(&fb_res,
810 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
811 res = &fb_res;
812 }
813
814 pmu_base = devm_ioremap_resource(&pdev->dev, res);
815 if (IS_ERR(pmu_base))
816 return PTR_ERR(pmu_base);
817
818 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
819 if (IS_ERR(gconfmap)) {
820 void __iomem *gc_base;
821
822 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
823 adjust_resource(&fb_res,
824 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
825 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
826 if (IS_ERR(gc_base))
827 return PTR_ERR(gc_base);
828 gconfmap = devm_regmap_init_mmio(&pdev->dev,
829 gc_base, &gc_regmap_config);
830 if (IS_ERR(gconfmap))
831 return PTR_ERR(gconfmap);
832 }
833
834 /* Warn on any missing DT resource */
835 WARN(fb_res.start, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
836
792 return mvebu_pinctrl_probe(pdev); 837 return mvebu_pinctrl_probe(pdev);
793} 838}
794 839
diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
index 6b504b5935a5..0d0211a1a0b0 100644
--- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
@@ -21,6 +21,18 @@
21 21
22#include "pinctrl-mvebu.h" 22#include "pinctrl-mvebu.h"
23 23
24static void __iomem *mpp_base;
25
26static int kirkwood_mpp_ctrl_get(unsigned pid, unsigned long *config)
27{
28 return default_mpp_ctrl_get(mpp_base, pid, config);
29}
30
31static int kirkwood_mpp_ctrl_set(unsigned pid, unsigned long config)
32{
33 return default_mpp_ctrl_set(mpp_base, pid, config);
34}
35
24#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \ 36#define V(f6180, f6190, f6192, f6281, f6282, dx4122) \
25 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \ 37 ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) | \
26 (f6281 << 3) | (f6282 << 4) | (dx4122 << 5)) 38 (f6281 << 3) | (f6282 << 4) | (dx4122 << 5))
@@ -359,7 +371,7 @@ static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
359}; 371};
360 372
361static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = { 373static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
362 MPP_REG_CTRL(0, 29), 374 MPP_FUNC_CTRL(0, 29, NULL, kirkwood_mpp_ctrl),
363}; 375};
364 376
365static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = { 377static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
@@ -367,7 +379,7 @@ static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
367}; 379};
368 380
369static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = { 381static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
370 MPP_REG_CTRL(0, 35), 382 MPP_FUNC_CTRL(0, 35, NULL, kirkwood_mpp_ctrl),
371}; 383};
372 384
373static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = { 385static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
@@ -376,7 +388,7 @@ static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
376}; 388};
377 389
378static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = { 390static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
379 MPP_REG_CTRL(0, 49), 391 MPP_FUNC_CTRL(0, 49, NULL, kirkwood_mpp_ctrl),
380}; 392};
381 393
382static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = { 394static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
@@ -456,9 +468,16 @@ static struct of_device_id kirkwood_pinctrl_of_match[] = {
456 468
457static int kirkwood_pinctrl_probe(struct platform_device *pdev) 469static int kirkwood_pinctrl_probe(struct platform_device *pdev)
458{ 470{
471 struct resource *res;
459 const struct of_device_id *match = 472 const struct of_device_id *match =
460 of_match_device(kirkwood_pinctrl_of_match, &pdev->dev); 473 of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
461 pdev->dev.platform_data = (void *)match->data; 474 pdev->dev.platform_data = (void *)match->data;
475
476 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
477 mpp_base = devm_ioremap_resource(&pdev->dev, res);
478 if (IS_ERR(mpp_base))
479 return PTR_ERR(mpp_base);
480
462 return mvebu_pinctrl_probe(pdev); 481 return mvebu_pinctrl_probe(pdev);
463} 482}
464 483
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index 0fd1ad31fbf9..9908374f8f92 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -50,7 +50,6 @@ struct mvebu_pinctrl {
50 struct device *dev; 50 struct device *dev;
51 struct pinctrl_dev *pctldev; 51 struct pinctrl_dev *pctldev;
52 struct pinctrl_desc desc; 52 struct pinctrl_desc desc;
53 void __iomem *base;
54 struct mvebu_pinctrl_group *groups; 53 struct mvebu_pinctrl_group *groups;
55 unsigned num_groups; 54 unsigned num_groups;
56 struct mvebu_pinctrl_function *functions; 55 struct mvebu_pinctrl_function *functions;
@@ -138,43 +137,6 @@ static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
138 return NULL; 137 return NULL;
139} 138}
140 139
141/*
142 * Common mpp pin configuration registers on MVEBU are
143 * registers of eight 4-bit values for each mpp setting.
144 * Register offset and bit mask are calculated accordingly below.
145 */
146static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
147 struct mvebu_pinctrl_group *grp,
148 unsigned long *config)
149{
150 unsigned pin = grp->gid;
151 unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
152 unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
153
154 *config = readl(pctl->base + off);
155 *config >>= shift;
156 *config &= MPP_MASK;
157
158 return 0;
159}
160
161static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
162 struct mvebu_pinctrl_group *grp,
163 unsigned long config)
164{
165 unsigned pin = grp->gid;
166 unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
167 unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
168 unsigned long reg;
169
170 reg = readl(pctl->base + off);
171 reg &= ~(MPP_MASK << shift);
172 reg |= (config << shift);
173 writel(reg, pctl->base + off);
174
175 return 0;
176}
177
178static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev, 140static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
179 unsigned gid, unsigned long *config) 141 unsigned gid, unsigned long *config)
180{ 142{
@@ -184,10 +146,7 @@ static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
184 if (!grp->ctrl) 146 if (!grp->ctrl)
185 return -EINVAL; 147 return -EINVAL;
186 148
187 if (grp->ctrl->mpp_get) 149 return grp->ctrl->mpp_get(grp->pins[0], config);
188 return grp->ctrl->mpp_get(grp->ctrl, config);
189
190 return mvebu_common_mpp_get(pctl, grp, config);
191} 150}
192 151
193static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev, 152static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
@@ -202,11 +161,7 @@ static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
202 return -EINVAL; 161 return -EINVAL;
203 162
204 for (i = 0; i < num_configs; i++) { 163 for (i = 0; i < num_configs; i++) {
205 if (grp->ctrl->mpp_set) 164 ret = grp->ctrl->mpp_set(grp->pins[0], configs[i]);
206 ret = grp->ctrl->mpp_set(grp->ctrl, configs[i]);
207 else
208 ret = mvebu_common_mpp_set(pctl, grp, configs[i]);
209
210 if (ret) 165 if (ret)
211 return ret; 166 return ret;
212 } /* for each config */ 167 } /* for each config */
@@ -347,7 +302,7 @@ static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
347 return -EINVAL; 302 return -EINVAL;
348 303
349 if (grp->ctrl->mpp_gpio_req) 304 if (grp->ctrl->mpp_gpio_req)
350 return grp->ctrl->mpp_gpio_req(grp->ctrl, offset); 305 return grp->ctrl->mpp_gpio_req(offset);
351 306
352 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); 307 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
353 if (!setting) 308 if (!setting)
@@ -370,7 +325,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
370 return -EINVAL; 325 return -EINVAL;
371 326
372 if (grp->ctrl->mpp_gpio_dir) 327 if (grp->ctrl->mpp_gpio_dir)
373 return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input); 328 return grp->ctrl->mpp_gpio_dir(offset, input);
374 329
375 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp); 330 setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
376 if (!setting) 331 if (!setting)
@@ -593,11 +548,12 @@ static int mvebu_pinctrl_build_functions(struct platform_device *pdev,
593int mvebu_pinctrl_probe(struct platform_device *pdev) 548int mvebu_pinctrl_probe(struct platform_device *pdev)
594{ 549{
595 struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev); 550 struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
596 struct resource *res;
597 struct mvebu_pinctrl *pctl; 551 struct mvebu_pinctrl *pctl;
598 void __iomem *base;
599 struct pinctrl_pin_desc *pdesc; 552 struct pinctrl_pin_desc *pdesc;
600 unsigned gid, n, k; 553 unsigned gid, n, k;
554 unsigned size, noname = 0;
555 char *noname_buf;
556 void *p;
601 int ret; 557 int ret;
602 558
603 if (!soc || !soc->controls || !soc->modes) { 559 if (!soc || !soc->controls || !soc->modes) {
@@ -605,11 +561,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
605 return -EINVAL; 561 return -EINVAL;
606 } 562 }
607 563
608 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
609 base = devm_ioremap_resource(&pdev->dev, res);
610 if (IS_ERR(base))
611 return PTR_ERR(base);
612
613 pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl), 564 pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
614 GFP_KERNEL); 565 GFP_KERNEL);
615 if (!pctl) { 566 if (!pctl) {
@@ -623,7 +574,6 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
623 pctl->desc.pmxops = &mvebu_pinmux_ops; 574 pctl->desc.pmxops = &mvebu_pinmux_ops;
624 pctl->desc.confops = &mvebu_pinconf_ops; 575 pctl->desc.confops = &mvebu_pinconf_ops;
625 pctl->variant = soc->variant; 576 pctl->variant = soc->variant;
626 pctl->base = base;
627 pctl->dev = &pdev->dev; 577 pctl->dev = &pdev->dev;
628 platform_set_drvdata(pdev, pctl); 578 platform_set_drvdata(pdev, pctl);
629 579
@@ -633,33 +583,23 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
633 pctl->desc.npins = 0; 583 pctl->desc.npins = 0;
634 for (n = 0; n < soc->ncontrols; n++) { 584 for (n = 0; n < soc->ncontrols; n++) {
635 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; 585 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
636 char *names;
637 586
638 pctl->desc.npins += ctrl->npins; 587 pctl->desc.npins += ctrl->npins;
639 /* initial control pins */ 588 /* initialize control's pins[] array */
640 for (k = 0; k < ctrl->npins; k++) 589 for (k = 0; k < ctrl->npins; k++)
641 ctrl->pins[k] = ctrl->pid + k; 590 ctrl->pins[k] = ctrl->pid + k;
642 591
643 /* special soc specific control */ 592 /*
644 if (ctrl->mpp_get || ctrl->mpp_set) { 593 * We allow to pass controls with NULL name that we treat
645 if (!ctrl->name || !ctrl->mpp_get || !ctrl->mpp_set) { 594 * as a range of one-pin groups with generic mvebu register
646 dev_err(&pdev->dev, "wrong soc control info\n"); 595 * controls.
647 return -EINVAL; 596 */
648 } 597 if (!ctrl->name) {
598 pctl->num_groups += ctrl->npins;
599 noname += ctrl->npins;
600 } else {
649 pctl->num_groups += 1; 601 pctl->num_groups += 1;
650 continue;
651 } 602 }
652
653 /* generic mvebu register control */
654 names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
655 if (!names) {
656 dev_err(&pdev->dev, "failed to alloc mpp names\n");
657 return -ENOMEM;
658 }
659 for (k = 0; k < ctrl->npins; k++)
660 sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
661 ctrl->name = names;
662 pctl->num_groups += ctrl->npins;
663 } 603 }
664 604
665 pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins * 605 pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
@@ -673,12 +613,17 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
673 pdesc[n].number = n; 613 pdesc[n].number = n;
674 pctl->desc.pins = pdesc; 614 pctl->desc.pins = pdesc;
675 615
676 pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups * 616 /*
677 sizeof(struct mvebu_pinctrl_group), GFP_KERNEL); 617 * allocate groups and name buffers for unnamed groups.
678 if (!pctl->groups) { 618 */
679 dev_err(&pdev->dev, "failed to alloc pinctrl groups\n"); 619 size = pctl->num_groups * sizeof(*pctl->groups) + noname * 8;
620 p = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
621 if (!p) {
622 dev_err(&pdev->dev, "failed to alloc group data\n");
680 return -ENOMEM; 623 return -ENOMEM;
681 } 624 }
625 pctl->groups = p;
626 noname_buf = p + pctl->num_groups * sizeof(*pctl->groups);
682 627
683 /* assign mpp controls to groups */ 628 /* assign mpp controls to groups */
684 gid = 0; 629 gid = 0;
@@ -690,17 +635,26 @@ int mvebu_pinctrl_probe(struct platform_device *pdev)
690 pctl->groups[gid].pins = ctrl->pins; 635 pctl->groups[gid].pins = ctrl->pins;
691 pctl->groups[gid].npins = ctrl->npins; 636 pctl->groups[gid].npins = ctrl->npins;
692 637
693 /* generic mvebu register control maps to a number of groups */ 638 /*
694 if (!ctrl->mpp_get && !ctrl->mpp_set) { 639 * We treat unnamed controls as a range of one-pin groups
640 * with generic mvebu register controls. Use one group for
641 * each in this range and assign a default group name.
642 */
643 if (!ctrl->name) {
644 pctl->groups[gid].name = noname_buf;
695 pctl->groups[gid].npins = 1; 645 pctl->groups[gid].npins = 1;
646 sprintf(noname_buf, "mpp%d", ctrl->pid+0);
647 noname_buf += 8;
696 648
697 for (k = 1; k < ctrl->npins; k++) { 649 for (k = 1; k < ctrl->npins; k++) {
698 gid++; 650 gid++;
699 pctl->groups[gid].gid = gid; 651 pctl->groups[gid].gid = gid;
700 pctl->groups[gid].ctrl = ctrl; 652 pctl->groups[gid].ctrl = ctrl;
701 pctl->groups[gid].name = &ctrl->name[8*k]; 653 pctl->groups[gid].name = noname_buf;
702 pctl->groups[gid].pins = &ctrl->pins[k]; 654 pctl->groups[gid].pins = &ctrl->pins[k];
703 pctl->groups[gid].npins = 1; 655 pctl->groups[gid].npins = 1;
656 sprintf(noname_buf, "mpp%d", ctrl->pid+k);
657 noname_buf += 8;
704 } 658 }
705 } 659 }
706 gid++; 660 gid++;
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
index 90bd3beee860..65a98e6f7265 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h
@@ -28,20 +28,19 @@
28 * between two or more different settings, e.g. assign mpp pin 13 to 28 * between two or more different settings, e.g. assign mpp pin 13 to
29 * uart1 or sata. 29 * uart1 or sata.
30 * 30 *
31 * If optional mpp_get/_set functions are set these are used to get/set 31 * The mpp_get/_set functions are mandatory and are used to get/set a
32 * a specific mode. Otherwise it is assumed that the mpp control is based 32 * specific mode. The optional mpp_gpio_req/_dir functions can be used
33 * on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir 33 * to allow pin settings with varying gpio pins.
34 * functions can be used to allow pin settings with varying gpio pins.
35 */ 34 */
36struct mvebu_mpp_ctrl { 35struct mvebu_mpp_ctrl {
37 const char *name; 36 const char *name;
38 u8 pid; 37 u8 pid;
39 u8 npins; 38 u8 npins;
40 unsigned *pins; 39 unsigned *pins;
41 int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config); 40 int (*mpp_get)(unsigned pid, unsigned long *config);
42 int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config); 41 int (*mpp_set)(unsigned pid, unsigned long config);
43 int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid); 42 int (*mpp_gpio_req)(unsigned pid);
44 int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input); 43 int (*mpp_gpio_dir)(unsigned pid, bool input);
45}; 44};
46 45
47/** 46/**
@@ -114,18 +113,6 @@ struct mvebu_pinctrl_soc_info {
114 int ngpioranges; 113 int ngpioranges;
115}; 114};
116 115
117#define MPP_REG_CTRL(_idl, _idh) \
118 { \
119 .name = NULL, \
120 .pid = _idl, \
121 .npins = _idh - _idl + 1, \
122 .pins = (unsigned[_idh - _idl + 1]) { }, \
123 .mpp_get = NULL, \
124 .mpp_set = NULL, \
125 .mpp_gpio_req = NULL, \
126 .mpp_gpio_dir = NULL, \
127 }
128
129#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \ 116#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
130 { \ 117 { \
131 .name = _name, \ 118 .name = _name, \
@@ -186,6 +173,34 @@ struct mvebu_pinctrl_soc_info {
186 .npins = _npins, \ 173 .npins = _npins, \
187 } 174 }
188 175
176#define MVEBU_MPPS_PER_REG 8
177#define MVEBU_MPP_BITS 4
178#define MVEBU_MPP_MASK 0xf
179
180static inline int default_mpp_ctrl_get(void __iomem *base, unsigned int pid,
181 unsigned long *config)
182{
183 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
184 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
185
186 *config = (readl(base + off) >> shift) & MVEBU_MPP_MASK;
187
188 return 0;
189}
190
191static inline int default_mpp_ctrl_set(void __iomem *base, unsigned int pid,
192 unsigned long config)
193{
194 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
195 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
196 unsigned long reg;
197
198 reg = readl(base + off) & ~(MVEBU_MPP_MASK << shift);
199 writel(reg | (config << shift), base + off);
200
201 return 0;
202}
203
189int mvebu_pinctrl_probe(struct platform_device *pdev); 204int mvebu_pinctrl_probe(struct platform_device *pdev);
190int mvebu_pinctrl_remove(struct platform_device *pdev); 205int mvebu_pinctrl_remove(struct platform_device *pdev);
191 206
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 22:19:19 -0400