drm/tilcdc fixup mode to workaround sync for tda998x

Add a fixup function that will flip the hsync priority and
add a hskew value that is used to shift the tda998x to the
right by a variable number of pixels depending on the mode.
This works around an issue with the sync timings that tilcdc
is outputing.

Signed-off-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Russell King <rmk_kernel@arm.linux.org.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>

2 files changed, 32 insertions, 2 deletions

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 7418dcd986d3..6d0524095fe3 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -379,7 +379,12 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
         else
                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 
-        if (mode->flags & DRM_MODE_FLAG_NHSYNC)
+        /*
+         * use value from adjusted_mode here as this might have been
+         * changed as part of the fixup for slave encoders to solve the
+         * issue where tilcdc timings are not VESA compliant
+         */
+        if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
         else
                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_slave.c b/drivers/gpu/drm/tilcdc/tilcdc_slave.c
index dfffaf014022..23b3203d8241 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_slave.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_slave.c
@@ -73,13 +73,38 @@ static void slave_encoder_prepare(struct drm_encoder *encoder)
         tilcdc_crtc_set_panel_info(encoder->crtc, &slave_info);
 }
 
+static bool slave_encoder_fixup(struct drm_encoder *encoder,
+                const struct drm_display_mode *mode,
+                struct drm_display_mode *adjusted_mode)
+{
+        /*
+         * tilcdc does not generate VESA-complient sync but aligns
+         * VS on the second edge of HS instead of first edge.
+         * We use adjusted_mode, to fixup sync by aligning both rising
+         * edges and add HSKEW offset to let the slave encoder fix it up.
+         */
+        adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
+        adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
+
+        if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
+                adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
+                adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
+        } else {
+                adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
+                adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
+        }
+
+        return drm_i2c_encoder_mode_fixup(encoder, mode, adjusted_mode);
+}
+
+
 static const struct drm_encoder_funcs slave_encoder_funcs = {
                 .destroy        = slave_encoder_destroy,
 };
 
 static const struct drm_encoder_helper_funcs slave_encoder_helper_funcs = {
                 .dpms           = drm_i2c_encoder_dpms,
-                .mode_fixup     = drm_i2c_encoder_mode_fixup,
+                .mode_fixup     = slave_encoder_fixup,
                 .prepare        = slave_encoder_prepare,
                 .commit         = drm_i2c_encoder_commit,
                 .mode_set       = drm_i2c_encoder_mode_set,