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authorAnatolij Gustschin <agust@denx.de>2013-02-01 11:48:00 -0500
committerAnatolij Gustschin <agust@denx.de>2013-02-05 02:40:27 -0500
commita9571a3837dc4b0b478297e4eaf84332d0f129d1 (patch)
tree6823def3a0830662d3802c4c4f280135b8953d77
parentedfcf33cabf29710f12a3bba4a7b3761a918e268 (diff)
powerpc/mpc512x: fix noderef sparse warnings
Fix: warning: dereference of noderef expression Signed-off-by: Anatolij Gustschin <agust@denx.de>
-rw-r--r--arch/powerpc/platforms/512x/clock.c18
1 files changed, 9 insertions, 9 deletions
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 7937361c5804..8a784d46f40c 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -184,7 +184,7 @@ static unsigned long spmf_mult(void)
184 36, 40, 44, 48, 184 36, 40, 44, 48,
185 52, 56, 60, 64 185 52, 56, 60, 64
186 }; 186 };
187 int spmf = (clockctl->spmr >> 24) & 0xf; 187 int spmf = (in_be32(&clockctl->spmr) >> 24) & 0xf;
188 return spmf_to_mult[spmf]; 188 return spmf_to_mult[spmf];
189} 189}
190 190
@@ -206,7 +206,7 @@ static unsigned long sysdiv_div_x_2(void)
206 52, 56, 58, 62, 206 52, 56, 58, 62,
207 60, 64, 66, 207 60, 64, 66,
208 }; 208 };
209 int sysdiv = (clockctl->scfr2 >> 26) & 0x3f; 209 int sysdiv = (in_be32(&clockctl->scfr2) >> 26) & 0x3f;
210 return sysdiv_to_div_x_2[sysdiv]; 210 return sysdiv_to_div_x_2[sysdiv];
211} 211}
212 212
@@ -230,7 +230,7 @@ static unsigned long sys_to_ref(unsigned long rate)
230 230
231static long ips_to_ref(unsigned long rate) 231static long ips_to_ref(unsigned long rate)
232{ 232{
233 int ips_div = (clockctl->scfr1 >> 23) & 0x7; 233 int ips_div = (in_be32(&clockctl->scfr1) >> 23) & 0x7;
234 234
235 rate *= ips_div; /* csb_clk = ips_clk * ips_div */ 235 rate *= ips_div; /* csb_clk = ips_clk * ips_div */
236 rate *= 2; /* sys_clk = csb_clk * 2 */ 236 rate *= 2; /* sys_clk = csb_clk * 2 */
@@ -284,7 +284,7 @@ static struct clk sys_clk = {
284 284
285static void diu_clk_calc(struct clk *clk) 285static void diu_clk_calc(struct clk *clk)
286{ 286{
287 int diudiv_x_2 = clockctl->scfr1 & 0xff; 287 int diudiv_x_2 = in_be32(&clockctl->scfr1) & 0xff;
288 unsigned long rate; 288 unsigned long rate;
289 289
290 rate = sys_clk.rate; 290 rate = sys_clk.rate;
@@ -311,7 +311,7 @@ static void half_clk_calc(struct clk *clk)
311 311
312static void generic_div_clk_calc(struct clk *clk) 312static void generic_div_clk_calc(struct clk *clk)
313{ 313{
314 int div = (clockctl->scfr1 >> clk->div_shift) & 0x7; 314 int div = (in_be32(&clockctl->scfr1) >> clk->div_shift) & 0x7;
315 315
316 clk->rate = clk->parent->rate / div; 316 clk->rate = clk->parent->rate / div;
317} 317}
@@ -329,7 +329,7 @@ static struct clk csb_clk = {
329 329
330static void e300_clk_calc(struct clk *clk) 330static void e300_clk_calc(struct clk *clk)
331{ 331{
332 int spmf = (clockctl->spmr >> 16) & 0xf; 332 int spmf = (in_be32(&clockctl->spmr) >> 16) & 0xf;
333 int ratex2 = clk->parent->rate * spmf; 333 int ratex2 = clk->parent->rate * spmf;
334 334
335 clk->rate = ratex2 / 2; 335 clk->rate = ratex2 / 2;
@@ -648,12 +648,12 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
648 out_be32(&clockctl->pccr[pscnum], 0x00020000); 648 out_be32(&clockctl->pccr[pscnum], 0x00020000);
649 out_be32(&clockctl->pccr[pscnum], 0x00030000); 649 out_be32(&clockctl->pccr[pscnum], 0x00030000);
650 650
651 if (clockctl->pccr[pscnum] & 0x80) { 651 if (in_be32(&clockctl->pccr[pscnum]) & 0x80) {
652 clk->rate = spdif_rxclk.rate; 652 clk->rate = spdif_rxclk.rate;
653 return; 653 return;
654 } 654 }
655 655
656 switch ((clockctl->pccr[pscnum] >> 14) & 0x3) { 656 switch ((in_be32(&clockctl->pccr[pscnum]) >> 14) & 0x3) {
657 case 0: 657 case 0:
658 mclk_src = sys_clk.rate; 658 mclk_src = sys_clk.rate;
659 break; 659 break;
@@ -668,7 +668,7 @@ static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
668 break; 668 break;
669 } 669 }
670 670
671 mclk_div = ((clockctl->pccr[pscnum] >> 17) & 0x7fff) + 1; 671 mclk_div = ((in_be32(&clockctl->pccr[pscnum]) >> 17) & 0x7fff) + 1;
672 clk->rate = mclk_src / mclk_div; 672 clk->rate = mclk_src / mclk_div;
673} 673}
674 674