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authorMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-11 06:06:36 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-11 06:06:36 -0500
commita948cae6ab124d7ff4365c9e72b33079b7769ae2 (patch)
tree61c6eb07053fa7038e27d4be278ab41dd92e399d
parentd0c65252c4fdd306f2dbcf5c14181001bfdbe70e (diff)
parent685e42154dcf3f6c0a52c115bd15e3d28ad8621b (diff)
Merge remote-tracking branch 'asoc/topic/max98090' into asoc-next
Diffstat
-rwxr-xr-xinclude/sound/max98090.h29
-rwxr-xr-x[-rw-r--r--]sound/soc/codecs/max98090.c2685
-rwxr-xr-xsound/soc/codecs/max98090.h1549
3 files changed, 3831 insertions, 432 deletions
diff --git a/include/sound/max98090.h b/include/sound/max98090.h
new file mode 100755
index 000000000000..95efb13f8478
--- /dev/null
+++ b/include/sound/max98090.h
@@ -0,0 +1,29 @@
1/*
2 * Platform data for MAX98090
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12
13#ifndef __SOUND_MAX98090_PDATA_H__
14#define __SOUND_MAX98090_PDATA_H__
15
16/* codec platform data */
17struct max98090_pdata {
18
19 /* Analog/digital microphone configuration:
20 * 0 = analog microphone input (normal setting)
21 * 1 = digital microphone input
22 */
23 unsigned int digmic_left_mode:1;
24 unsigned int digmic_right_mode:1;
25 unsigned int digmic_3_mode:1;
26 unsigned int digmic_4_mode:1;
27};
28
29#endif
diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c
index c9772ca3da4f..fc176044994d 100644..100755
--- a/sound/soc/codecs/max98090.c
+++ b/sound/soc/codecs/max98090.c
@@ -1,562 +1,2381 @@
1/* 1/*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver 2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 * based on Rev0p8 datasheet
4 * 3 *
5 * Copyright (C) 2012 Renesas Solutions Corp. 4 * Copyright 2011-2012 Maxim Integrated Products
6 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 *
8 * Based on
9 *
10 * max98095.c
11 * Copyright 2011 Maxim Integrated Products
12 *
13 * https://github.com/hardkernel/linux/commit/\
14 * 3417d7166b17113b3b33b0a337c74d1c7cc313df#sound/soc/codecs/max98090.c
15 * Copyright 2011 Maxim Integrated Products
16 * 5 *
17 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
20 */ 9 */
21 10
11#include <linux/delay.h>
22#include <linux/i2c.h> 12#include <linux/i2c.h>
23#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/pm.h>
15#include <linux/pm_runtime.h>
24#include <linux/regmap.h> 16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <sound/jack.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
25#include <sound/soc.h> 21#include <sound/soc.h>
26#include <sound/tlv.h> 22#include <sound/tlv.h>
23#include <sound/max98090.h>
24#include "max98090.h"
25
26#include <linux/version.h>
27
28#define DEBUG
29#define EXTMIC_METHOD
30#define EXTMIC_METHOD_TEST
31
32/* Allows for sparsely populated register maps */
33static struct reg_default max98090_reg[] = {
34 { 0x00, 0x00 }, /* 00 Software Reset */
35 { 0x03, 0x04 }, /* 03 Interrupt Masks */
36 { 0x04, 0x00 }, /* 04 System Clock Quick */
37 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
38 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
39 { 0x07, 0x00 }, /* 07 DAC Path Quick */
40 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
41 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
42 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
43 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
44 { 0x0C, 0x00 }, /* 0C Reserved */
45 { 0x0D, 0x00 }, /* 0D Input Config */
46 { 0x0E, 0x1B }, /* 0E Line Input Level */
47 { 0x0F, 0x00 }, /* 0F Line Config */
48
49 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
50 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
51 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
52 { 0x13, 0x00 }, /* 13 Digital Mic Config */
53 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
54 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
55 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
56 { 0x17, 0x03 }, /* 17 Left ADC Level */
57 { 0x18, 0x03 }, /* 18 Right ADC Level */
58 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
59 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
60 { 0x1B, 0x00 }, /* 1B System Clock */
61 { 0x1C, 0x00 }, /* 1C Clock Mode */
62 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
63 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
64 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
65
66 { 0x20, 0x00 }, /* 20 Any Clock 4 */
67 { 0x21, 0x00 }, /* 21 Master Mode */
68 { 0x22, 0x00 }, /* 22 Interface Format */
69 { 0x23, 0x00 }, /* 23 TDM Format 1*/
70 { 0x24, 0x00 }, /* 24 TDM Format 2*/
71 { 0x25, 0x00 }, /* 25 I/O Configuration */
72 { 0x26, 0x80 }, /* 26 Filter Config */
73 { 0x27, 0x00 }, /* 27 DAI Playback Level */
74 { 0x28, 0x00 }, /* 28 EQ Playback Level */
75 { 0x29, 0x00 }, /* 29 Left HP Mixer */
76 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
77 { 0x2B, 0x00 }, /* 2B HP Control */
78 { 0x2C, 0x1A }, /* 2C Left HP Volume */
79 { 0x2D, 0x1A }, /* 2D Right HP Volume */
80 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
81 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
82
83 { 0x30, 0x00 }, /* 30 Spk Control */
84 { 0x31, 0x2C }, /* 31 Left Spk Volume */
85 { 0x32, 0x2C }, /* 32 Right Spk Volume */
86 { 0x33, 0x00 }, /* 33 ALC Timing */
87 { 0x34, 0x00 }, /* 34 ALC Compressor */
88 { 0x35, 0x00 }, /* 35 ALC Expander */
89 { 0x36, 0x00 }, /* 36 ALC Gain */
90 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
91 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
92 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
93 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
94 { 0x3B, 0x00 }, /* 3B Line OutR Control */
95 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
96 { 0x3D, 0x00 }, /* 3D Jack Detect */
97 { 0x3E, 0x00 }, /* 3E Input Enable */
98 { 0x3F, 0x00 }, /* 3F Output Enable */
99
100 { 0x40, 0x00 }, /* 40 Level Control */
101 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
102 { 0x42, 0x00 }, /* 42 Bias Control */
103 { 0x43, 0x00 }, /* 43 DAC Control */
104 { 0x44, 0x06 }, /* 44 ADC Control */
105 { 0x45, 0x00 }, /* 45 Device Shutdown */
106 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
107 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
108 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
109 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
110 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
111 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
112 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
113 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
114 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
115 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
116
117 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
118 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
119 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
120 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
121 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
122 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
123 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
124 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
125 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
126 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
127 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
128 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
129 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
130 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
131 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
132 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
133
134 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
135 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
136 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
137 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
138 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
139 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
140 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
141 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
142 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
143 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
144 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
145 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
146 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
147 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
148 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
149 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
150
151 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
152 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
153 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
154 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
155 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
156 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
157 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
158 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
159 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
160 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
161 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
162 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
163 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
164 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
165 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
166 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
167
168 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
169 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
170 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
171 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
172 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
173 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
174 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
175 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
176 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
177 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
178 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
179 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
180 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
181 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
182 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
183 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
184
185 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
186 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
187 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
188 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
189 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
190 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
191 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
192 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
193 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
194 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
195 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
196 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
197 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
198 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
199 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
200 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
201
202 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
203 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
204 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
205 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
206 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
207 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
208 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
209 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
210 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
211 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
212 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
213 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
214 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
215 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
216 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
217 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
218
219 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
220 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
221 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
222 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
223 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
224 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
225 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
226 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
227 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
228 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
229 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
230 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
231 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
232 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
233 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
234 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
235
236 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
237 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
238 { 0xC2, 0x00 }, /* C2 Sample Rate */
239 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
240 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
241 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
242 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
243 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
244 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
245 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
246 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
247 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
248 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
249 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
250 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
251 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
252
253 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
254 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
255};
27 256
28/* 257static bool max98090_volatile_register(struct device *dev, unsigned int reg)
29 * 258{
30 * MAX98090 Registers Definition 259 switch (reg) {
31 * 260 case M98090_REG_DEVICE_STATUS:
32 */ 261 case M98090_REG_JACK_STATUS:
262 case M98090_REG_REVISION_ID:
263 return true;
264 default:
265 return false;
266 }
267}
33 268
34/* RESET / STATUS / INTERRUPT REGISTERS */ 269static bool max98090_readable_register(struct device *dev, unsigned int reg)
35#define MAX98090_0x00_SW_RESET 0x00 270{
36#define MAX98090_0x01_INT_STS 0x01 271 switch (reg) {
37#define MAX98090_0x02_JACK_STS 0x02 272 case M98090_REG_DEVICE_STATUS:
38#define MAX98090_0x03_INT_MASK 0x03 273 case M98090_REG_JACK_STATUS:
39 274 case M98090_REG_INTERRUPT_S:
40/* QUICK SETUP REGISTERS */ 275 case M98090_REG_RESERVED:
41#define MAX98090_0x04_SYS_CLK 0x04 276 case M98090_REG_LINE_INPUT_CONFIG:
42#define MAX98090_0x05_SAMPLE_RATE 0x05 277 case M98090_REG_LINE_INPUT_LEVEL:
43#define MAX98090_0x06_DAI_IF 0x06 278 case M98090_REG_INPUT_MODE:
44#define MAX98090_0x07_DAC_PATH 0x07 279 case M98090_REG_MIC1_INPUT_LEVEL:
45#define MAX98090_0x08_MIC_TO_ADC 0x08 280 case M98090_REG_MIC2_INPUT_LEVEL:
46#define MAX98090_0x09_LINE_TO_ADC 0x09 281 case M98090_REG_MIC_BIAS_VOLTAGE:
47#define MAX98090_0x0A_ANALOG_MIC_LOOP 0x0A 282 case M98090_REG_DIGITAL_MIC_ENABLE:
48#define MAX98090_0x0B_ANALOG_LINE_LOOP 0x0B 283 case M98090_REG_DIGITAL_MIC_CONFIG:
49 284 case M98090_REG_LEFT_ADC_MIXER:
50/* ANALOG INPUT CONFIGURATION REGISTERS */ 285 case M98090_REG_RIGHT_ADC_MIXER:
51#define MAX98090_0x0D_INPUT_CONFIG 0x0D 286 case M98090_REG_LEFT_ADC_LEVEL:
52#define MAX98090_0x0E_LINE_IN_LVL 0x0E 287 case M98090_REG_RIGHT_ADC_LEVEL:
53#define MAX98090_0x0F_LINI_IN_CFG 0x0F 288 case M98090_REG_ADC_BIQUAD_LEVEL:
54#define MAX98090_0x10_MIC1_IN_LVL 0x10 289 case M98090_REG_ADC_SIDETONE:
55#define MAX98090_0x11_MIC2_IN_LVL 0x11 290 case M98090_REG_SYSTEM_CLOCK:
56 291 case M98090_REG_CLOCK_MODE:
57/* MICROPHONE CONFIGURATION REGISTERS */ 292 case M98090_REG_CLOCK_RATIO_NI_MSB:
58#define MAX98090_0x12_MIC_BIAS_VOL 0x12 293 case M98090_REG_CLOCK_RATIO_NI_LSB:
59#define MAX98090_0x13_DIGITAL_MIC_CFG 0x13 294 case M98090_REG_CLOCK_RATIO_MI_MSB:
60#define MAX98090_0x14_DIGITAL_MIC_MODE 0x14 295 case M98090_REG_CLOCK_RATIO_MI_LSB:
61 296 case M98090_REG_MASTER_MODE:
62/* ADC PATH AND CONFIGURATION REGISTERS */ 297 case M98090_REG_INTERFACE_FORMAT:
63#define MAX98090_0x15_L_ADC_MIX 0x15 298 case M98090_REG_TDM_CONTROL:
64#define MAX98090_0x16_R_ADC_MIX 0x16 299 case M98090_REG_TDM_FORMAT:
65#define MAX98090_0x17_L_ADC_LVL 0x17 300 case M98090_REG_IO_CONFIGURATION:
66#define MAX98090_0x18_R_ADC_LVL 0x18 301 case M98090_REG_FILTER_CONFIG:
67#define MAX98090_0x19_ADC_BIQUAD_LVL 0x19 302 case M98090_REG_DAI_PLAYBACK_LEVEL:
68#define MAX98090_0x1A_ADC_SIDETONE 0x1A 303 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
69 304 case M98090_REG_LEFT_HP_MIXER:
70/* CLOCK CONFIGURATION REGISTERS */ 305 case M98090_REG_RIGHT_HP_MIXER:
71#define MAX98090_0x1B_SYS_CLK 0x1B 306 case M98090_REG_HP_CONTROL:
72#define MAX98090_0x1C_CLK_MODE 0x1C 307 case M98090_REG_LEFT_HP_VOLUME:
73#define MAX98090_0x1D_ANY_CLK1 0x1D 308 case M98090_REG_RIGHT_HP_VOLUME:
74#define MAX98090_0x1E_ANY_CLK2 0x1E 309 case M98090_REG_LEFT_SPK_MIXER:
75#define MAX98090_0x1F_ANY_CLK3 0x1F 310 case M98090_REG_RIGHT_SPK_MIXER:
76#define MAX98090_0x20_ANY_CLK4 0x20 311 case M98090_REG_SPK_CONTROL:
77#define MAX98090_0x21_MASTER_MODE 0x21 312 case M98090_REG_LEFT_SPK_VOLUME:
78 313 case M98090_REG_RIGHT_SPK_VOLUME:
79/* INTERFACE CONTROL REGISTERS */ 314 case M98090_REG_DRC_TIMING:
80#define MAX98090_0x22_DAI_IF_FMT 0x22 315 case M98090_REG_DRC_COMPRESSOR:
81#define MAX98090_0x23_DAI_TDM_FMT1 0x23 316 case M98090_REG_DRC_EXPANDER:
82#define MAX98090_0x24_DAI_TDM_FMT2 0x24 317 case M98090_REG_DRC_GAIN:
83#define MAX98090_0x25_DAI_IO_CFG 0x25 318 case M98090_REG_RCV_LOUTL_MIXER:
84#define MAX98090_0x26_FILTER_CFG 0x26 319 case M98090_REG_RCV_LOUTL_CONTROL:
85#define MAX98090_0x27_DAI_PLAYBACK_LVL 0x27 320 case M98090_REG_RCV_LOUTL_VOLUME:
86#define MAX98090_0x28_EQ_PLAYBACK_LVL 0x28 321 case M98090_REG_LOUTR_MIXER:
87 322 case M98090_REG_LOUTR_CONTROL:
88/* HEADPHONE CONTROL REGISTERS */ 323 case M98090_REG_LOUTR_VOLUME:
89#define MAX98090_0x29_L_HP_MIX 0x29 324 case M98090_REG_JACK_DETECT:
90#define MAX98090_0x2A_R_HP_MIX 0x2A 325 case M98090_REG_INPUT_ENABLE:
91#define MAX98090_0x2B_HP_CTR 0x2B 326 case M98090_REG_OUTPUT_ENABLE:
92#define MAX98090_0x2C_L_HP_VOL 0x2C 327 case M98090_REG_LEVEL_CONTROL:
93#define MAX98090_0x2D_R_HP_VOL 0x2D 328 case M98090_REG_DSP_FILTER_ENABLE:
94 329 case M98090_REG_BIAS_CONTROL:
95/* SPEAKER CONFIGURATION REGISTERS */ 330 case M98090_REG_DAC_CONTROL:
96#define MAX98090_0x2E_L_SPK_MIX 0x2E 331 case M98090_REG_ADC_CONTROL:
97#define MAX98090_0x2F_R_SPK_MIX 0x2F 332 case M98090_REG_DEVICE_SHUTDOWN:
98#define MAX98090_0x30_SPK_CTR 0x30 333 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
99#define MAX98090_0x31_L_SPK_VOL 0x31 334 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
100#define MAX98090_0x32_R_SPK_VOL 0x32 335 case M98090_REG_DMIC3_VOLUME:
101 336 case M98090_REG_DMIC4_VOLUME:
102/* ALC CONFIGURATION REGISTERS */ 337 case M98090_REG_DMIC34_BQ_PREATTEN:
103#define MAX98090_0x33_ALC_TIMING 0x33 338 case M98090_REG_RECORD_TDM_SLOT:
104#define MAX98090_0x34_ALC_COMPRESSOR 0x34 339 case M98090_REG_SAMPLE_RATE:
105#define MAX98090_0x35_ALC_EXPANDER 0x35 340 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
106#define MAX98090_0x36_ALC_GAIN 0x36 341 return true;
107 342 default:
108/* RECEIVER AND LINE_OUTPUT REGISTERS */ 343 return false;
109#define MAX98090_0x37_RCV_LOUT_L_MIX 0x37 344 }
110#define MAX98090_0x38_RCV_LOUT_L_CNTL 0x38 345}
111#define MAX98090_0x39_RCV_LOUT_L_VOL 0x39
112#define MAX98090_0x3A_LOUT_R_MIX 0x3A
113#define MAX98090_0x3B_LOUT_R_CNTL 0x3B
114#define MAX98090_0x3C_LOUT_R_VOL 0x3C
115
116/* JACK DETECT AND ENABLE REGISTERS */
117#define MAX98090_0x3D_JACK_DETECT 0x3D
118#define MAX98090_0x3E_IN_ENABLE 0x3E
119#define MAX98090_0x3F_OUT_ENABLE 0x3F
120#define MAX98090_0x40_LVL_CTR 0x40
121#define MAX98090_0x41_DSP_FILTER_ENABLE 0x41
122
123/* BIAS AND POWER MODE CONFIGURATION REGISTERS */
124#define MAX98090_0x42_BIAS_CTR 0x42
125#define MAX98090_0x43_DAC_CTR 0x43
126#define MAX98090_0x44_ADC_CTR 0x44
127#define MAX98090_0x45_DEV_SHUTDOWN 0x45
128
129/* REVISION ID REGISTER */
130#define MAX98090_0xFF_REV_ID 0xFF
131
132#define MAX98090_REG_MAX_CACHED 0x45
133#define MAX98090_REG_END 0xFF
134 346
135/* 347static int max98090_reset(struct max98090_priv *max98090)
136 * 348{
137 * MAX98090 Registers Bit Fields 349 int ret;
138 *
139 */
140 350
141/* MAX98090_0x06_DAI_IF */ 351 /* Reset the codec by writing to this write-only reset register */
142#define MAX98090_DAI_IF_MASK 0x3F 352 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
143#define MAX98090_RJ_M (1 << 5) 353 M98090_SWRESET_MASK);
144#define MAX98090_RJ_S (1 << 4) 354 if (ret < 0) {
145#define MAX98090_LJ_M (1 << 3) 355 dev_err(max98090->codec->dev,
146#define MAX98090_LJ_S (1 << 2) 356 "Failed to reset codec: %d\n", ret);
147#define MAX98090_I2S_M (1 << 1) 357 return ret;
148#define MAX98090_I2S_S (1 << 0) 358 }
149 359
150/* MAX98090_0x45_DEV_SHUTDOWN */ 360 msleep(20);
151#define MAX98090_SHDNRUN (1 << 7) 361 return ret;
152 362}
153/* codec private data */ 363
154struct max98090_priv { 364static const unsigned int max98090_micboost_tlv[] = {
155 struct regmap *regmap; 365 TLV_DB_RANGE_HEAD(2),
156}; 366 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
157 367 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
158static const struct reg_default max98090_reg_defaults[] = { 368};
159 /* RESET / STATUS / INTERRUPT REGISTERS */ 369
160 {MAX98090_0x00_SW_RESET, 0x00}, 370static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
161 {MAX98090_0x01_INT_STS, 0x00}, 371
162 {MAX98090_0x02_JACK_STS, 0x00}, 372static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
163 {MAX98090_0x03_INT_MASK, 0x04}, 373 -600, 600, 0);
164 374
165 /* QUICK SETUP REGISTERS */ 375static const unsigned int max98090_line_tlv[] = {
166 {MAX98090_0x04_SYS_CLK, 0x00}, 376 TLV_DB_RANGE_HEAD(2),
167 {MAX98090_0x05_SAMPLE_RATE, 0x00}, 377 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
168 {MAX98090_0x06_DAI_IF, 0x00}, 378 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
169 {MAX98090_0x07_DAC_PATH, 0x00}, 379};
170 {MAX98090_0x08_MIC_TO_ADC, 0x00}, 380
171 {MAX98090_0x09_LINE_TO_ADC, 0x00}, 381static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
172 {MAX98090_0x0A_ANALOG_MIC_LOOP, 0x00}, 382static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
173 {MAX98090_0x0B_ANALOG_LINE_LOOP, 0x00}, 383
174 384static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
175 /* ANALOG INPUT CONFIGURATION REGISTERS */ 385static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
176 {MAX98090_0x0D_INPUT_CONFIG, 0x00}, 386
177 {MAX98090_0x0E_LINE_IN_LVL, 0x1B}, 387static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
178 {MAX98090_0x0F_LINI_IN_CFG, 0x00}, 388
179 {MAX98090_0x10_MIC1_IN_LVL, 0x11}, 389static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
180 {MAX98090_0x11_MIC2_IN_LVL, 0x11}, 390static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
181 391static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
182 /* MICROPHONE CONFIGURATION REGISTERS */ 392static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
183 {MAX98090_0x12_MIC_BIAS_VOL, 0x00}, 393
184 {MAX98090_0x13_DIGITAL_MIC_CFG, 0x00}, 394static const unsigned int max98090_mixout_tlv[] = {
185 {MAX98090_0x14_DIGITAL_MIC_MODE, 0x00}, 395 TLV_DB_RANGE_HEAD(2),
186 396 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
187 /* ADC PATH AND CONFIGURATION REGISTERS */ 397 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
188 {MAX98090_0x15_L_ADC_MIX, 0x00},
189 {MAX98090_0x16_R_ADC_MIX, 0x00},
190 {MAX98090_0x17_L_ADC_LVL, 0x03},
191 {MAX98090_0x18_R_ADC_LVL, 0x03},
192 {MAX98090_0x19_ADC_BIQUAD_LVL, 0x00},
193 {MAX98090_0x1A_ADC_SIDETONE, 0x00},
194
195 /* CLOCK CONFIGURATION REGISTERS */
196 {MAX98090_0x1B_SYS_CLK, 0x00},
197 {MAX98090_0x1C_CLK_MODE, 0x00},
198 {MAX98090_0x1D_ANY_CLK1, 0x00},
199 {MAX98090_0x1E_ANY_CLK2, 0x00},
200 {MAX98090_0x1F_ANY_CLK3, 0x00},
201 {MAX98090_0x20_ANY_CLK4, 0x00},
202 {MAX98090_0x21_MASTER_MODE, 0x00},
203
204 /* INTERFACE CONTROL REGISTERS */
205 {MAX98090_0x22_DAI_IF_FMT, 0x00},
206 {MAX98090_0x23_DAI_TDM_FMT1, 0x00},
207 {MAX98090_0x24_DAI_TDM_FMT2, 0x00},
208 {MAX98090_0x25_DAI_IO_CFG, 0x00},
209 {MAX98090_0x26_FILTER_CFG, 0x80},
210 {MAX98090_0x27_DAI_PLAYBACK_LVL, 0x00},
211 {MAX98090_0x28_EQ_PLAYBACK_LVL, 0x00},
212
213 /* HEADPHONE CONTROL REGISTERS */
214 {MAX98090_0x29_L_HP_MIX, 0x00},
215 {MAX98090_0x2A_R_HP_MIX, 0x00},
216 {MAX98090_0x2B_HP_CTR, 0x00},
217 {MAX98090_0x2C_L_HP_VOL, 0x1A},
218 {MAX98090_0x2D_R_HP_VOL, 0x1A},
219
220 /* SPEAKER CONFIGURATION REGISTERS */
221 {MAX98090_0x2E_L_SPK_MIX, 0x00},
222 {MAX98090_0x2F_R_SPK_MIX, 0x00},
223 {MAX98090_0x30_SPK_CTR, 0x00},
224 {MAX98090_0x31_L_SPK_VOL, 0x2C},
225 {MAX98090_0x32_R_SPK_VOL, 0x2C},
226
227 /* ALC CONFIGURATION REGISTERS */
228 {MAX98090_0x33_ALC_TIMING, 0x00},
229 {MAX98090_0x34_ALC_COMPRESSOR, 0x00},
230 {MAX98090_0x35_ALC_EXPANDER, 0x00},
231 {MAX98090_0x36_ALC_GAIN, 0x00},
232
233 /* RECEIVER AND LINE_OUTPUT REGISTERS */
234 {MAX98090_0x37_RCV_LOUT_L_MIX, 0x00},
235 {MAX98090_0x38_RCV_LOUT_L_CNTL, 0x00},
236 {MAX98090_0x39_RCV_LOUT_L_VOL, 0x15},
237 {MAX98090_0x3A_LOUT_R_MIX, 0x00},
238 {MAX98090_0x3B_LOUT_R_CNTL, 0x00},
239 {MAX98090_0x3C_LOUT_R_VOL, 0x15},
240
241 /* JACK DETECT AND ENABLE REGISTERS */
242 {MAX98090_0x3D_JACK_DETECT, 0x00},
243 {MAX98090_0x3E_IN_ENABLE, 0x00},
244 {MAX98090_0x3F_OUT_ENABLE, 0x00},
245 {MAX98090_0x40_LVL_CTR, 0x00},
246 {MAX98090_0x41_DSP_FILTER_ENABLE, 0x00},
247
248 /* BIAS AND POWER MODE CONFIGURATION REGISTERS */
249 {MAX98090_0x42_BIAS_CTR, 0x00},
250 {MAX98090_0x43_DAC_CTR, 0x00},
251 {MAX98090_0x44_ADC_CTR, 0x06},
252 {MAX98090_0x45_DEV_SHUTDOWN, 0x00},
253}; 398};
254 399
255static const unsigned int max98090_hp_tlv[] = { 400static const unsigned int max98090_hp_tlv[] = {
256 TLV_DB_RANGE_HEAD(5), 401 TLV_DB_RANGE_HEAD(5),
257 0x0, 0x6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 402 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
258 0x7, 0xE, TLV_DB_SCALE_ITEM(-4000, 300, 0), 403 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
259 0xF, 0x15, TLV_DB_SCALE_ITEM(-1700, 200, 0), 404 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
260 0x16, 0x1B, TLV_DB_SCALE_ITEM(-400, 100, 0), 405 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
261 0x1C, 0x1F, TLV_DB_SCALE_ITEM(150, 50, 0), 406 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
262}; 407};
263 408
264static struct snd_kcontrol_new max98090_snd_controls[] = { 409static const unsigned int max98090_spk_tlv[] = {
265 SOC_DOUBLE_R_TLV("Headphone Volume", MAX98090_0x2C_L_HP_VOL, 410 TLV_DB_RANGE_HEAD(5),
266 MAX98090_0x2D_R_HP_VOL, 0, 31, 0, max98090_hp_tlv), 411 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
412 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
413 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
414 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
415 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
267}; 416};
268 417
269/* Left HeadPhone Mixer Switch */ 418static const unsigned int max98090_rcv_lout_tlv[] = {
270static struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 419 TLV_DB_RANGE_HEAD(5),
271 SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x29_L_HP_MIX, 1, 1, 0), 420 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
272 SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x29_L_HP_MIX, 0, 1, 0), 421 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
422 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
423 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
424 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
273}; 425};
274 426
275/* Right HeadPhone Mixer Switch */ 427static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
276static struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 428 struct snd_ctl_elem_value *ucontrol)
277 SOC_DAPM_SINGLE("DACR Switch", MAX98090_0x2A_R_HP_MIX, 1, 1, 0), 429{
278 SOC_DAPM_SINGLE("DACL Switch", MAX98090_0x2A_R_HP_MIX, 0, 1, 0), 430 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
431 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
432 struct soc_mixer_control *mc =
433 (struct soc_mixer_control *)kcontrol->private_value;
434 unsigned int mask = (1 << fls(mc->max)) - 1;
435 unsigned int val = snd_soc_read(codec, mc->reg);
436 unsigned int *select;
437
438 switch (mc->reg) {
439 case M98090_REG_MIC1_INPUT_LEVEL:
440 select = &(max98090->pa1en);
441 break;
442 case M98090_REG_MIC2_INPUT_LEVEL:
443 select = &(max98090->pa2en);
444 break;
445 case M98090_REG_ADC_SIDETONE:
446 select = &(max98090->sidetone);
447 break;
448 default:
449 return -EINVAL;
450 }
451
452 val = (val >> mc->shift) & mask;
453
454 if (val >= 1) {
455 /* If on, return the volume */
456 val = val - 1;
457 *select = val;
458 } else {
459 /* If off, return last stored value */
460 val = *select;
461 }
462
463 ucontrol->value.integer.value[0] = val;
464 return 0;
465}
466
467static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469{
470 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
471 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
472 struct soc_mixer_control *mc =
473 (struct soc_mixer_control *)kcontrol->private_value;
474 unsigned int mask = (1 << fls(mc->max)) - 1;
475 unsigned int sel = ucontrol->value.integer.value[0];
476 unsigned int val = snd_soc_read(codec, mc->reg);
477 unsigned int *select;
478
479 switch (mc->reg) {
480 case M98090_REG_MIC1_INPUT_LEVEL:
481 select = &(max98090->pa1en);
482 break;
483 case M98090_REG_MIC2_INPUT_LEVEL:
484 select = &(max98090->pa2en);
485 break;
486 case M98090_REG_ADC_SIDETONE:
487 select = &(max98090->sidetone);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 val = (val >> mc->shift) & mask;
494
495 *select = sel;
496
497 /* Setting a volume is only valid if it is already On */
498 if (val >= 1) {
499 sel = sel + 1;
500 } else {
501 /* Write what was already there */
502 sel = val;
503 }
504
505 snd_soc_update_bits(codec, mc->reg,
506 mask << mc->shift,
507 sel << mc->shift);
508
509 return 0;
510}
511
512static const char * max98090_perf_pwr_text[] =
513 { "High Performance", "Low Power" };
514static const char * max98090_pwr_perf_text[] =
515 { "Low Power", "High Performance" };
516
517static const struct soc_enum max98090_vcmbandgap_enum =
518 SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_SHIFT,
519 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
520
521static const char * max98090_osr128_text[] = { "64*fs", "128*fs" };
522
523static const struct soc_enum max98090_osr128_enum =
524 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_OSR128_SHIFT,
525 ARRAY_SIZE(max98090_osr128_text), max98090_osr128_text);
526
527static const char *max98090_mode_text[] = { "Voice", "Music" };
528
529static const struct soc_enum max98090_mode_enum =
530 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, M98090_MODE_SHIFT,
531 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
532
533static const struct soc_enum max98090_filter_dmic34mode_enum =
534 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG,
535 M98090_FLT_DMIC34MODE_SHIFT,
536 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
537
538static const char * max98090_drcatk_text[] =
539 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
540
541static const struct soc_enum max98090_drcatk_enum =
542 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCATK_SHIFT,
543 ARRAY_SIZE(max98090_drcatk_text), max98090_drcatk_text);
544
545static const char * max98090_drcrls_text[] =
546 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
547
548static const struct soc_enum max98090_drcrls_enum =
549 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCRLS_SHIFT,
550 ARRAY_SIZE(max98090_drcrls_text), max98090_drcrls_text);
551
552static const char * max98090_alccmp_text[] =
553 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
554
555static const struct soc_enum max98090_alccmp_enum =
556 SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR, M98090_DRCCMP_SHIFT,
557 ARRAY_SIZE(max98090_alccmp_text), max98090_alccmp_text);
558
559static const char * max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
560
561static const struct soc_enum max98090_drcexp_enum =
562 SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER, M98090_DRCEXP_SHIFT,
563 ARRAY_SIZE(max98090_drcexp_text), max98090_drcexp_text);
564
565static const struct soc_enum max98090_dac_perfmode_enum =
566 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_PERFMODE_SHIFT,
567 ARRAY_SIZE(max98090_perf_pwr_text), max98090_perf_pwr_text);
568
569static const struct soc_enum max98090_dachp_enum =
570 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_DACHP_SHIFT,
571 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
572
573static const struct soc_enum max98090_adchp_enum =
574 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_ADCHP_SHIFT,
575 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
576
577static const struct snd_kcontrol_new max98090_snd_controls[] = {
578 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
579
580 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
581 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
582
583 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
584 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
585 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
586 max98090_put_enab_tlv, max98090_micboost_tlv),
587
588 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
589 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
590 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
591 max98090_put_enab_tlv, max98090_micboost_tlv),
592
593 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
594 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
595 max98090_mic_tlv),
596
597 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
598 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
599 max98090_mic_tlv),
600
601 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
602 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
603 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
604
605 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
606 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
607 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
608
609 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
610 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
611 max98090_line_tlv),
612
613 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
614 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
615 max98090_line_tlv),
616
617 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
618 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
619 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
620 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
621
622 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
623 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
624 max98090_avg_tlv),
625 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
626 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
627 max98090_avg_tlv),
628
629 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
630 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
631 max98090_av_tlv),
632 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
633 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
634 max98090_av_tlv),
635
636 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
637 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
638 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
639 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
640
641 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
642 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
643 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
644 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
645 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
646 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
647 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
648 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
649 SOC_ENUM("Filter Mode", max98090_mode_enum),
650 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
651 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
652 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
653 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
654 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
655 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
656 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
657 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
658 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
659 max98090_put_enab_tlv, max98090_micboost_tlv),
660 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
661 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
662 max98090_dvg_tlv),
663 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
664 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
665 max98090_dv_tlv),
666 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
667 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
668 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
669 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
670 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
671 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
672 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
673 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
674 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
675 1),
676 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
677 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
678 max98090_dv_tlv),
679
680 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
681 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
682 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
683 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
684 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
685 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
686 max98090_alcmakeup_tlv),
687 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
688 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
689 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
690 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
691 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
692 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
693 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
694 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
695
696 SOC_ENUM("DAC HP Playback Performance Mode",
697 max98090_dac_perfmode_enum),
698 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
699
700 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
701 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
702 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
703 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
704 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
705 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
706
707 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
708 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
709 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
710 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
711 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
712 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
713
714 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
715 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
716 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
717 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
718 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
719 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
720
721 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
722 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
723 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
724
725 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
726 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
727 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
728 0, max98090_spk_tlv),
729
730 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
731 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
732 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
733
734 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
735 M98090_HPLM_SHIFT, 1, 1),
736 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
737 M98090_HPRM_SHIFT, 1, 1),
738
739 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
740 M98090_SPLM_SHIFT, 1, 1),
741 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
742 M98090_SPRM_SHIFT, 1, 1),
743
744 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
745 M98090_RCVLM_SHIFT, 1, 1),
746 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
747 M98090_RCVRM_SHIFT, 1, 1),
748
749 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
750 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
751 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
752 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
753 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
754 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
755
756 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
757 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
758 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
279}; 759};
280 760
281static struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 761static const struct snd_kcontrol_new max98091_snd_controls[] = {
282 /* Output */ 762
763 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
764 M98090_DMIC34_ZEROPAD_SHIFT,
765 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
766
767 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
768 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
769 M98090_FLT_DMIC34HPF_SHIFT,
770 M98090_FLT_DMIC34HPF_NUM - 1, 0),
771
772 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
773 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
774 max98090_avg_tlv),
775 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
776 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
777 max98090_avg_tlv),
778
779 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
780 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
781 max98090_av_tlv),
782 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
783 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
784 max98090_av_tlv),
785
786 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
787 M98090_REG_DMIC34_BIQUAD_BASE, 15),
788 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
789 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
790
791 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
792 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
793 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
794};
795
796static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
797 struct snd_kcontrol *kcontrol, int event)
798{
799 struct snd_soc_codec *codec = w->codec;
800 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
801
802 unsigned int val = snd_soc_read(codec, w->reg);
803
804 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
805 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
806 else
807 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
808
809
810 if (val >= 1) {
811 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
812 max98090->pa1en = val - 1; /* Update for volatile */
813 } else {
814 max98090->pa2en = val - 1; /* Update for volatile */
815 }
816 }
817
818 switch (event) {
819 case SND_SOC_DAPM_POST_PMU:
820 /* If turning on, set to most recently selected volume */
821 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
822 val = max98090->pa1en + 1;
823 else
824 val = max98090->pa2en + 1;
825 break;
826 case SND_SOC_DAPM_POST_PMD:
827 /* If turning off, turn off */
828 val = 0;
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
835 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
836 val << M98090_MIC_PA1EN_SHIFT);
837 else
838 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
839 val << M98090_MIC_PA2EN_SHIFT);
840
841 return 0;
842}
843
844static const char *mic1_mux_text[] = { "IN12", "IN56" };
845
846static const struct soc_enum mic1_mux_enum =
847 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC1_SHIFT,
848 ARRAY_SIZE(mic1_mux_text), mic1_mux_text);
849
850static const struct snd_kcontrol_new max98090_mic1_mux =
851 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
852
853static const char *mic2_mux_text[] = { "IN34", "IN56" };
854
855static const struct soc_enum mic2_mux_enum =
856 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC2_SHIFT,
857 ARRAY_SIZE(mic2_mux_text), mic2_mux_text);
858
859static const struct snd_kcontrol_new max98090_mic2_mux =
860 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
861
862static const char * max98090_micpre_text[] = { "Off", "On" };
863
864static const struct soc_enum max98090_pa1en_enum =
865 SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
866 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
867
868static const struct soc_enum max98090_pa2en_enum =
869 SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
870 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
871
872/* LINEA mixer switch */
873static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
874 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
875 M98090_IN1SEEN_SHIFT, 1, 0),
876 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
877 M98090_IN3SEEN_SHIFT, 1, 0),
878 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
879 M98090_IN5SEEN_SHIFT, 1, 0),
880 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
881 M98090_IN34DIFF_SHIFT, 1, 0),
882};
883
884/* LINEB mixer switch */
885static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
886 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
887 M98090_IN2SEEN_SHIFT, 1, 0),
888 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
889 M98090_IN4SEEN_SHIFT, 1, 0),
890 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
891 M98090_IN6SEEN_SHIFT, 1, 0),
892 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
893 M98090_IN56DIFF_SHIFT, 1, 0),
894};
895
896/* Left ADC mixer switch */
897static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
898 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
899 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
900 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
901 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
902 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
903 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
904 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
905 M98090_MIXADL_LINEA_SHIFT, 1, 0),
906 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
907 M98090_MIXADL_LINEB_SHIFT, 1, 0),
908 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
909 M98090_MIXADL_MIC1_SHIFT, 1, 0),
910 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
911 M98090_MIXADL_MIC2_SHIFT, 1, 0),
912};
913
914/* Right ADC mixer switch */
915static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
916 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
917 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
918 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
919 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
920 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
921 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
922 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
923 M98090_MIXADR_LINEA_SHIFT, 1, 0),
924 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
925 M98090_MIXADR_LINEB_SHIFT, 1, 0),
926 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
927 M98090_MIXADR_MIC1_SHIFT, 1, 0),
928 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
929 M98090_MIXADR_MIC2_SHIFT, 1, 0),
930};
931
932static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
933
934static const struct soc_enum ltenl_mux_enum =
935 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
936 ARRAY_SIZE(lten_mux_text), lten_mux_text);
937
938static const struct soc_enum ltenr_mux_enum =
939 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
940 ARRAY_SIZE(lten_mux_text), lten_mux_text);
941
942static const struct snd_kcontrol_new max98090_ltenl_mux =
943 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
944
945static const struct snd_kcontrol_new max98090_ltenr_mux =
946 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
947
948static const char *lben_mux_text[] = { "Normal", "Loopback" };
949
950static const struct soc_enum lbenl_mux_enum =
951 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
952 ARRAY_SIZE(lben_mux_text), lben_mux_text);
953
954static const struct soc_enum lbenr_mux_enum =
955 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
956 ARRAY_SIZE(lben_mux_text), lben_mux_text);
957
958static const struct snd_kcontrol_new max98090_lbenl_mux =
959 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
960
961static const struct snd_kcontrol_new max98090_lbenr_mux =
962 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
963
964static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
965
966static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
967
968static const struct soc_enum stenl_mux_enum =
969 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSL_SHIFT,
970 ARRAY_SIZE(stenl_mux_text), stenl_mux_text);
971
972static const struct soc_enum stenr_mux_enum =
973 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSR_SHIFT,
974 ARRAY_SIZE(stenr_mux_text), stenr_mux_text);
975
976static const struct snd_kcontrol_new max98090_stenl_mux =
977 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
978
979static const struct snd_kcontrol_new max98090_stenr_mux =
980 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
981
982/* Left speaker mixer switch */
983static const struct
984 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
985 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
986 M98090_MIXSPL_DACL_SHIFT, 1, 0),
987 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
988 M98090_MIXSPL_DACR_SHIFT, 1, 0),
989 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
990 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
991 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
992 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
993 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
994 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
996 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
997};
998
999/* Right speaker mixer switch */
1000static const struct
1001 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1002 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1003 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1004 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1005 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1006 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1007 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1008 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1009 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1010 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1011 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1012 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1013 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1014};
1015
1016/* Left headphone mixer switch */
1017static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1018 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1019 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1021 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1022 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1023 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1024 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1025 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1026 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1027 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1028 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1029 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1030};
1031
1032/* Right headphone mixer switch */
1033static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1034 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1035 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1036 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1037 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1038 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1039 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1040 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1041 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1042 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1043 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1044 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1045 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1046};
1047
1048/* Left receiver mixer switch */
1049static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1050 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1051 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1052 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1053 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1054 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1055 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1056 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1057 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1058 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1059 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1060 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1061 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1062};
1063
1064/* Right receiver mixer switch */
1065static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1066 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1067 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1068 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1069 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1070 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1071 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1072 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1073 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1074 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1075 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1076 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1077 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1078};
1079
1080static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1081
1082static const struct soc_enum linmod_mux_enum =
1083 SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER, M98090_LINMOD_SHIFT,
1084 ARRAY_SIZE(linmod_mux_text), linmod_mux_text);
1085
1086static const struct snd_kcontrol_new max98090_linmod_mux =
1087 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1088
1089static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1090
1091/*
1092 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1093 */
1094static const struct soc_enum mixhplsel_mux_enum =
1095 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPLSEL_SHIFT,
1096 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1097
1098static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1099 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1100
1101static const struct soc_enum mixhprsel_mux_enum =
1102 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPRSEL_SHIFT,
1103 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1104
1105static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1106 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1107
1108static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1109
1110 SND_SOC_DAPM_INPUT("MIC1"),
1111 SND_SOC_DAPM_INPUT("MIC2"),
1112 SND_SOC_DAPM_INPUT("DMICL"),
1113 SND_SOC_DAPM_INPUT("DMICR"),
1114 SND_SOC_DAPM_INPUT("IN1"),
1115 SND_SOC_DAPM_INPUT("IN2"),
1116 SND_SOC_DAPM_INPUT("IN3"),
1117 SND_SOC_DAPM_INPUT("IN4"),
1118 SND_SOC_DAPM_INPUT("IN5"),
1119 SND_SOC_DAPM_INPUT("IN6"),
1120 SND_SOC_DAPM_INPUT("IN12"),
1121 SND_SOC_DAPM_INPUT("IN34"),
1122 SND_SOC_DAPM_INPUT("IN56"),
1123
1124 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1125 M98090_MBEN_SHIFT, 0, NULL, 0),
1126 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1127 M98090_SHDNN_SHIFT, 0, NULL, 0),
1128 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1129 M98090_SDIEN_SHIFT, 0, NULL, 0),
1130 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1131 M98090_SDOEN_SHIFT, 0, NULL, 0),
1132 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1133 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1134 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1135 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1136 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1137 M98090_AHPF_SHIFT, 0, NULL, 0),
1138
1139/*
1140 * Note: Sysclk and misc power supplies are taken care of by SHDN
1141 */
1142
1143 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1144 0, 0, &max98090_mic1_mux),
1145
1146 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1147 0, 0, &max98090_mic2_mux),
1148
1149 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1150 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1151 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1152
1153 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1154 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1155 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1156
1157 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1158 &max98090_linea_mixer_controls[0],
1159 ARRAY_SIZE(max98090_linea_mixer_controls)),
1160
1161 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1162 &max98090_lineb_mixer_controls[0],
1163 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1164
1165 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1166 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1167 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1168 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1169
1170 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1171 &max98090_left_adc_mixer_controls[0],
1172 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1173
1174 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1175 &max98090_right_adc_mixer_controls[0],
1176 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1177
1178 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1179 M98090_ADLEN_SHIFT, 0),
1180 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1181 M98090_ADREN_SHIFT, 0),
1182
1183 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1184 SND_SOC_NOPM, 0, 0),
1185 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1186 SND_SOC_NOPM, 0, 0),
1187
1188 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1189 0, 0, &max98090_lbenl_mux),
1190
1191 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1192 0, 0, &max98090_lbenr_mux),
1193
1194 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1195 0, 0, &max98090_ltenl_mux),
1196
1197 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1198 0, 0, &max98090_ltenr_mux),
1199
1200 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1201 0, 0, &max98090_stenl_mux),
1202
1203 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1204 0, 0, &max98090_stenr_mux),
1205
1206 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1207 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1208
1209 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1210 M98090_DALEN_SHIFT, 0),
1211 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1212 M98090_DAREN_SHIFT, 0),
1213
1214 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1215 &max98090_left_hp_mixer_controls[0],
1216 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1217
1218 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1219 &max98090_right_hp_mixer_controls[0],
1220 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1221
1222 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1223 &max98090_left_speaker_mixer_controls[0],
1224 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1225
1226 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1227 &max98090_right_speaker_mixer_controls[0],
1228 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1229
1230 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1231 &max98090_left_rcv_mixer_controls[0],
1232 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1233
1234 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1235 &max98090_right_rcv_mixer_controls[0],
1236 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1237
1238 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1239 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1240
1241 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1242 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1243
1244 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1245 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1246
1247 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1248 M98090_HPLEN_SHIFT, 0, NULL, 0),
1249 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1250 M98090_HPREN_SHIFT, 0, NULL, 0),
1251
1252 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1253 M98090_SPLEN_SHIFT, 0, NULL, 0),
1254 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1255 M98090_SPREN_SHIFT, 0, NULL, 0),
1256
1257 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1258 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1259 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1260 M98090_RCVREN_SHIFT, 0, NULL, 0),
1261
283 SND_SOC_DAPM_OUTPUT("HPL"), 1262 SND_SOC_DAPM_OUTPUT("HPL"),
284 SND_SOC_DAPM_OUTPUT("HPR"), 1263 SND_SOC_DAPM_OUTPUT("HPR"),
1264 SND_SOC_DAPM_OUTPUT("SPKL"),
1265 SND_SOC_DAPM_OUTPUT("SPKR"),
1266 SND_SOC_DAPM_OUTPUT("RCVL"),
1267 SND_SOC_DAPM_OUTPUT("RCVR"),
1268};
1269
1270static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
285 1271
286 /* PGA */ 1272 SND_SOC_DAPM_INPUT("DMIC3"),
287 SND_SOC_DAPM_PGA("HPL Out", MAX98090_0x3F_OUT_ENABLE, 7, 0, NULL, 0), 1273 SND_SOC_DAPM_INPUT("DMIC4"),
288 SND_SOC_DAPM_PGA("HPR Out", MAX98090_0x3F_OUT_ENABLE, 6, 0, NULL, 0),
289 1274
290 /* Mixer */ 1275 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
291 SND_SOC_DAPM_MIXER("HPL Mixer", SND_SOC_NOPM, 0, 0, 1276 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
292 max98090_left_hp_mixer_controls, 1277 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
293 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1278 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1279};
294 1280
295 SND_SOC_DAPM_MIXER("HPR Mixer", SND_SOC_NOPM, 0, 0, 1281static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
296 max98090_right_hp_mixer_controls, 1282
297 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1283 {"MIC1 Input", NULL, "MIC1"},
1284 {"MIC2 Input", NULL, "MIC2"},
1285
1286 {"DMICL", NULL, "DMICL_ENA"},
1287 {"DMICR", NULL, "DMICR_ENA"},
1288 {"DMICL", NULL, "AHPF"},
1289 {"DMICR", NULL, "AHPF"},
1290
1291 /* MIC1 input mux */
1292 {"MIC1 Mux", "IN12", "IN12"},
1293 {"MIC1 Mux", "IN56", "IN56"},
1294
1295 /* MIC2 input mux */
1296 {"MIC2 Mux", "IN34", "IN34"},
1297 {"MIC2 Mux", "IN56", "IN56"},
1298
1299 {"MIC1 Input", NULL, "MIC1 Mux"},
1300 {"MIC2 Input", NULL, "MIC2 Mux"},
1301
1302 /* Left ADC input mixer */
1303 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1304 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1305 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1306 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1307 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1308 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1309 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1310
1311 /* Right ADC input mixer */
1312 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1313 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1314 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1315 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1316 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1317 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1318 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1319
1320 /* Line A input mixer */
1321 {"LINEA Mixer", "IN1 Switch", "IN1"},
1322 {"LINEA Mixer", "IN3 Switch", "IN3"},
1323 {"LINEA Mixer", "IN5 Switch", "IN5"},
1324 {"LINEA Mixer", "IN34 Switch", "IN34"},
1325
1326 /* Line B input mixer */
1327 {"LINEB Mixer", "IN2 Switch", "IN2"},
1328 {"LINEB Mixer", "IN4 Switch", "IN4"},
1329 {"LINEB Mixer", "IN6 Switch", "IN6"},
1330 {"LINEB Mixer", "IN56 Switch", "IN56"},
1331
1332 {"LINEA Input", NULL, "LINEA Mixer"},
1333 {"LINEB Input", NULL, "LINEB Mixer"},
1334
1335 /* Inputs */
1336 {"ADCL", NULL, "Left ADC Mixer"},
1337 {"ADCR", NULL, "Right ADC Mixer"},
1338 {"ADCL", NULL, "SHDN"},
1339 {"ADCR", NULL, "SHDN"},
1340
1341 {"LBENL Mux", "Normal", "ADCL"},
1342 {"LBENL Mux", "Normal", "DMICL"},
1343 {"LBENL Mux", "Loopback", "LTENL Mux"},
1344 {"LBENR Mux", "Normal", "ADCR"},
1345 {"LBENR Mux", "Normal", "DMICR"},
1346 {"LBENR Mux", "Loopback", "LTENR Mux"},
1347
1348 {"AIFOUTL", NULL, "LBENL Mux"},
1349 {"AIFOUTR", NULL, "LBENR Mux"},
1350 {"AIFOUTL", NULL, "SHDN"},
1351 {"AIFOUTR", NULL, "SHDN"},
1352 {"AIFOUTL", NULL, "SDOEN"},
1353 {"AIFOUTR", NULL, "SDOEN"},
1354
1355 {"LTENL Mux", "Normal", "AIFINL"},
1356 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1357 {"LTENR Mux", "Normal", "AIFINR"},
1358 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1359
1360 {"DACL", NULL, "LTENL Mux"},
1361 {"DACR", NULL, "LTENR Mux"},
1362
1363 {"STENL Mux", "Sidetone Left", "ADCL"},
1364 {"STENL Mux", "Sidetone Left", "DMICL"},
1365 {"STENR Mux", "Sidetone Right", "ADCR"},
1366 {"STENR Mux", "Sidetone Right", "DMICR"},
1367 {"DACL", "NULL", "STENL Mux"},
1368 {"DACR", "NULL", "STENL Mux"},
1369
1370 {"AIFINL", NULL, "SHDN"},
1371 {"AIFINR", NULL, "SHDN"},
1372 {"AIFINL", NULL, "SDIEN"},
1373 {"AIFINR", NULL, "SDIEN"},
1374 {"DACL", NULL, "SHDN"},
1375 {"DACR", NULL, "SHDN"},
1376
1377 /* Left headphone output mixer */
1378 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1379 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1380 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1381 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1382 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1383 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1384
1385 /* Right headphone output mixer */
1386 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1387 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1388 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1389 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1390 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1391 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1392
1393 /* Left speaker output mixer */
1394 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1395 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1396 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1397 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1398 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1399 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1400
1401 /* Right speaker output mixer */
1402 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1403 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1404 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1405 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1406 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1407 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1408
1409 /* Left Receiver output mixer */
1410 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1411 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1412 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1413 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1414 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1415 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1416
1417 /* Right Receiver output mixer */
1418 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1419 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1420 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1421 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1422 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1423 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1424
1425 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1426
1427 /*
1428 * Disable this for lowest power if bypassing
1429 * the DAC with an analog signal
1430 */
1431 {"HP Left Out", NULL, "DACL"},
1432 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1433
1434 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1435
1436 /*
1437 * Disable this for lowest power if bypassing
1438 * the DAC with an analog signal
1439 */
1440 {"HP Right Out", NULL, "DACR"},
1441 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1442
1443 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1444 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1445 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1446
1447 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1448 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1449 {"RCV Right Out", NULL, "LINMOD Mux"},
1450
1451 {"HPL", NULL, "HP Left Out"},
1452 {"HPR", NULL, "HP Right Out"},
1453 {"SPKL", NULL, "SPK Left Out"},
1454 {"SPKR", NULL, "SPK Right Out"},
1455 {"RCVL", NULL, "RCV Left Out"},
1456 {"RCVR", NULL, "RCV Right Out"},
298 1457
299 /* DAC */
300 SND_SOC_DAPM_DAC("DACL", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 0, 0),
301 SND_SOC_DAPM_DAC("DACR", "Hifi Playback", MAX98090_0x3F_OUT_ENABLE, 1, 0),
302}; 1458};
303 1459
304static struct snd_soc_dapm_route max98090_audio_map[] = { 1460static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
305 /* Output */ 1461
306 {"HPL", NULL, "HPL Out"}, 1462 /* DMIC inputs */
307 {"HPR", NULL, "HPR Out"}, 1463 {"DMIC3", NULL, "DMIC3_ENA"},
1464 {"DMIC4", NULL, "DMIC4_ENA"},
1465 {"DMIC3", NULL, "AHPF"},
1466 {"DMIC4", NULL, "AHPF"},
1467
1468};
1469
1470static int max98090_add_widgets(struct snd_soc_codec *codec)
1471{
1472 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1473 struct snd_soc_dapm_context *dapm = &codec->dapm;
1474
1475 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1476 ARRAY_SIZE(max98090_snd_controls));
308 1477
309 /* PGA */ 1478 if (max98090->devtype == MAX98091) {
310 {"HPL Out", NULL, "HPL Mixer"}, 1479 snd_soc_add_codec_controls(codec, max98091_snd_controls,
311 {"HPR Out", NULL, "HPR Mixer"}, 1480 ARRAY_SIZE(max98091_snd_controls));
1481 }
1482
1483 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1484 ARRAY_SIZE(max98090_dapm_widgets));
1485
1486 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1487 ARRAY_SIZE(max98090_dapm_routes));
1488
1489 if (max98090->devtype == MAX98091) {
1490 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1491 ARRAY_SIZE(max98091_dapm_widgets));
1492
1493 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1494 ARRAY_SIZE(max98091_dapm_routes));
1495
1496 }
312 1497
313 /* Mixer*/ 1498 return 0;
314 {"HPL Mixer", "DACR Switch", "DACR"}, 1499}
315 {"HPL Mixer", "DACL Switch", "DACL"}, 1500
1501static const int pclk_rates[] = {
1502 12000000, 12000000, 13000000, 13000000,
1503 16000000, 16000000, 19200000, 19200000
1504};
1505
1506static const int lrclk_rates[] = {
1507 8000, 16000, 8000, 16000,
1508 8000, 16000, 8000, 16000
1509};
316 1510
317 {"HPR Mixer", "DACR Switch", "DACR"}, 1511static const int user_pclk_rates[] = {
318 {"HPR Mixer", "DACL Switch", "DACL"}, 1512 13000000, 13000000
319}; 1513};
320 1514
321static bool max98090_volatile(struct device *dev, unsigned int reg) 1515static const int user_lrclk_rates[] = {
1516 44100, 48000
1517};
1518
1519static const unsigned long long ni_value[] = {
1520 3528, 768
1521};
1522
1523static const unsigned long long mi_value[] = {
1524 8125, 1625
1525};
1526
1527static void max98090_configure_bclk(struct snd_soc_codec *codec)
322{ 1528{
323 if ((reg == MAX98090_0x01_INT_STS) || 1529 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
324 (reg == MAX98090_0x02_JACK_STS) || 1530 unsigned long long ni;
325 (reg > MAX98090_REG_MAX_CACHED)) 1531 int i;
326 return true; 1532
1533 if (!max98090->sysclk) {
1534 dev_err(codec->dev, "No SYSCLK configured\n");
1535 return;
1536 }
1537
1538 if (!max98090->bclk || !max98090->lrclk) {
1539 dev_err(codec->dev, "No audio clocks configured\n");
1540 return;
1541 }
1542
1543 /* Skip configuration when operating as slave */
1544 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1545 M98090_MAS_MASK)) {
1546 return;
1547 }
327 1548
328 return false; 1549 /* Check for supported PCLK to LRCLK ratios */
1550 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1551 if ((pclk_rates[i] == max98090->sysclk) &&
1552 (lrclk_rates[i] == max98090->lrclk)) {
1553 dev_dbg(codec->dev,
1554 "Found supported PCLK to LRCLK rates 0x%x\n",
1555 i + 0x8);
1556
1557 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1558 M98090_FREQ_MASK,
1559 (i + 0x8) << M98090_FREQ_SHIFT);
1560 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1561 M98090_USE_M1_MASK, 0);
1562 return;
1563 }
1564 }
1565
1566 /* Check for user calculated MI and NI ratios */
1567 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1568 if ((user_pclk_rates[i] == max98090->sysclk) &&
1569 (user_lrclk_rates[i] == max98090->lrclk)) {
1570 dev_dbg(codec->dev,
1571 "Found user supported PCLK to LRCLK rates\n");
1572 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1573 i, ni_value[i], mi_value[i]);
1574
1575 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1576 M98090_FREQ_MASK, 0);
1577 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1578 M98090_USE_M1_MASK,
1579 1 << M98090_USE_M1_SHIFT);
1580
1581 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1582 (ni_value[i] >> 8) & 0x7F);
1583 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1584 ni_value[i] & 0xFF);
1585 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1586 (mi_value[i] >> 8) & 0x7F);
1587 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1588 mi_value[i] & 0xFF);
1589
1590 return;
1591 }
1592 }
1593
1594 /*
1595 * Calculate based on MI = 65536 (not as good as either method above)
1596 */
1597 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1598 M98090_FREQ_MASK, 0);
1599 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1600 M98090_USE_M1_MASK, 0);
1601
1602 /*
1603 * Configure NI when operating as master
1604 * Note: There is a small, but significant audio quality improvement
1605 * by calculating ni and mi.
1606 */
1607 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1608 * (unsigned long long int)max98090->lrclk;
1609 do_div(ni, (unsigned long long int)max98090->sysclk);
1610 dev_info(codec->dev, "No better method found\n");
1611 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1612 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1613 (ni >> 8) & 0x7F);
1614 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
329} 1615}
330 1616
331static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1617static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
332 struct snd_pcm_hw_params *params, 1618 unsigned int fmt)
333 struct snd_soc_dai *dai)
334{ 1619{
335 struct snd_soc_codec *codec = dai->codec; 1620 struct snd_soc_codec *codec = codec_dai->codec;
336 unsigned int val; 1621 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1622 struct max98090_cdata *cdata;
1623 u8 regval;
1624
1625 max98090->dai_fmt = fmt;
1626 cdata = &max98090->dai[0];
1627
1628 if (fmt != cdata->fmt) {
1629 cdata->fmt = fmt;
1630
1631 regval = 0;
1632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1633 case SND_SOC_DAIFMT_CBS_CFS:
1634 /* Set to slave mode PLL - MAS mode off */
1635 snd_soc_write(codec,
1636 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1637 snd_soc_write(codec,
1638 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1639 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1640 M98090_USE_M1_MASK, 0);
1641 break;
1642 case SND_SOC_DAIFMT_CBM_CFM:
1643 /* Set to master mode */
1644 if (max98090->tdm_slots == 4) {
1645 /* TDM */
1646 regval |= M98090_MAS_MASK |
1647 M98090_BSEL_64;
1648 } else if (max98090->tdm_slots == 3) {
1649 /* TDM */
1650 regval |= M98090_MAS_MASK |
1651 M98090_BSEL_48;
1652 } else {
1653 /* Few TDM slots, or No TDM */
1654 regval |= M98090_MAS_MASK |
1655 M98090_BSEL_32;
1656 }
1657 break;
1658 case SND_SOC_DAIFMT_CBS_CFM:
1659 case SND_SOC_DAIFMT_CBM_CFS:
1660 default:
1661 dev_err(codec->dev, "DAI clock mode unsupported");
1662 return -EINVAL;
1663 }
1664 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1665
1666 regval = 0;
1667 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1668 case SND_SOC_DAIFMT_I2S:
1669 regval |= M98090_DLY_MASK;
1670 break;
1671 case SND_SOC_DAIFMT_LEFT_J:
1672 break;
1673 case SND_SOC_DAIFMT_RIGHT_J:
1674 regval |= M98090_RJ_MASK;
1675 break;
1676 case SND_SOC_DAIFMT_DSP_A:
1677 /* Not supported mode */
1678 default:
1679 dev_err(codec->dev, "DAI format unsupported");
1680 return -EINVAL;
1681 }
1682
1683 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1684 case SND_SOC_DAIFMT_NB_NF:
1685 break;
1686 case SND_SOC_DAIFMT_NB_IF:
1687 regval |= M98090_WCI_MASK;
1688 break;
1689 case SND_SOC_DAIFMT_IB_NF:
1690 regval |= M98090_BCI_MASK;
1691 break;
1692 case SND_SOC_DAIFMT_IB_IF:
1693 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1694 break;
1695 default:
1696 dev_err(codec->dev, "DAI invert mode unsupported");
1697 return -EINVAL;
1698 }
1699
1700 /*
1701 * This accommodates an inverted logic in the MAX98090 chip
1702 * for Bit Clock Invert (BCI). The inverted logic is only
1703 * seen for the case of TDM mode. The remaining cases have
1704 * normal logic.
1705 */
1706 if (max98090->tdm_slots > 1) {
1707 regval ^= M98090_BCI_MASK;
1708 }
1709
1710 snd_soc_write(codec,
1711 M98090_REG_INTERFACE_FORMAT, regval);
1712 }
337 1713
338 switch (params_rate(params)) { 1714 return 0;
339 case 96000: 1715}
340 val = 1 << 5; 1716
341 break; 1717static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
342 case 32000: 1718 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
343 val = 1 << 4; 1719{
344 break; 1720 struct snd_soc_codec *codec = codec_dai->codec;
345 case 48000: 1721 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
346 val = 1 << 3; 1722 struct max98090_cdata *cdata;
1723 cdata = &max98090->dai[0];
1724
1725 if (slots < 0 || slots > 4)
1726 return -EINVAL;
1727
1728 max98090->tdm_slots = slots;
1729 max98090->tdm_width = slot_width;
1730
1731 if (max98090->tdm_slots > 1) {
1732 /* SLOTL SLOTR SLOTDLY */
1733 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1734 0 << M98090_TDM_SLOTL_SHIFT |
1735 1 << M98090_TDM_SLOTR_SHIFT |
1736 0 << M98090_TDM_SLOTDLY_SHIFT);
1737
1738 /* FSW TDM */
1739 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1740 M98090_TDM_MASK,
1741 M98090_TDM_MASK);
1742 }
1743
1744 /*
1745 * Normally advisable to set TDM first, but this permits either order
1746 */
1747 cdata->fmt = 0;
1748 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1749
1750 return 0;
1751}
1752
1753static int max98090_set_bias_level(struct snd_soc_codec *codec,
1754 enum snd_soc_bias_level level)
1755{
1756 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1757 int ret;
1758
1759 switch (level) {
1760 case SND_SOC_BIAS_ON:
1761 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1762 ret = regcache_sync(max98090->regmap);
1763
1764 if (ret != 0) {
1765 dev_err(codec->dev,
1766 "Failed to sync cache: %d\n", ret);
1767 return ret;
1768 }
1769 }
1770
1771 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1772 /*
1773 * Set to normal bias level.
1774 */
1775 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1776 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1777 }
347 break; 1778 break;
348 case 44100: 1779
349 val = 1 << 2; 1780 case SND_SOC_BIAS_PREPARE:
350 break; 1781 break;
351 case 16000: 1782
352 val = 1 << 1; 1783 case SND_SOC_BIAS_STANDBY:
1784 case SND_SOC_BIAS_OFF:
1785 /* Set internal pull-up to lowest power mode */
1786 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1787 M98090_JDWK_MASK, M98090_JDWK_MASK);
1788 regcache_mark_dirty(max98090->regmap);
353 break; 1789 break;
354 case 8000: 1790 }
355 val = 1 << 0; 1791 codec->dapm.bias_level = level;
1792 return 0;
1793}
1794
1795static const int comp_pclk_rates[] = {
1796 11289600, 12288000, 12000000, 13000000, 19200000
1797};
1798
1799static const int dmic_micclk[] = {
1800 2, 2, 2, 2, 4, 2
1801};
1802
1803static const int comp_lrclk_rates[] = {
1804 8000, 16000, 32000, 44100, 48000, 96000
1805};
1806
1807static const int dmic_comp[6][6] = {
1808 {7, 8, 3, 3, 3, 3},
1809 {7, 8, 3, 3, 3, 3},
1810 {7, 8, 3, 3, 3, 3},
1811 {7, 8, 3, 1, 1, 1},
1812 {7, 8, 3, 1, 2, 2},
1813 {7, 8, 3, 3, 3, 3}
1814};
1815
1816static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1817 struct snd_pcm_hw_params *params,
1818 struct snd_soc_dai *dai)
1819{
1820 struct snd_soc_codec *codec = dai->codec;
1821 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1822 struct max98090_cdata *cdata;
1823 int i, j;
1824
1825 cdata = &max98090->dai[0];
1826 max98090->bclk = snd_soc_params_to_bclk(params);
1827 if (params_channels(params) == 1)
1828 max98090->bclk *= 2;
1829
1830 max98090->lrclk = params_rate(params);
1831
1832 switch (params_format(params)) {
1833 case SNDRV_PCM_FORMAT_S16_LE:
1834 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1835 M98090_WS_MASK, 0);
356 break; 1836 break;
357 default: 1837 default:
358 dev_err(codec->dev, "unsupported rate\n");
359 return -EINVAL; 1838 return -EINVAL;
360 } 1839 }
361 snd_soc_update_bits(codec, MAX98090_0x05_SAMPLE_RATE, 0x03F, val); 1840
1841 max98090_configure_bclk(codec);
1842
1843 cdata->rate = max98090->lrclk;
1844
1845 /* Update filter mode */
1846 if (max98090->lrclk < 24000)
1847 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1848 M98090_MODE_MASK, 0);
1849 else
1850 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1851 M98090_MODE_MASK, M98090_MODE_MASK);
1852
1853 /* Update sample rate mode */
1854 if (max98090->lrclk < 50000)
1855 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1856 M98090_DHF_MASK, 0);
1857 else
1858 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1859 M98090_DHF_MASK, M98090_DHF_MASK);
1860
1861 /* Check for supported PCLK to LRCLK ratios */
1862 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1863 if (comp_pclk_rates[j] == max98090->sysclk) {
1864 break;
1865 }
1866 }
1867
1868 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1869 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1870 comp_lrclk_rates[i + 1]) / 2) {
1871 break;
1872 }
1873 }
1874
1875 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1876 M98090_MICCLK_MASK,
1877 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1878
1879 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1880 M98090_DMIC_COMP_MASK,
1881 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
362 1882
363 return 0; 1883 return 0;
364} 1884}
365 1885
1886/*
1887 * PLL / Sysclk
1888 */
366static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1889static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
367 int clk_id, unsigned int freq, int dir) 1890 int clk_id, unsigned int freq, int dir)
368{ 1891{
369 struct snd_soc_codec *codec = dai->codec; 1892 struct snd_soc_codec *codec = dai->codec;
370 unsigned int val; 1893 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
371 1894
372 snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, 1895 /* Requested clock frequency is already setup */
373 MAX98090_SHDNRUN, 0); 1896 if (freq == max98090->sysclk)
374 1897 return 0;
375 switch (freq) { 1898
376 case 26000000: 1899 /* Setup clocks for slave mode, and using the PLL
377 val = 1 << 7; 1900 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
378 break; 1901 * 0x02 (when master clk is 20MHz to 40MHz)..
379 case 19200000: 1902 * 0x03 (when master clk is 40MHz to 60MHz)..
380 val = 1 << 6; 1903 */
381 break; 1904 if ((freq >= 10000000) && (freq < 20000000)) {
382 case 13000000: 1905 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
383 val = 1 << 5; 1906 M98090_PSCLK_DIV1);
384 break; 1907 } else if ((freq >= 20000000) && (freq < 40000000)) {
385 case 12288000: 1908 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
386 val = 1 << 4; 1909 M98090_PSCLK_DIV2);
387 break; 1910 } else if ((freq >= 40000000) && (freq < 60000000)) {
388 case 12000000: 1911 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
389 val = 1 << 3; 1912 M98090_PSCLK_DIV4);
390 break; 1913 } else {
391 case 11289600:
392 val = 1 << 2;
393 break;
394 default:
395 dev_err(codec->dev, "Invalid master clock frequency\n"); 1914 dev_err(codec->dev, "Invalid master clock frequency\n");
396 return -EINVAL; 1915 return -EINVAL;
397 } 1916 }
398 snd_soc_update_bits(codec, MAX98090_0x04_SYS_CLK, 0xFD, val);
399 1917
400 snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, 1918 max98090->sysclk = freq;
401 MAX98090_SHDNRUN, MAX98090_SHDNRUN);
402 1919
403 dev_dbg(dai->dev, "sysclk is %uHz\n", freq); 1920 max98090_configure_bclk(codec);
404 1921
405 return 0; 1922 return 0;
406} 1923}
407 1924
408static int max98090_dai_set_fmt(struct snd_soc_dai *dai, 1925static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
409 unsigned int fmt)
410{ 1926{
411 struct snd_soc_codec *codec = dai->codec; 1927 struct snd_soc_codec *codec = codec_dai->codec;
412 int is_master; 1928 int regval;
413 u8 val;
414 1929
415 /* master/slave mode */ 1930 regval = mute ? M98090_DVM_MASK : 0;
416 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1931 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
417 case SND_SOC_DAIFMT_CBM_CFM: 1932 M98090_DVM_MASK, regval);
418 is_master = 1; 1933
419 break; 1934 return 0;
420 case SND_SOC_DAIFMT_CBS_CFS: 1935}
421 is_master = 0; 1936
422 break; 1937static void max98090_jack_work(struct work_struct *work)
423 default: 1938{
424 dev_err(codec->dev, "unsupported clock\n"); 1939 struct max98090_priv *max98090 = container_of(work,
425 return -EINVAL; 1940 struct max98090_priv,
1941 jack_work.work);
1942 struct snd_soc_codec *codec = max98090->codec;
1943 struct snd_soc_dapm_context *dapm = &codec->dapm;
1944 int status = 0;
1945 int reg;
1946
1947 /* Read a second time */
1948 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1949
1950 /* Strong pull up allows mic detection */
1951 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1952 M98090_JDWK_MASK, 0);
1953
1954 msleep(50);
1955
1956 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1957
1958 /* Weak pull up allows only insertion detection */
1959 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1960 M98090_JDWK_MASK, M98090_JDWK_MASK);
1961 } else {
1962 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
426 } 1963 }
427 1964
428 /* format */ 1965 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
429 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1966
430 case SND_SOC_DAIFMT_I2S: 1967 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
431 val = (is_master) ? MAX98090_I2S_M : MAX98090_I2S_S; 1968 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
432 break; 1969 dev_dbg(codec->dev, "No Headset Detected\n");
433 case SND_SOC_DAIFMT_RIGHT_J: 1970
434 val = (is_master) ? MAX98090_RJ_M : MAX98090_RJ_S; 1971 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
435 break; 1972
436 case SND_SOC_DAIFMT_LEFT_J: 1973 status |= 0;
437 val = (is_master) ? MAX98090_LJ_M : MAX98090_LJ_S; 1974
438 break; 1975 break;
439 default: 1976
440 dev_err(codec->dev, "unsupported format\n"); 1977 case 0:
441 return -EINVAL; 1978 if (max98090->jack_state ==
1979 M98090_JACK_STATE_HEADSET) {
1980
1981 dev_dbg(codec->dev,
1982 "Headset Button Down Detected\n");
1983
1984 /*
1985 * max98090_headset_button_event(codec)
1986 * could be defined, then called here.
1987 */
1988
1989 status |= SND_JACK_HEADSET;
1990 status |= SND_JACK_BTN_0;
1991
1992 break;
1993 }
1994
1995 /* Line is reported as Headphone */
1996 /* Nokia Headset is reported as Headphone */
1997 /* Mono Headphone is reported as Headphone */
1998 dev_dbg(codec->dev, "Headphone Detected\n");
1999
2000 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2001
2002 status |= SND_JACK_HEADPHONE;
2003
2004 break;
2005
2006 case M98090_JKSNS_MASK:
2007 dev_dbg(codec->dev, "Headset Detected\n");
2008
2009 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2010
2011 status |= SND_JACK_HEADSET;
2012
2013 break;
2014
2015 default:
2016 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2017 break;
2018 }
2019
2020 snd_soc_jack_report(max98090->jack, status,
2021 SND_JACK_HEADSET | SND_JACK_BTN_0);
2022
2023 snd_soc_dapm_sync(dapm);
2024}
2025
2026static irqreturn_t max98090_interrupt(int irq, void *data)
2027{
2028 struct snd_soc_codec *codec = data;
2029 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2030 int ret;
2031 unsigned int mask;
2032 unsigned int active;
2033
2034 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2035
2036 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2037
2038 if (ret != 0) {
2039 dev_err(codec->dev,
2040 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2041 ret);
2042 return IRQ_NONE;
2043 }
2044
2045 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2046
2047 if (ret != 0) {
2048 dev_err(codec->dev,
2049 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2050 ret);
2051 return IRQ_NONE;
2052 }
2053
2054 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2055 active, mask, active & mask);
2056
2057 active &= mask;
2058
2059 if (!active)
2060 return IRQ_NONE;
2061
2062 if (active & M98090_CLD_MASK) {
2063 dev_err(codec->dev, "M98090_CLD_MASK\n");
2064 }
2065
2066 if (active & M98090_SLD_MASK) {
2067 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
442 } 2068 }
443 snd_soc_update_bits(codec, MAX98090_0x06_DAI_IF, 2069
444 MAX98090_DAI_IF_MASK, val); 2070 if (active & M98090_ULK_MASK) {
2071 dev_err(codec->dev, "M98090_ULK_MASK\n");
2072 }
2073
2074 if (active & M98090_JDET_MASK) {
2075 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2076
2077 pm_wakeup_event(codec->dev, 100);
2078
2079 schedule_delayed_work(&max98090->jack_work,
2080 msecs_to_jiffies(100));
2081 }
2082
2083 if (active & M98090_DRCACT_MASK) {
2084 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2085 }
2086
2087 if (active & M98090_DRCCLP_MASK) {
2088 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2089 }
2090
2091 return IRQ_HANDLED;
2092}
2093
2094/**
2095 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2096 *
2097 * @codec: MAX98090 codec
2098 * @jack: jack to report detection events on
2099 *
2100 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2101 * being used to bring out signals to the processor then only platform
2102 * data configuration is needed for MAX98090 and processor GPIOs should
2103 * be configured using snd_soc_jack_add_gpios() instead.
2104 *
2105 * If no jack is supplied detection will be disabled.
2106 */
2107int max98090_mic_detect(struct snd_soc_codec *codec,
2108 struct snd_soc_jack *jack)
2109{
2110 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2111
2112 dev_dbg(codec->dev, "max98090_mic_detect\n");
2113
2114 max98090->jack = jack;
2115 if (jack) {
2116 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2117 M98090_IJDET_MASK,
2118 1 << M98090_IJDET_SHIFT);
2119 } else {
2120 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2121 M98090_IJDET_MASK,
2122 0);
2123 }
2124
2125 /* Send an initial empty report */
2126 snd_soc_jack_report(max98090->jack, 0,
2127 SND_JACK_HEADSET | SND_JACK_BTN_0);
2128
2129 schedule_delayed_work(&max98090->jack_work,
2130 msecs_to_jiffies(100));
445 2131
446 return 0; 2132 return 0;
447} 2133}
2134EXPORT_SYMBOL_GPL(max98090_mic_detect);
448 2135
449#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2136#define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
450#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2137#define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
451 2138
452static struct snd_soc_dai_ops max98090_dai_ops = { 2139static struct snd_soc_dai_ops max98090_dai_ops = {
453 .set_sysclk = max98090_dai_set_sysclk, 2140 .set_sysclk = max98090_dai_set_sysclk,
454 .set_fmt = max98090_dai_set_fmt, 2141 .set_fmt = max98090_dai_set_fmt,
455 .hw_params = max98090_dai_hw_params, 2142 .set_tdm_slot = max98090_set_tdm_slot,
2143 .hw_params = max98090_dai_hw_params,
2144 .digital_mute = max98090_dai_digital_mute,
456}; 2145};
457 2146
458static struct snd_soc_dai_driver max98090_dai = { 2147static struct snd_soc_dai_driver max98090_dai[] = {
459 .name = "max98090-Hifi", 2148{
2149 .name = "HiFi",
460 .playback = { 2150 .playback = {
461 .stream_name = "Playback", 2151 .stream_name = "HiFi Playback",
462 .channels_min = 1, 2152 .channels_min = 2,
463 .channels_max = 2, 2153 .channels_max = 2,
464 .rates = MAX98090_RATES, 2154 .rates = MAX98090_RATES,
465 .formats = MAX98090_FORMATS, 2155 .formats = MAX98090_FORMATS,
2156 },
2157 .capture = {
2158 .stream_name = "HiFi Capture",
2159 .channels_min = 1,
2160 .channels_max = 2,
2161 .rates = MAX98090_RATES,
2162 .formats = MAX98090_FORMATS,
466 }, 2163 },
467 .ops = &max98090_dai_ops, 2164 .ops = &max98090_dai_ops,
2165}
468}; 2166};
469 2167
2168static void max98090_handle_pdata(struct snd_soc_codec *codec)
2169{
2170 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2171 struct max98090_pdata *pdata = max98090->pdata;
2172
2173 if (!pdata) {
2174 dev_err(codec->dev, "No platform data\n");
2175 return;
2176 }
2177
2178}
2179
470static int max98090_probe(struct snd_soc_codec *codec) 2180static int max98090_probe(struct snd_soc_codec *codec)
471{ 2181{
472 struct max98090_priv *priv = snd_soc_codec_get_drvdata(codec); 2182 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
473 struct device *dev = codec->dev; 2183 struct max98090_cdata *cdata;
474 int ret; 2184 int ret = 0;
2185
2186 dev_dbg(codec->dev, "max98090_probe\n");
2187
2188 max98090->codec = codec;
2189
2190 codec->control_data = max98090->regmap;
475 2191
476 codec->control_data = priv->regmap;
477 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); 2192 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
478 if (ret < 0) { 2193 if (ret != 0) {
479 dev_err(dev, "Failed to set cache I/O: %d\n", ret); 2194 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
480 return ret; 2195 return ret;
481 } 2196 }
482 2197
483 /* Device active */ 2198 /* Reset the codec, the DSP core, and disable all interrupts */
484 snd_soc_update_bits(codec, MAX98090_0x45_DEV_SHUTDOWN, 2199 max98090_reset(max98090);
485 MAX98090_SHDNRUN, MAX98090_SHDNRUN);
486 2200
487 return 0; 2201 /* Initialize private data */
2202
2203 max98090->sysclk = (unsigned)-1;
2204
2205 cdata = &max98090->dai[0];
2206 cdata->rate = (unsigned)-1;
2207 cdata->fmt = (unsigned)-1;
2208
2209 max98090->lin_state = 0;
2210 max98090->pa1en = 0;
2211 max98090->pa2en = 0;
2212 max98090->extmic_mux = 0;
2213
2214 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2215 if (ret < 0) {
2216 dev_err(codec->dev, "Failed to read device revision: %d\n",
2217 ret);
2218 goto err_access;
2219 }
2220
2221 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2222 max98090->devtype = MAX98090;
2223 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2224 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2225 max98090->devtype = MAX98091;
2226 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2227 } else {
2228 max98090->devtype = MAX98090;
2229 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2230 }
2231
2232 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2233
2234 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2235
2236 /* Enable jack detection */
2237 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2238 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2239
2240 /* Register for interrupts */
2241 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2242
2243 ret = request_threaded_irq(max98090->irq, NULL,
2244 max98090_interrupt, IRQF_TRIGGER_FALLING,
2245 "max98090_interrupt", codec);
2246 if (ret < 0) {
2247 dev_err(codec->dev, "request_irq failed: %d\n",
2248 ret);
2249 }
2250
2251 /*
2252 * Clear any old interrupts.
2253 * An old interrupt ocurring prior to installing the ISR
2254 * can keep a new interrupt from generating a trigger.
2255 */
2256 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2257
2258 /* High Performance is default */
2259 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2260 M98090_DACHP_MASK,
2261 1 << M98090_DACHP_SHIFT);
2262 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2263 M98090_PERFMODE_MASK,
2264 0 << M98090_PERFMODE_SHIFT);
2265 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2266 M98090_ADCHP_MASK,
2267 1 << M98090_ADCHP_SHIFT);
2268
2269 /* Turn on VCM bandgap reference */
2270 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2271 M98090_VCM_MODE_MASK);
2272
2273 max98090_handle_pdata(codec);
2274
2275 max98090_add_widgets(codec);
2276
2277err_access:
2278 return ret;
488} 2279}
489 2280
490static int max98090_remove(struct snd_soc_codec *codec) 2281static int max98090_remove(struct snd_soc_codec *codec)
491{ 2282{
2283 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2284
2285 cancel_delayed_work_sync(&max98090->jack_work);
2286
492 return 0; 2287 return 0;
493} 2288}
494 2289
495static struct snd_soc_codec_driver soc_codec_dev_max98090 = { 2290static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
496 .probe = max98090_probe, 2291 .probe = max98090_probe,
497 .remove = max98090_remove, 2292 .remove = max98090_remove,
498 .controls = max98090_snd_controls, 2293 .set_bias_level = max98090_set_bias_level,
499 .num_controls = ARRAY_SIZE(max98090_snd_controls),
500 .dapm_widgets = max98090_dapm_widgets,
501 .num_dapm_widgets = ARRAY_SIZE(max98090_dapm_widgets),
502 .dapm_routes = max98090_audio_map,
503 .num_dapm_routes = ARRAY_SIZE(max98090_audio_map),
504}; 2294};
505 2295
506static const struct regmap_config max98090_regmap = { 2296static const struct regmap_config max98090_regmap = {
507 .reg_bits = 8, 2297 .reg_bits = 8,
508 .val_bits = 8, 2298 .val_bits = 8,
509 .max_register = MAX98090_REG_END, 2299
510 .volatile_reg = max98090_volatile, 2300 .max_register = MAX98090_MAX_REGISTER,
511 .cache_type = REGCACHE_RBTREE, 2301 .reg_defaults = max98090_reg,
512 .reg_defaults = max98090_reg_defaults, 2302 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
513 .num_reg_defaults = ARRAY_SIZE(max98090_reg_defaults), 2303 .volatile_reg = max98090_volatile_register,
2304 .readable_reg = max98090_readable_register,
2305 .cache_type = REGCACHE_RBTREE,
514}; 2306};
515 2307
516static int max98090_i2c_probe(struct i2c_client *i2c, 2308static int max98090_i2c_probe(struct i2c_client *i2c,
517 const struct i2c_device_id *id) 2309 const struct i2c_device_id *id)
518{ 2310{
519 struct max98090_priv *priv; 2311 struct max98090_priv *max98090;
520 struct device *dev = &i2c->dev;
521 unsigned int val;
522 int ret; 2312 int ret;
523 2313
524 priv = devm_kzalloc(dev, sizeof(struct max98090_priv), 2314 pr_debug("max98090_i2c_probe\n");
525 GFP_KERNEL);
526 if (!priv)
527 return -ENOMEM;
528
529 priv->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
530 if (IS_ERR(priv->regmap)) {
531 ret = PTR_ERR(priv->regmap);
532 dev_err(dev, "Failed to init regmap: %d\n", ret);
533 return ret;
534 }
535 2315
536 i2c_set_clientdata(i2c, priv); 2316 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2317 GFP_KERNEL);
2318 if (max98090 == NULL)
2319 return -ENOMEM;
537 2320
538 ret = regmap_read(priv->regmap, MAX98090_0xFF_REV_ID, &val); 2321 max98090->devtype = id->driver_data;
539 if (ret < 0) { 2322 i2c_set_clientdata(i2c, max98090);
540 dev_err(dev, "Failed to read device revision: %d\n", ret); 2323 max98090->control_data = i2c;
541 return ret; 2324 max98090->pdata = i2c->dev.platform_data;
2325 max98090->irq = i2c->irq;
2326
2327 max98090->regmap = regmap_init_i2c(i2c, &max98090_regmap);
2328 if (IS_ERR(max98090->regmap)) {
2329 ret = PTR_ERR(max98090->regmap);
2330 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2331 goto err_enable;
542 } 2332 }
543 dev_info(dev, "revision 0x%02x\n", val);
544 2333
545 ret = snd_soc_register_codec(dev, 2334 ret = snd_soc_register_codec(&i2c->dev,
546 &soc_codec_dev_max98090, 2335 &soc_codec_dev_max98090, max98090_dai,
547 &max98090_dai, 1); 2336 ARRAY_SIZE(max98090_dai));
2337 if (ret < 0)
2338 regmap_exit(max98090->regmap);
548 2339
2340err_enable:
549 return ret; 2341 return ret;
550} 2342}
551 2343
552static int max98090_i2c_remove(struct i2c_client *client) 2344static int max98090_i2c_remove(struct i2c_client *client)
553{ 2345{
2346 struct max98090_priv *max98090 = dev_get_drvdata(&client->dev);
554 snd_soc_unregister_codec(&client->dev); 2347 snd_soc_unregister_codec(&client->dev);
2348 regmap_exit(max98090->regmap);
2349 return 0;
2350}
2351
2352static int max98090_runtime_resume(struct device *dev)
2353{
2354 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2355
2356 regcache_cache_only(max98090->regmap, false);
2357
2358 regcache_sync(max98090->regmap);
2359
555 return 0; 2360 return 0;
556} 2361}
557 2362
2363static int max98090_runtime_suspend(struct device *dev)
2364{
2365 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2366
2367 regcache_cache_only(max98090->regmap, true);
2368
2369 return 0;
2370}
2371
2372static struct dev_pm_ops max98090_pm = {
2373 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2374 max98090_runtime_resume, NULL)
2375};
2376
558static const struct i2c_device_id max98090_i2c_id[] = { 2377static const struct i2c_device_id max98090_i2c_id[] = {
559 { "max98090", 0 }, 2378 { "max98090", MAX98090 },
560 { } 2379 { }
561}; 2380};
562MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2381MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
@@ -565,13 +2384,15 @@ static struct i2c_driver max98090_i2c_driver = {
565 .driver = { 2384 .driver = {
566 .name = "max98090", 2385 .name = "max98090",
567 .owner = THIS_MODULE, 2386 .owner = THIS_MODULE,
2387 .pm = &max98090_pm,
568 }, 2388 },
569 .probe = max98090_i2c_probe, 2389 .probe = max98090_i2c_probe,
570 .remove = max98090_i2c_remove, 2390 .remove = max98090_i2c_remove,
571 .id_table = max98090_i2c_id, 2391 .id_table = max98090_i2c_id,
572}; 2392};
2393
573module_i2c_driver(max98090_i2c_driver); 2394module_i2c_driver(max98090_i2c_driver);
574 2395
575MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2396MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
576MODULE_AUTHOR("Peter Hsiang, Kuninori Morimoto"); 2397MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
577MODULE_LICENSE("GPL"); 2398MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98090.h b/sound/soc/codecs/max98090.h
new file mode 100755
index 000000000000..7e103f249053
--- /dev/null
+++ b/sound/soc/codecs/max98090.h
@@ -0,0 +1,1549 @@
1/*
2 * max98090.h -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _MAX98090_H
12#define _MAX98090_H
13
14#include <linux/version.h>
15
16/* One can override the Linux version here with an explicit version number */
17#define M98090_LINUX_VERSION LINUX_VERSION_CODE
18
19/*
20 * MAX98090 Register Definitions
21 */
22
23#define M98090_REG_SOFTWARE_RESET 0x00
24#define M98090_REG_DEVICE_STATUS 0x01
25#define M98090_REG_JACK_STATUS 0x02
26#define M98090_REG_INTERRUPT_S 0x03
27#define M98090_REG_QUICK_SYSTEM_CLOCK 0x04
28#define M98090_REG_QUICK_SAMPLE_RATE 0x05
29#define M98090_REG_DAI_INTERFACE 0x06
30#define M98090_REG_DAC_PATH 0x07
31#define M98090_REG_MIC_DIRECT_TO_ADC 0x08
32#define M98090_REG_LINE_TO_ADC 0x09
33#define M98090_REG_ANALOG_MIC_LOOP 0x0A
34#define M98090_REG_ANALOG_LINE_LOOP 0x0B
35#define M98090_REG_RESERVED 0x0C
36#define M98090_REG_LINE_INPUT_CONFIG 0x0D
37#define M98090_REG_LINE_INPUT_LEVEL 0x0E
38#define M98090_REG_INPUT_MODE 0x0F
39#define M98090_REG_MIC1_INPUT_LEVEL 0x10
40#define M98090_REG_MIC2_INPUT_LEVEL 0x11
41#define M98090_REG_MIC_BIAS_VOLTAGE 0x12
42#define M98090_REG_DIGITAL_MIC_ENABLE 0x13
43#define M98090_REG_DIGITAL_MIC_CONFIG 0x14
44#define M98090_REG_LEFT_ADC_MIXER 0x15
45#define M98090_REG_RIGHT_ADC_MIXER 0x16
46#define M98090_REG_LEFT_ADC_LEVEL 0x17
47#define M98090_REG_RIGHT_ADC_LEVEL 0x18
48#define M98090_REG_ADC_BIQUAD_LEVEL 0x19
49#define M98090_REG_ADC_SIDETONE 0x1A
50#define M98090_REG_SYSTEM_CLOCK 0x1B
51#define M98090_REG_CLOCK_MODE 0x1C
52#define M98090_REG_CLOCK_RATIO_NI_MSB 0x1D
53#define M98090_REG_CLOCK_RATIO_NI_LSB 0x1E
54#define M98090_REG_CLOCK_RATIO_MI_MSB 0x1F
55#define M98090_REG_CLOCK_RATIO_MI_LSB 0x20
56#define M98090_REG_MASTER_MODE 0x21
57#define M98090_REG_INTERFACE_FORMAT 0x22
58#define M98090_REG_TDM_CONTROL 0x23
59#define M98090_REG_TDM_FORMAT 0x24
60#define M98090_REG_IO_CONFIGURATION 0x25
61#define M98090_REG_FILTER_CONFIG 0x26
62#define M98090_REG_DAI_PLAYBACK_LEVEL 0x27
63#define M98090_REG_DAI_PLAYBACK_LEVEL_EQ 0x28
64#define M98090_REG_LEFT_HP_MIXER 0x29
65#define M98090_REG_RIGHT_HP_MIXER 0x2A
66#define M98090_REG_HP_CONTROL 0x2B
67#define M98090_REG_LEFT_HP_VOLUME 0x2C
68#define M98090_REG_RIGHT_HP_VOLUME 0x2D
69#define M98090_REG_LEFT_SPK_MIXER 0x2E
70#define M98090_REG_RIGHT_SPK_MIXER 0x2F
71#define M98090_REG_SPK_CONTROL 0x30
72#define M98090_REG_LEFT_SPK_VOLUME 0x31
73#define M98090_REG_RIGHT_SPK_VOLUME 0x32
74#define M98090_REG_DRC_TIMING 0x33
75#define M98090_REG_DRC_COMPRESSOR 0x34
76#define M98090_REG_DRC_EXPANDER 0x35
77#define M98090_REG_DRC_GAIN 0x36
78#define M98090_REG_RCV_LOUTL_MIXER 0x37
79#define M98090_REG_RCV_LOUTL_CONTROL 0x38
80#define M98090_REG_RCV_LOUTL_VOLUME 0x39
81#define M98090_REG_LOUTR_MIXER 0x3A
82#define M98090_REG_LOUTR_CONTROL 0x3B
83#define M98090_REG_LOUTR_VOLUME 0x3C
84#define M98090_REG_JACK_DETECT 0x3D
85#define M98090_REG_INPUT_ENABLE 0x3E
86#define M98090_REG_OUTPUT_ENABLE 0x3F
87#define M98090_REG_LEVEL_CONTROL 0x40
88#define M98090_REG_DSP_FILTER_ENABLE 0x41
89#define M98090_REG_BIAS_CONTROL 0x42
90#define M98090_REG_DAC_CONTROL 0x43
91#define M98090_REG_ADC_CONTROL 0x44
92#define M98090_REG_DEVICE_SHUTDOWN 0x45
93#define M98090_REG_EQUALIZER_BASE 0x46
94#define M98090_REG_RECORD_BIQUAD_BASE 0xAF
95#define M98090_REG_DMIC3_VOLUME 0xBE
96#define M98090_REG_DMIC4_VOLUME 0xBF
97#define M98090_REG_DMIC34_BQ_PREATTEN 0xC0
98#define M98090_REG_RECORD_TDM_SLOT 0xC1
99#define M98090_REG_SAMPLE_RATE 0xC2
100#define M98090_REG_DMIC34_BIQUAD_BASE 0xC3
101#define M98090_REG_REVISION_ID 0xFF
102
103#define M98090_REG_CNT (0xFF+1)
104#define MAX98090_MAX_REGISTER 0xFF
105
106/* MAX98090 Register Bit Fields */
107
108/*
109 * M98090_REG_SOFTWARE_RESET
110 */
111#define M98090_SWRESET_MASK (1<<7)
112#define M98090_SWRESET_SHIFT 7
113#define M98090_SWRESET_WIDTH 1
114
115/*
116 * M98090_REG_DEVICE_STATUS
117 */
118#define M98090_CLD_MASK (1<<7)
119#define M98090_CLD_SHIFT 7
120#define M98090_CLD_WIDTH 1
121#define M98090_SLD_MASK (1<<6)
122#define M98090_SLD_SHIFT 6
123#define M98090_SLD_WIDTH 1
124#define M98090_ULK_MASK (1<<5)
125#define M98090_ULK_SHIFT 5
126#define M98090_ULK_WIDTH 1
127#define M98090_JDET_MASK (1<<2)
128#define M98090_JDET_SHIFT 2
129#define M98090_JDET_WIDTH 1
130#define M98090_DRCACT_MASK (1<<1)
131#define M98090_DRCACT_SHIFT 1
132#define M98090_DRCACT_WIDTH 1
133#define M98090_DRCCLP_MASK (1<<0)
134#define M98090_DRCCLP_SHIFT 0
135#define M98090_DRCCLP_WIDTH 1
136
137/*
138 * M98090_REG_JACK_STATUS
139 */
140#define M98090_LSNS_MASK (1<<2)
141#define M98090_LSNS_SHIFT 2
142#define M98090_LSNS_WIDTH 1
143#define M98090_JKSNS_MASK (1<<1)
144#define M98090_JKSNS_SHIFT 1
145#define M98090_JKSNS_WIDTH 1
146
147/*
148 * M98090_REG_INTERRUPT_S
149 */
150#define M98090_ICLD_MASK (1<<7)
151#define M98090_ICLD_SHIFT 7
152#define M98090_ICLD_WIDTH 1
153#define M98090_ISLD_MASK (1<<6)
154#define M98090_ISLD_SHIFT 6
155#define M98090_ISLD_WIDTH 1
156#define M98090_IULK_MASK (1<<5)
157#define M98090_IULK_SHIFT 5
158#define M98090_IULK_WIDTH 1
159#define M98090_IJDET_MASK (1<<2)
160#define M98090_IJDET_SHIFT 2
161#define M98090_IJDET_WIDTH 1
162#define M98090_IDRCACT_MASK (1<<1)
163#define M98090_IDRCACT_SHIFT 1
164#define M98090_IDRCACT_WIDTH 1
165#define M98090_IDRCCLP_MASK (1<<0)
166#define M98090_IDRCCLP_SHIFT 0
167#define M98090_IDRCCLP_WIDTH 1
168
169/*
170 * M98090_REG_QUICK_SYSTEM_CLOCK
171 */
172#define M98090_26M_MASK (1<<7)
173#define M98090_26M_SHIFT 7
174#define M98090_26M_WIDTH 1
175#define M98090_19P2M_MASK (1<<6)
176#define M98090_19P2M_SHIFT 6
177#define M98090_19P2M_WIDTH 1
178#define M98090_13M_MASK (1<<5)
179#define M98090_13M_SHIFT 5
180#define M98090_13M_WIDTH 1
181#define M98090_12P288M_MASK (1<<4)
182#define M98090_12P288M_SHIFT 4
183#define M98090_12P288M_WIDTH 1
184#define M98090_12M_MASK (1<<3)
185#define M98090_12M_SHIFT 3
186#define M98090_12M_WIDTH 1
187#define M98090_11P2896M_MASK (1<<2)
188#define M98090_11P2896M_SHIFT 2
189#define M98090_11P2896M_WIDTH 1
190#define M98090_256FS_MASK (1<<0)
191#define M98090_256FS_SHIFT 0
192#define M98090_256FS_WIDTH 1
193#define M98090_CLK_ALL_SHIFT 0
194#define M98090_CLK_ALL_WIDTH 8
195#define M98090_CLK_ALL_NUM (1<<M98090_CLK_ALL_WIDTH)
196
197/*
198 * M98090_REG_QUICK_SAMPLE_RATE
199 */
200#define M98090_SR_96K_MASK (1<<5)
201#define M98090_SR_96K_SHIFT 5
202#define M98090_SR_96K_WIDTH 1
203#define M98090_SR_32K_MASK (1<<4)
204#define M98090_SR_32K_SHIFT 4
205#define M98090_SR_32K_WIDTH 1
206#define M98090_SR_48K_MASK (1<<3)
207#define M98090_SR_48K_SHIFT 3
208#define M98090_SR_48K_WIDTH 1
209#define M98090_SR_44K1_MASK (1<<2)
210#define M98090_SR_44K1_SHIFT 2
211#define M98090_SR_44K1_WIDTH 1
212#define M98090_SR_16K_MASK (1<<1)
213#define M98090_SR_16K_SHIFT 1
214#define M98090_SR_16K_WIDTH 1
215#define M98090_SR_8K_MASK (1<<0)
216#define M98090_SR_8K_SHIFT 0
217#define M98090_SR_8K_WIDTH 1
218#define M98090_SR_MASK 0x3F
219#define M98090_SR_ALL_SHIFT 0
220#define M98090_SR_ALL_WIDTH 8
221#define M98090_SR_ALL_NUM (1<<M98090_SR_ALL_WIDTH)
222
223/*
224 * M98090_REG_DAI_INTERFACE
225 */
226#define M98090_RJ_M_MASK (1<<5)
227#define M98090_RJ_M_SHIFT 5
228#define M98090_RJ_M_WIDTH 1
229#define M98090_RJ_S_MASK (1<<4)
230#define M98090_RJ_S_SHIFT 4
231#define M98090_RJ_S_WIDTH 1
232#define M98090_LJ_M_MASK (1<<3)
233#define M98090_LJ_M_SHIFT 3
234#define M98090_LJ_M_WIDTH 1
235#define M98090_LJ_S_MASK (1<<2)
236#define M98090_LJ_S_SHIFT 2
237#define M98090_LJ_S_WIDTH 1
238#define M98090_I2S_M_MASK (1<<1)
239#define M98090_I2S_M_SHIFT 1
240#define M98090_I2S_M_WIDTH 1
241#define M98090_I2S_S_MASK (1<<0)
242#define M98090_I2S_S_SHIFT 0
243#define M98090_I2S_S_WIDTH 1
244#define M98090_DAI_ALL_SHIFT 0
245#define M98090_DAI_ALL_WIDTH 8
246#define M98090_DAI_ALL_NUM (1<<M98090_DAI_ALL_WIDTH)
247
248/*
249 * M98090_REG_DAC_PATH
250 */
251#define M98090_DIG2_HP_MASK (1<<7)
252#define M98090_DIG2_HP_SHIFT 7
253#define M98090_DIG2_HP_WIDTH 1
254#define M98090_DIG2_EAR_MASK (1<<6)
255#define M98090_DIG2_EAR_SHIFT 6
256#define M98090_DIG2_EAR_WIDTH 1
257#define M98090_DIG2_SPK_MASK (1<<5)
258#define M98090_DIG2_SPK_SHIFT 5
259#define M98090_DIG2_SPK_WIDTH 1
260#define M98090_DIG2_LOUT_MASK (1<<4)
261#define M98090_DIG2_LOUT_SHIFT 4
262#define M98090_DIG2_LOUT_WIDTH 1
263#define M98090_DIG2_ALL_SHIFT 0
264#define M98090_DIG2_ALL_WIDTH 8
265#define M98090_DIG2_ALL_NUM (1<<M98090_DIG2_ALL_WIDTH)
266
267/*
268 * M98090_REG_MIC_DIRECT_TO_ADC
269 */
270#define M98090_IN12_MIC1_MASK (1<<7)
271#define M98090_IN12_MIC1_SHIFT 7
272#define M98090_IN12_MIC1_WIDTH 1
273#define M98090_IN34_MIC2_MASK (1<<6)
274#define M98090_IN34_MIC2_SHIFT 6
275#define M98090_IN34_MIC2_WIDTH 1
276#define M98090_IN56_MIC1_MASK (1<<5)
277#define M98090_IN56_MIC1_SHIFT 5
278#define M98090_IN56_MIC1_WIDTH 1
279#define M98090_IN56_MIC2_MASK (1<<4)
280#define M98090_IN56_MIC2_SHIFT 4
281#define M98090_IN56_MIC2_WIDTH 1
282#define M98090_IN12_DADC_MASK (1<<3)
283#define M98090_IN12_DADC_SHIFT 3
284#define M98090_IN12_DADC_WIDTH 1
285#define M98090_IN34_DADC_MASK (1<<2)
286#define M98090_IN34_DADC_SHIFT 2
287#define M98090_IN34_DADC_WIDTH 1
288#define M98090_IN56_DADC_MASK (1<<1)
289#define M98090_IN56_DADC_SHIFT 1
290#define M98090_IN56_DADC_WIDTH 1
291#define M98090_MIC_ALL_SHIFT 0
292#define M98090_MIC_ALL_WIDTH 8
293#define M98090_MIC_ALL_NUM (1<<M98090_MIC_ALL_WIDTH)
294
295/*
296 * M98090_REG_LINE_TO_ADC
297 */
298#define M98090_IN12S_AB_MASK (1<<7)
299#define M98090_IN12S_AB_SHIFT 7
300#define M98090_IN12S_AB_WIDTH 1
301#define M98090_IN34S_AB_MASK (1<<6)
302#define M98090_IN34S_AB_SHIFT 6
303#define M98090_IN34S_AB_WIDTH 1
304#define M98090_IN56S_AB_MASK (1<<5)
305#define M98090_IN56S_AB_SHIFT 5
306#define M98090_IN56S_AB_WIDTH 1
307#define M98090_IN34D_A_MASK (1<<4)
308#define M98090_IN34D_A_SHIFT 4
309#define M98090_IN34D_A_WIDTH 1
310#define M98090_IN56D_B_MASK (1<<3)
311#define M98090_IN56D_B_SHIFT 3
312#define M98090_IN56D_B_WIDTH 1
313#define M98090_LINE_ALL_SHIFT 0
314#define M98090_LINE_ALL_WIDTH 8
315#define M98090_LINE_ALL_NUM (1<<M98090_LINE_ALL_WIDTH)
316
317/*
318 * M98090_REG_ANALOG_MIC_LOOP
319 */
320#define M98090_IN12_M1HPL_MASK (1<<7)
321#define M98090_IN12_M1HPL_SHIFT 7
322#define M98090_IN12_M1HPL_WIDTH 1
323#define M98090_IN12_M1SPKL_MASK (1<<6)
324#define M98090_IN12_M1SPKL_SHIFT 6
325#define M98090_IN12_M1SPKL_WIDTH 1
326#define M98090_IN12_M1EAR_MASK (1<<5)
327#define M98090_IN12_M1EAR_SHIFT 5
328#define M98090_IN12_M1EAR_WIDTH 1
329#define M98090_IN12_M1LOUTL_MASK (1<<4)
330#define M98090_IN12_M1LOUTL_SHIFT 4
331#define M98090_IN12_M1LOUTL_WIDTH 1
332#define M98090_IN34_M2HPR_MASK (1<<3)
333#define M98090_IN34_M2HPR_SHIFT 3
334#define M98090_IN34_M2HPR_WIDTH 1
335#define M98090_IN34_M2SPKR_MASK (1<<2)
336#define M98090_IN34_M2SPKR_SHIFT 2
337#define M98090_IN34_M2SPKR_WIDTH 1
338#define M98090_IN34_M2EAR_MASK (1<<1)
339#define M98090_IN34_M2EAR_SHIFT 1
340#define M98090_IN34_M2EAR_WIDTH 1
341#define M98090_IN34_M2LOUTR_MASK (1<<0)
342#define M98090_IN34_M2LOUTR_SHIFT 0
343#define M98090_IN34_M2LOUTR_WIDTH 1
344#define M98090_AMIC_ALL_SHIFT 0
345#define M98090_AMIC_ALL_WIDTH 8
346#define M98090_AMIC_ALL_NUM (1<<M98090_AMIC_ALL_WIDTH)
347
348/*
349 * M98090_REG_ANALOG_LINE_LOOP
350 */
351#define M98090_IN12S_ABHP_MASK (1<<7)
352#define M98090_IN12S_ABHP_SHIFT 7
353#define M98090_IN12S_ABHP_WIDTH 1
354#define M98090_IN34D_ASPKL_MASK (1<<6)
355#define M98090_IN34D_ASPKL_SHIFT 6
356#define M98090_IN34D_ASPKL_WIDTH 1
357#define M98090_IN34D_AEAR_MASK (1<<5)
358#define M98090_IN34D_AEAR_SHIFT 5
359#define M98090_IN34D_AEAR_WIDTH 1
360#define M98090_IN12S_ABLOUT_MASK (1<<4)
361#define M98090_IN12S_ABLOUT_SHIFT 4
362#define M98090_IN12S_ABLOUT_WIDTH 1
363#define M98090_IN34S_ABHP_MASK (1<<3)
364#define M98090_IN34S_ABHP_SHIFT 3
365#define M98090_IN34S_ABHP_WIDTH 1
366#define M98090_IN56D_BSPKR_MASK (1<<2)
367#define M98090_IN56D_BSPKR_SHIFT 2
368#define M98090_IN56D_BSPKR_WIDTH 1
369#define M98090_IN56D_BEAR_MASK (1<<1)
370#define M98090_IN56D_BEAR_SHIFT 1
371#define M98090_IN56D_BEAR_WIDTH 1
372#define M98090_IN34S_ABLOUT_MASK (1<<0)
373#define M98090_IN34S_ABLOUT_SHIFT 0
374#define M98090_IN34S_ABLOUT_WIDTH 1
375#define M98090_ALIN_ALL_SHIFT 0
376#define M98090_ALIN_ALL_WIDTH 8
377#define M98090_ALIN_ALL_NUM (1<<M98090_ALIN_ALL_WIDTH)
378
379/*
380 * M98090_REG_RESERVED
381 */
382
383/*
384 * M98090_REG_LINE_INPUT_CONFIG
385 */
386#define M98090_IN34DIFF_MASK (1<<7)
387#define M98090_IN34DIFF_SHIFT 7
388#define M98090_IN34DIFF_WIDTH 1
389#define M98090_IN56DIFF_MASK (1<<6)
390#define M98090_IN56DIFF_SHIFT 6
391#define M98090_IN56DIFF_WIDTH 1
392#define M98090_IN1SEEN_MASK (1<<5)
393#define M98090_IN1SEEN_SHIFT 5
394#define M98090_IN1SEEN_WIDTH 1
395#define M98090_IN2SEEN_MASK (1<<4)
396#define M98090_IN2SEEN_SHIFT 4
397#define M98090_IN2SEEN_WIDTH 1
398#define M98090_IN3SEEN_MASK (1<<3)
399#define M98090_IN3SEEN_SHIFT 3
400#define M98090_IN3SEEN_WIDTH 1
401#define M98090_IN4SEEN_MASK (1<<2)
402#define M98090_IN4SEEN_SHIFT 2
403#define M98090_IN4SEEN_WIDTH 1
404#define M98090_IN5SEEN_MASK (1<<1)
405#define M98090_IN5SEEN_SHIFT 1
406#define M98090_IN5SEEN_WIDTH 1
407#define M98090_IN6SEEN_MASK (1<<0)
408#define M98090_IN6SEEN_SHIFT 0
409#define M98090_IN6SEEN_WIDTH 1
410
411/*
412 * M98090_REG_LINE_INPUT_LEVEL
413 */
414#define M98090_MIXG135_MASK (1<<7)
415#define M98090_MIXG135_SHIFT 7
416#define M98090_MIXG135_WIDTH 1
417#define M98090_MIXG135_NUM (1<<M98090_MIXG135_WIDTH)
418#define M98090_MIXG246_MASK (1<<6)
419#define M98090_MIXG246_SHIFT 6
420#define M98090_MIXG246_WIDTH 1
421#define M98090_MIXG246_NUM (1<<M98090_MIXG246_WIDTH)
422#define M98090_LINAPGA_MASK (7<<3)
423#define M98090_LINAPGA_SHIFT 3
424#define M98090_LINAPGA_WIDTH 3
425#define M98090_LINAPGA_NUM 6
426#define M98090_LINBPGA_MASK (7<<0)
427#define M98090_LINBPGA_SHIFT 0
428#define M98090_LINBPGA_WIDTH 3
429#define M98090_LINBPGA_NUM 6
430
431/*
432 * M98090_REG_INPUT_MODE
433 */
434#define M98090_EXTBUFA_MASK (1<<7)
435#define M98090_EXTBUFA_SHIFT 7
436#define M98090_EXTBUFA_WIDTH 1
437#define M98090_EXTBUFA_NUM (1<<M98090_EXTBUFA_WIDTH)
438#define M98090_EXTBUFB_MASK (1<<6)
439#define M98090_EXTBUFB_SHIFT 6
440#define M98090_EXTBUFB_WIDTH 1
441#define M98090_EXTBUFB_NUM (1<<M98090_EXTBUFB_WIDTH)
442#define M98090_EXTMIC_MASK (3<<0)
443#define M98090_EXTMIC_SHIFT 0
444#define M98090_EXTMIC1_SHIFT 0
445#define M98090_EXTMIC2_SHIFT 1
446#define M98090_EXTMIC_WIDTH 2
447#define M98090_EXTMIC_NONE (0<<0)
448#define M98090_EXTMIC_MIC1 (1<<0)
449#define M98090_EXTMIC_MIC2 (2<<0)
450
451/*
452 * M98090_REG_MIC1_INPUT_LEVEL
453 */
454#define M98090_MIC_PA1EN_MASK (3<<5)
455#define M98090_MIC_PA1EN_SHIFT 5
456#define M98090_MIC_PA1EN_WIDTH 2
457#define M98090_MIC_PA1EN_NUM 3
458#define M98090_MIC_PGAM1_MASK (31<<0)
459#define M98090_MIC_PGAM1_SHIFT 0
460#define M98090_MIC_PGAM1_WIDTH 5
461#define M98090_MIC_PGAM1_NUM 21
462
463/*
464 * M98090_REG_MIC2_INPUT_LEVEL
465 */
466#define M98090_MIC_PA2EN_MASK (3<<5)
467#define M98090_MIC_PA2EN_SHIFT 5
468#define M98090_MIC_PA2EN_WIDTH 2
469#define M98090_MIC_PA2EN_NUM 3
470#define M98090_MIC_PGAM2_MASK (31<<0)
471#define M98090_MIC_PGAM2_SHIFT 0
472#define M98090_MIC_PGAM2_WIDTH 5
473#define M98090_MIC_PGAM2_NUM 21
474
475/*
476 * M98090_REG_MIC_BIAS_VOLTAGE
477 */
478#define M98090_MBVSEL_MASK (3<<0)
479#define M98090_MBVSEL_SHIFT 0
480#define M98090_MBVSEL_WIDTH 2
481#define M98090_MBVSEL_2V8 (3<<0)
482#define M98090_MBVSEL_2V55 (2<<0)
483#define M98090_MBVSEL_2V4 (1<<0)
484#define M98090_MBVSEL_2V2 (0<<0)
485
486/*
487 * M98090_REG_DIGITAL_MIC_ENABLE
488 */
489#define M98090_MICCLK_MASK (7<<4)
490#define M98090_MICCLK_SHIFT 4
491#define M98090_MICCLK_WIDTH 3
492#define M98090_DIGMIC4_MASK (1<<3)
493#define M98090_DIGMIC4_SHIFT 3
494#define M98090_DIGMIC4_WIDTH 1
495#define M98090_DIGMIC4_NUM (1<<M98090_DIGMIC4_WIDTH)
496#define M98090_DIGMIC3_MASK (1<<2)
497#define M98090_DIGMIC3_SHIFT 2
498#define M98090_DIGMIC3_WIDTH 1
499#define M98090_DIGMIC3_NUM (1<<M98090_DIGMIC3_WIDTH)
500#define M98090_DIGMICR_MASK (1<<1)
501#define M98090_DIGMICR_SHIFT 1
502#define M98090_DIGMICR_WIDTH 1
503#define M98090_DIGMICR_NUM (1<<M98090_DIGMICR_WIDTH)
504#define M98090_DIGMICL_MASK (1<<0)
505#define M98090_DIGMICL_SHIFT 0
506#define M98090_DIGMICL_WIDTH 1
507#define M98090_DIGMICL_NUM (1<<M98090_DIGMICL_WIDTH)
508
509/*
510 * M98090_REG_DIGITAL_MIC_CONFIG
511 */
512#define M98090_DMIC_COMP_MASK (15<<4)
513#define M98090_DMIC_COMP_SHIFT 4
514#define M98090_DMIC_COMP_WIDTH 4
515#define M98090_DMIC_COMP_NUM (1<<M98090_DMIC_COMP_WIDTH)
516#define M98090_DMIC_FREQ_MASK (3<<0)
517#define M98090_DMIC_FREQ_SHIFT 0
518#define M98090_DMIC_FREQ_WIDTH 2
519
520/*
521 * M98090_REG_LEFT_ADC_MIXER
522 */
523#define M98090_MIXADL_MIC2_MASK (1<<6)
524#define M98090_MIXADL_MIC2_SHIFT 6
525#define M98090_MIXADL_MIC2_WIDTH 1
526#define M98090_MIXADL_MIC1_MASK (1<<5)
527#define M98090_MIXADL_MIC1_SHIFT 5
528#define M98090_MIXADL_MIC1_WIDTH 1
529#define M98090_MIXADL_LINEB_MASK (1<<4)
530#define M98090_MIXADL_LINEB_SHIFT 4
531#define M98090_MIXADL_LINEB_WIDTH 1
532#define M98090_MIXADL_LINEA_MASK (1<<3)
533#define M98090_MIXADL_LINEA_SHIFT 3
534#define M98090_MIXADL_LINEA_WIDTH 1
535#define M98090_MIXADL_IN65DIFF_MASK (1<<2)
536#define M98090_MIXADL_IN65DIFF_SHIFT 2
537#define M98090_MIXADL_IN65DIFF_WIDTH 1
538#define M98090_MIXADL_IN34DIFF_MASK (1<<1)
539#define M98090_MIXADL_IN34DIFF_SHIFT 1
540#define M98090_MIXADL_IN34DIFF_WIDTH 1
541#define M98090_MIXADL_IN12DIFF_MASK (1<<0)
542#define M98090_MIXADL_IN12DIFF_SHIFT 0
543#define M98090_MIXADL_IN12DIFF_WIDTH 1
544#define M98090_MIXADL_MASK (255<<0)
545#define M98090_MIXADL_SHIFT 0
546#define M98090_MIXADL_WIDTH 8
547
548/*
549 * M98090_REG_RIGHT_ADC_MIXER
550 */
551#define M98090_MIXADR_MIC2_MASK (1<<6)
552#define M98090_MIXADR_MIC2_SHIFT 6
553#define M98090_MIXADR_MIC2_WIDTH 1
554#define M98090_MIXADR_MIC1_MASK (1<<5)
555#define M98090_MIXADR_MIC1_SHIFT 5
556#define M98090_MIXADR_MIC1_WIDTH 1
557#define M98090_MIXADR_LINEB_MASK (1<<4)
558#define M98090_MIXADR_LINEB_SHIFT 4
559#define M98090_MIXADR_LINEB_WIDTH 1
560#define M98090_MIXADR_LINEA_MASK (1<<3)
561#define M98090_MIXADR_LINEA_SHIFT 3
562#define M98090_MIXADR_LINEA_WIDTH 1
563#define M98090_MIXADR_IN65DIFF_MASK (1<<2)
564#define M98090_MIXADR_IN65DIFF_SHIFT 2
565#define M98090_MIXADR_IN65DIFF_WIDTH 1
566#define M98090_MIXADR_IN34DIFF_MASK (1<<1)
567#define M98090_MIXADR_IN34DIFF_SHIFT 1
568#define M98090_MIXADR_IN34DIFF_WIDTH 1
569#define M98090_MIXADR_IN12DIFF_MASK (1<<0)
570#define M98090_MIXADR_IN12DIFF_SHIFT 0
571#define M98090_MIXADR_IN12DIFF_WIDTH 1
572#define M98090_MIXADR_MASK (255<<0)
573#define M98090_MIXADR_SHIFT 0
574#define M98090_MIXADR_WIDTH 8
575
576/*
577 * M98090_REG_LEFT_ADC_LEVEL
578 */
579#define M98090_AVLG_MASK (7<<4)
580#define M98090_AVLG_SHIFT 4
581#define M98090_AVLG_WIDTH 3
582#define M98090_AVLG_NUM (1<<M98090_AVLG_WIDTH)
583#define M98090_AVL_MASK (15<<0)
584#define M98090_AVL_SHIFT 0
585#define M98090_AVL_WIDTH 4
586#define M98090_AVL_NUM (1<<M98090_AVL_WIDTH)
587
588/*
589 * M98090_REG_RIGHT_ADC_LEVEL
590 */
591#define M98090_AVRG_MASK (7<<4)
592#define M98090_AVRG_SHIFT 4
593#define M98090_AVRG_WIDTH 3
594#define M98090_AVRG_NUM (1<<M98090_AVRG_WIDTH)
595#define M98090_AVR_MASK (15<<0)
596#define M98090_AVR_SHIFT 0
597#define M98090_AVR_WIDTH 4
598#define M98090_AVR_NUM (1<<M98090_AVR_WIDTH)
599
600/*
601 * M98090_REG_ADC_BIQUAD_LEVEL
602 */
603#define M98090_AVBQ_MASK (15<<0)
604#define M98090_AVBQ_SHIFT 0
605#define M98090_AVBQ_WIDTH 4
606#define M98090_AVBQ_NUM (1<<M98090_AVBQ_WIDTH)
607
608/*
609 * M98090_REG_ADC_SIDETONE
610 */
611#define M98090_DSTSR_MASK (1<<7)
612#define M98090_DSTSR_SHIFT 7
613#define M98090_DSTSR_WIDTH 1
614#define M98090_DSTSL_MASK (1<<6)
615#define M98090_DSTSL_SHIFT 6
616#define M98090_DSTSL_WIDTH 1
617#define M98090_DVST_MASK (31<<0)
618#define M98090_DVST_SHIFT 0
619#define M98090_DVST_WIDTH 5
620#define M98090_DVST_NUM 31
621
622/*
623 * M98090_REG_SYSTEM_CLOCK
624 */
625#define M98090_PSCLK_MASK (3<<4)
626#define M98090_PSCLK_SHIFT 4
627#define M98090_PSCLK_WIDTH 2
628#define M98090_PSCLK_DISABLED (0<<4)
629#define M98090_PSCLK_DIV1 (1<<4)
630#define M98090_PSCLK_DIV2 (2<<4)
631#define M98090_PSCLK_DIV4 (3<<4)
632
633/*
634 * M98090_REG_CLOCK_MODE
635 */
636#define M98090_FREQ_MASK (15<<4)
637#define M98090_FREQ_SHIFT 4
638#define M98090_FREQ_WIDTH 4
639#define M98090_USE_M1_MASK (1<<0)
640#define M98090_USE_M1_SHIFT 0
641#define M98090_USE_M1_WIDTH 1
642#define M98090_USE_M1_NUM (1<<M98090_USE_M1_WIDTH)
643
644/*
645 * M98090_REG_CLOCK_RATIO_NI_MSB
646 */
647#define M98090_NI_HI_MASK (127<<0)
648#define M98090_NI_HI_SHIFT 0
649#define M98090_NI_HI_WIDTH 7
650#define M98090_NI_HI_NUM (1<<M98090_NI_HI_WIDTH)
651
652/*
653 * M98090_REG_CLOCK_RATIO_NI_LSB
654 */
655#define M98090_NI_LO_MASK (255<<0)
656#define M98090_NI_LO_SHIFT 0
657#define M98090_NI_LO_WIDTH 8
658#define M98090_NI_LO_NUM (1<<M98090_NI_LO_WIDTH)
659
660/*
661 * M98090_REG_CLOCK_RATIO_MI_MSB
662 */
663#define M98090_MI_HI_MASK (255<<0)
664#define M98090_MI_HI_SHIFT 0
665#define M98090_MI_HI_WIDTH 8
666#define M98090_MI_HI_NUM (1<<M98090_MI_HI_WIDTH)
667
668/*
669 * M98090_REG_CLOCK_RATIO_MI_LSB
670 */
671#define M98090_MI_LO_MASK (255<<0)
672#define M98090_MI_LO_SHIFT 0
673#define M98090_MI_LO_WIDTH 8
674#define M98090_MI_LO_NUM (1<<M98090_MI_LO_WIDTH)
675
676/*
677 * M98090_REG_MASTER_MODE
678 */
679#define M98090_MAS_MASK (1<<7)
680#define M98090_MAS_SHIFT 7
681#define M98090_MAS_WIDTH 1
682#define M98090_BSEL_MASK (1<<0)
683#define M98090_BSEL_SHIFT 0
684#define M98090_BSEL_WIDTH 1
685#define M98090_BSEL_32 (1<<0)
686#define M98090_BSEL_48 (2<<0)
687#define M98090_BSEL_64 (3<<0)
688
689/*
690 * M98090_REG_INTERFACE_FORMAT
691 */
692#define M98090_RJ_MASK (1<<5)
693#define M98090_RJ_SHIFT 5
694#define M98090_RJ_WIDTH 1
695#define M98090_WCI_MASK (1<<4)
696#define M98090_WCI_SHIFT 4
697#define M98090_WCI_WIDTH 1
698#define M98090_BCI_MASK (1<<3)
699#define M98090_BCI_SHIFT 3
700#define M98090_BCI_WIDTH 1
701#define M98090_DLY_MASK (1<<2)
702#define M98090_DLY_SHIFT 2
703#define M98090_DLY_WIDTH 1
704#define M98090_WS_MASK (3<<0)
705#define M98090_WS_SHIFT 0
706#define M98090_WS_WIDTH 2
707#define M98090_WS_NUM (1<<M98090_WS_WIDTH)
708
709/*
710 * M98090_REG_TDM_CONTROL
711 */
712#define M98090_FSW_MASK (1<<1)
713#define M98090_FSW_SHIFT 1
714#define M98090_FSW_WIDTH 1
715#define M98090_TDM_MASK (1<<0)
716#define M98090_TDM_SHIFT 0
717#define M98090_TDM_WIDTH 1
718#define M98090_TDM_NUM (1<<M98090_TDM_WIDTH)
719
720/*
721 * M98090_REG_TDM_FORMAT
722 */
723#define M98090_TDM_SLOTL_MASK (3<<6)
724#define M98090_TDM_SLOTL_SHIFT 6
725#define M98090_TDM_SLOTL_WIDTH 2
726#define M98090_TDM_SLOTL_NUM (1<<M98090_TDM_SLOTL_WIDTH)
727#define M98090_TDM_SLOTR_MASK (3<<4)
728#define M98090_TDM_SLOTR_SHIFT 4
729#define M98090_TDM_SLOTR_WIDTH 2
730#define M98090_TDM_SLOTR_NUM (1<<M98090_TDM_SLOTR_WIDTH)
731#define M98090_TDM_SLOTDLY_MASK (15<<0)
732#define M98090_TDM_SLOTDLY_SHIFT 0
733#define M98090_TDM_SLOTDLY_WIDTH 4
734#define M98090_TDM_SLOTDLY_NUM (1<<M98090_TDM_SLOTDLY_WIDTH)
735
736/*
737 * M98090_REG_IO_CONFIGURATION
738 */
739#define M98090_LTEN_MASK (1<<5)
740#define M98090_LTEN_SHIFT 5
741#define M98090_LTEN_WIDTH 1
742#define M98090_LTEN_NUM (1<<M98090_LTEN_WIDTH)
743#define M98090_LBEN_MASK (1<<4)
744#define M98090_LBEN_SHIFT 4
745#define M98090_LBEN_WIDTH 1
746#define M98090_LBEN_NUM (1<<M98090_LBEN_WIDTH)
747#define M98090_DMONO_MASK (1<<3)
748#define M98090_DMONO_SHIFT 3
749#define M98090_DMONO_WIDTH 1
750#define M98090_DMONO_NUM (1<<M98090_DMONO_WIDTH)
751#define M98090_HIZOFF_MASK (1<<2)
752#define M98090_HIZOFF_SHIFT 2
753#define M98090_HIZOFF_WIDTH 1
754#define M98090_HIZOFF_NUM (1<<M98090_HIZOFF_WIDTH)
755#define M98090_SDOEN_MASK (1<<1)
756#define M98090_SDOEN_SHIFT 1
757#define M98090_SDOEN_WIDTH 1
758#define M98090_SDOEN_NUM (1<<M98090_SDOEN_WIDTH)
759#define M98090_SDIEN_MASK (1<<0)
760#define M98090_SDIEN_SHIFT 0
761#define M98090_SDIEN_WIDTH 1
762#define M98090_SDIEN_NUM (1<<M98090_SDIEN_WIDTH)
763
764/*
765 * M98090_REG_FILTER_CONFIG
766 */
767#define M98090_MODE_MASK (1<<7)
768#define M98090_MODE_SHIFT 7
769#define M98090_MODE_WIDTH 1
770#define M98090_AHPF_MASK (1<<6)
771#define M98090_AHPF_SHIFT 6
772#define M98090_AHPF_WIDTH 1
773#define M98090_AHPF_NUM (1<<M98090_AHPF_WIDTH)
774#define M98090_DHPF_MASK (1<<5)
775#define M98090_DHPF_SHIFT 5
776#define M98090_DHPF_WIDTH 1
777#define M98090_DHPF_NUM (1<<M98090_DHPF_WIDTH)
778#define M98090_DHF_MASK (1<<4)
779#define M98090_DHF_SHIFT 4
780#define M98090_DHF_WIDTH 1
781#define M98090_FLT_DMIC34MODE_MASK (1<<3)
782#define M98090_FLT_DMIC34MODE_SHIFT 3
783#define M98090_FLT_DMIC34MODE_WIDTH 1
784#define M98090_FLT_DMIC34HPF_MASK (1<<2)
785#define M98090_FLT_DMIC34HPF_SHIFT 2
786#define M98090_FLT_DMIC34HPF_WIDTH 1
787#define M98090_FLT_DMIC34HPF_NUM (1<<M98090_FLT_DMIC34HPF_WIDTH)
788
789/*
790 * M98090_REG_DAI_PLAYBACK_LEVEL
791 */
792#define M98090_DVM_MASK (1<<7)
793#define M98090_DVM_SHIFT 7
794#define M98090_DVM_WIDTH 1
795#define M98090_DVG_MASK (3<<4)
796#define M98090_DVG_SHIFT 4
797#define M98090_DVG_WIDTH 2
798#define M98090_DVG_NUM (1<<M98090_DVG_WIDTH)
799#define M98090_DV_MASK (15<<0)
800#define M98090_DV_SHIFT 0
801#define M98090_DV_WIDTH 4
802#define M98090_DV_NUM (1<<M98090_DV_WIDTH)
803
804/*
805 * M98090_REG_DAI_PLAYBACK_LEVEL_EQ
806 */
807#define M98090_EQCLPN_MASK (1<<4)
808#define M98090_EQCLPN_SHIFT 4
809#define M98090_EQCLPN_WIDTH 1
810#define M98090_EQCLPN_NUM (1<<M98090_EQCLPN_WIDTH)
811#define M98090_DVEQ_MASK (15<<0)
812#define M98090_DVEQ_SHIFT 0
813#define M98090_DVEQ_WIDTH 4
814#define M98090_DVEQ_NUM (1<<M98090_DVEQ_WIDTH)
815
816/*
817 * M98090_REG_LEFT_HP_MIXER
818 */
819#define M98090_MIXHPL_MIC2_MASK (1<<5)
820#define M98090_MIXHPL_MIC2_SHIFT 5
821#define M98090_MIXHPL_MIC2_WIDTH 1
822#define M98090_MIXHPL_MIC1_MASK (1<<4)
823#define M98090_MIXHPL_MIC1_SHIFT 4
824#define M98090_MIXHPL_MIC1_WIDTH 1
825#define M98090_MIXHPL_LINEB_MASK (1<<3)
826#define M98090_MIXHPL_LINEB_SHIFT 3
827#define M98090_MIXHPL_LINEB_WIDTH 1
828#define M98090_MIXHPL_LINEA_MASK (1<<2)
829#define M98090_MIXHPL_LINEA_SHIFT 2
830#define M98090_MIXHPL_LINEA_WIDTH 1
831#define M98090_MIXHPL_DACR_MASK (1<<1)
832#define M98090_MIXHPL_DACR_SHIFT 1
833#define M98090_MIXHPL_DACR_WIDTH 1
834#define M98090_MIXHPL_DACL_MASK (1<<0)
835#define M98090_MIXHPL_DACL_SHIFT 0
836#define M98090_MIXHPL_DACL_WIDTH 1
837#define M98090_MIXHPL_MASK (63<<0)
838#define M98090_MIXHPL_SHIFT 0
839#define M98090_MIXHPL_WIDTH 6
840
841/*
842 * M98090_REG_RIGHT_HP_MIXER
843 */
844#define M98090_MIXHPR_MIC2_MASK (1<<5)
845#define M98090_MIXHPR_MIC2_SHIFT 5
846#define M98090_MIXHPR_MIC2_WIDTH 1
847#define M98090_MIXHPR_MIC1_MASK (1<<4)
848#define M98090_MIXHPR_MIC1_SHIFT 4
849#define M98090_MIXHPR_MIC1_WIDTH 1
850#define M98090_MIXHPR_LINEB_MASK (1<<3)
851#define M98090_MIXHPR_LINEB_SHIFT 3
852#define M98090_MIXHPR_LINEB_WIDTH 1
853#define M98090_MIXHPR_LINEA_MASK (1<<2)
854#define M98090_MIXHPR_LINEA_SHIFT 2
855#define M98090_MIXHPR_LINEA_WIDTH 1
856#define M98090_MIXHPR_DACR_MASK (1<<1)
857#define M98090_MIXHPR_DACR_SHIFT 1
858#define M98090_MIXHPR_DACR_WIDTH 1
859#define M98090_MIXHPR_DACL_MASK (1<<0)
860#define M98090_MIXHPR_DACL_SHIFT 0
861#define M98090_MIXHPR_DACL_WIDTH 1
862#define M98090_MIXHPR_MASK (63<<0)
863#define M98090_MIXHPR_SHIFT 0
864#define M98090_MIXHPR_WIDTH 6
865
866/*
867 * M98090_REG_HP_CONTROL
868 */
869#define M98090_MIXHPRSEL_MASK (1<<5)
870#define M98090_MIXHPRSEL_SHIFT 5
871#define M98090_MIXHPRSEL_WIDTH 1
872#define M98090_MIXHPLSEL_MASK (1<<4)
873#define M98090_MIXHPLSEL_SHIFT 4
874#define M98090_MIXHPLSEL_WIDTH 1
875#define M98090_MIXHPRG_MASK (3<<2)
876#define M98090_MIXHPRG_SHIFT 2
877#define M98090_MIXHPRG_WIDTH 2
878#define M98090_MIXHPRG_NUM (1<<M98090_MIXHPRG_WIDTH)
879#define M98090_MIXHPLG_MASK (3<<0)
880#define M98090_MIXHPLG_SHIFT 0
881#define M98090_MIXHPLG_WIDTH 2
882#define M98090_MIXHPLG_NUM (1<<M98090_MIXHPLG_WIDTH)
883
884/*
885 * M98090_REG_LEFT_HP_VOLUME
886 */
887#define M98090_HPLM_MASK (1<<7)
888#define M98090_HPLM_SHIFT 7
889#define M98090_HPLM_WIDTH 1
890#define M98090_HPVOLL_MASK (31<<0)
891#define M98090_HPVOLL_SHIFT 0
892#define M98090_HPVOLL_WIDTH 5
893#define M98090_HPVOLL_NUM (1<<M98090_HPVOLL_WIDTH)
894
895/*
896 * M98090_REG_RIGHT_HP_VOLUME
897 */
898#define M98090_HPRM_MASK (1<<7)
899#define M98090_HPRM_SHIFT 7
900#define M98090_HPRM_WIDTH 1
901#define M98090_HPVOLR_MASK (31<<0)
902#define M98090_HPVOLR_SHIFT 0
903#define M98090_HPVOLR_WIDTH 5
904#define M98090_HPVOLR_NUM (1<<M98090_HPVOLR_WIDTH)
905
906/*
907 * M98090_REG_LEFT_SPK_MIXER
908 */
909#define M98090_MIXSPL_MIC2_MASK (1<<5)
910#define M98090_MIXSPL_MIC2_SHIFT 5
911#define M98090_MIXSPL_MIC2_WIDTH 1
912#define M98090_MIXSPL_MIC1_MASK (1<<4)
913#define M98090_MIXSPL_MIC1_SHIFT 4
914#define M98090_MIXSPL_MIC1_WIDTH 1
915#define M98090_MIXSPL_LINEB_MASK (1<<3)
916#define M98090_MIXSPL_LINEB_SHIFT 3
917#define M98090_MIXSPL_LINEB_WIDTH 1
918#define M98090_MIXSPL_LINEA_MASK (1<<2)
919#define M98090_MIXSPL_LINEA_SHIFT 2
920#define M98090_MIXSPL_LINEA_WIDTH 1
921#define M98090_MIXSPL_DACR_MASK (1<<1)
922#define M98090_MIXSPL_DACR_SHIFT 1
923#define M98090_MIXSPL_DACR_WIDTH 1
924#define M98090_MIXSPL_DACL_MASK (1<<0)
925#define M98090_MIXSPL_DACL_SHIFT 0
926#define M98090_MIXSPL_DACL_WIDTH 1
927#define M98090_MIXSPL_MASK (63<<0)
928#define M98090_MIXSPL_SHIFT 0
929#define M98090_MIXSPL_WIDTH 6
930#define M98090_MIXSPR_DACR_MASK (1<<1)
931#define M98090_MIXSPR_DACR_SHIFT 1
932#define M98090_MIXSPR_DACR_WIDTH 1
933
934
935/*
936 * M98090_REG_RIGHT_SPK_MIXER
937 */
938#define M98090_SPK_SLAVE_MASK (1<<6)
939#define M98090_SPK_SLAVE_SHIFT 6
940#define M98090_SPK_SLAVE_WIDTH 1
941#define M98090_MIXSPR_MIC2_MASK (1<<5)
942#define M98090_MIXSPR_MIC2_SHIFT 5
943#define M98090_MIXSPR_MIC2_WIDTH 1
944#define M98090_MIXSPR_MIC1_MASK (1<<4)
945#define M98090_MIXSPR_MIC1_SHIFT 4
946#define M98090_MIXSPR_MIC1_WIDTH 1
947#define M98090_MIXSPR_LINEB_MASK (1<<3)
948#define M98090_MIXSPR_LINEB_SHIFT 3
949#define M98090_MIXSPR_LINEB_WIDTH 1
950#define M98090_MIXSPR_LINEA_MASK (1<<2)
951#define M98090_MIXSPR_LINEA_SHIFT 2
952#define M98090_MIXSPR_LINEA_WIDTH 1
953#define M98090_MIXSPR_DACR_MASK (1<<1)
954#define M98090_MIXSPR_DACR_SHIFT 1
955#define M98090_MIXSPR_DACR_WIDTH 1
956#define M98090_MIXSPR_DACL_MASK (1<<0)
957#define M98090_MIXSPR_DACL_SHIFT 0
958#define M98090_MIXSPR_DACL_WIDTH 1
959#define M98090_MIXSPR_MASK (63<<0)
960#define M98090_MIXSPR_SHIFT 0
961#define M98090_MIXSPR_WIDTH 6
962
963/*
964 * M98090_REG_SPK_CONTROL
965 */
966#define M98090_MIXSPRG_MASK (3<<2)
967#define M98090_MIXSPRG_SHIFT 2
968#define M98090_MIXSPRG_WIDTH 2
969#define M98090_MIXSPRG_NUM (1<<M98090_MIXSPRG_WIDTH)
970#define M98090_MIXSPLG_MASK (3<<0)
971#define M98090_MIXSPLG_SHIFT 0
972#define M98090_MIXSPLG_WIDTH 2
973#define M98090_MIXSPLG_NUM (1<<M98090_MIXSPLG_WIDTH)
974
975/*
976 * M98090_REG_LEFT_SPK_VOLUME
977 */
978#define M98090_SPLM_MASK (1<<7)
979#define M98090_SPLM_SHIFT 7
980#define M98090_SPLM_WIDTH 1
981#define M98090_SPVOLL_MASK (63<<0)
982#define M98090_SPVOLL_SHIFT 0
983#define M98090_SPVOLL_WIDTH 6
984#define M98090_SPVOLL_NUM 40
985
986/*
987 * M98090_REG_RIGHT_SPK_VOLUME
988 */
989#define M98090_SPRM_MASK (1<<7)
990#define M98090_SPRM_SHIFT 7
991#define M98090_SPRM_WIDTH 1
992#define M98090_SPVOLR_MASK (63<<0)
993#define M98090_SPVOLR_SHIFT 0
994#define M98090_SPVOLR_WIDTH 6
995#define M98090_SPVOLR_NUM 40
996
997/*
998 * M98090_REG_DRC_TIMING
999 */
1000#define M98090_DRCEN_MASK (1<<7)
1001#define M98090_DRCEN_SHIFT 7
1002#define M98090_DRCEN_WIDTH 1
1003#define M98090_DRCEN_NUM (1<<M98090_DRCEN_WIDTH)
1004#define M98090_DRCRLS_MASK (7<<4)
1005#define M98090_DRCRLS_SHIFT 4
1006#define M98090_DRCRLS_WIDTH 3
1007#define M98090_DRCATK_MASK (7<<0)
1008#define M98090_DRCATK_SHIFT 0
1009#define M98090_DRCATK_WIDTH 3
1010
1011/*
1012 * M98090_REG_DRC_COMPRESSOR
1013 */
1014#define M98090_DRCCMP_MASK (7<<5)
1015#define M98090_DRCCMP_SHIFT 5
1016#define M98090_DRCCMP_WIDTH 3
1017#define M98090_DRCTHC_MASK (31<<0)
1018#define M98090_DRCTHC_SHIFT 0
1019#define M98090_DRCTHC_WIDTH 5
1020#define M98090_DRCTHC_NUM (1<<M98090_DRCTHC_WIDTH)
1021
1022/*
1023 * M98090_REG_DRC_EXPANDER
1024 */
1025#define M98090_DRCEXP_MASK (7<<5)
1026#define M98090_DRCEXP_SHIFT 5
1027#define M98090_DRCEXP_WIDTH 3
1028#define M98090_DRCTHE_MASK (31<<0)
1029#define M98090_DRCTHE_SHIFT 0
1030#define M98090_DRCTHE_WIDTH 5
1031#define M98090_DRCTHE_NUM (1<<M98090_DRCTHE_WIDTH)
1032
1033/*
1034 * M98090_REG_DRC_GAIN
1035 */
1036#define M98090_DRCG_MASK (31<<0)
1037#define M98090_DRCG_SHIFT 0
1038#define M98090_DRCG_WIDTH 5
1039#define M98090_DRCG_NUM 13
1040
1041/*
1042 * M98090_REG_RCV_LOUTL_MIXER
1043 */
1044#define M98090_MIXRCVL_MIC2_MASK (1<<5)
1045#define M98090_MIXRCVL_MIC2_SHIFT 5
1046#define M98090_MIXRCVL_MIC2_WIDTH 1
1047#define M98090_MIXRCVL_MIC1_MASK (1<<4)
1048#define M98090_MIXRCVL_MIC1_SHIFT 4
1049#define M98090_MIXRCVL_MIC1_WIDTH 1
1050#define M98090_MIXRCVL_LINEB_MASK (1<<3)
1051#define M98090_MIXRCVL_LINEB_SHIFT 3
1052#define M98090_MIXRCVL_LINEB_WIDTH 1
1053#define M98090_MIXRCVL_LINEA_MASK (1<<2)
1054#define M98090_MIXRCVL_LINEA_SHIFT 2
1055#define M98090_MIXRCVL_LINEA_WIDTH 1
1056#define M98090_MIXRCVL_DACR_MASK (1<<1)
1057#define M98090_MIXRCVL_DACR_SHIFT 1
1058#define M98090_MIXRCVL_DACR_WIDTH 1
1059#define M98090_MIXRCVL_DACL_MASK (1<<0)
1060#define M98090_MIXRCVL_DACL_SHIFT 0
1061#define M98090_MIXRCVL_DACL_WIDTH 1
1062#define M98090_MIXRCVL_MASK (63<<0)
1063#define M98090_MIXRCVL_SHIFT 0
1064#define M98090_MIXRCVL_WIDTH 6
1065
1066/*
1067 * M98090_REG_RCV_LOUTL_CONTROL
1068 */
1069#define M98090_MIXRCVLG_MASK (3<<0)
1070#define M98090_MIXRCVLG_SHIFT 0
1071#define M98090_MIXRCVLG_WIDTH 2
1072#define M98090_MIXRCVLG_NUM (1<<M98090_MIXRCVLG_WIDTH)
1073
1074/*
1075 * M98090_REG_RCV_LOUTL_VOLUME
1076 */
1077#define M98090_RCVLM_MASK (1<<7)
1078#define M98090_RCVLM_SHIFT 7
1079#define M98090_RCVLM_WIDTH 1
1080#define M98090_RCVLVOL_MASK (31<<0)
1081#define M98090_RCVLVOL_SHIFT 0
1082#define M98090_RCVLVOL_WIDTH 5
1083#define M98090_RCVLVOL_NUM (1<<M98090_RCVLVOL_WIDTH)
1084
1085/*
1086 * M98090_REG_LOUTR_MIXER
1087 */
1088#define M98090_LINMOD_MASK (1<<7)
1089#define M98090_LINMOD_SHIFT 7
1090#define M98090_LINMOD_WIDTH 1
1091#define M98090_MIXRCVR_MIC2_MASK (1<<5)
1092#define M98090_MIXRCVR_MIC2_SHIFT 5
1093#define M98090_MIXRCVR_MIC2_WIDTH 1
1094#define M98090_MIXRCVR_MIC1_MASK (1<<4)
1095#define M98090_MIXRCVR_MIC1_SHIFT 4
1096#define M98090_MIXRCVR_MIC1_WIDTH 1
1097#define M98090_MIXRCVR_LINEB_MASK (1<<3)
1098#define M98090_MIXRCVR_LINEB_SHIFT 3
1099#define M98090_MIXRCVR_LINEB_WIDTH 1
1100#define M98090_MIXRCVR_LINEA_MASK (1<<2)
1101#define M98090_MIXRCVR_LINEA_SHIFT 2
1102#define M98090_MIXRCVR_LINEA_WIDTH 1
1103#define M98090_MIXRCVR_DACR_MASK (1<<1)
1104#define M98090_MIXRCVR_DACR_SHIFT 1
1105#define M98090_MIXRCVR_DACR_WIDTH 1
1106#define M98090_MIXRCVR_DACL_MASK (1<<0)
1107#define M98090_MIXRCVR_DACL_SHIFT 0
1108#define M98090_MIXRCVR_DACL_WIDTH 1
1109#define M98090_MIXRCVR_MASK (63<<0)
1110#define M98090_MIXRCVR_SHIFT 0
1111#define M98090_MIXRCVR_WIDTH 6
1112
1113/*
1114 * M98090_REG_LOUTR_CONTROL
1115 */
1116#define M98090_MIXRCVRG_MASK (3<<0)
1117#define M98090_MIXRCVRG_SHIFT 0
1118#define M98090_MIXRCVRG_WIDTH 2
1119#define M98090_MIXRCVRG_NUM (1<<M98090_MIXRCVRG_WIDTH)
1120
1121/*
1122 * M98090_REG_LOUTR_VOLUME
1123 */
1124#define M98090_RCVRM_MASK (1<<7)
1125#define M98090_RCVRM_SHIFT 7
1126#define M98090_RCVRM_WIDTH 1
1127#define M98090_RCVRVOL_MASK (31<<0)
1128#define M98090_RCVRVOL_SHIFT 0
1129#define M98090_RCVRVOL_WIDTH 5
1130#define M98090_RCVRVOL_NUM (1<<M98090_RCVRVOL_WIDTH)
1131
1132/*
1133 * M98090_REG_JACK_DETECT
1134 */
1135#define M98090_JDETEN_MASK (1<<7)
1136#define M98090_JDETEN_SHIFT 7
1137#define M98090_JDETEN_WIDTH 1
1138#define M98090_JDWK_MASK (1<<6)
1139#define M98090_JDWK_SHIFT 6
1140#define M98090_JDWK_WIDTH 1
1141#define M98090_JDEB_MASK (3<<0)
1142#define M98090_JDEB_SHIFT 0
1143#define M98090_JDEB_WIDTH 2
1144#define M98090_JDEB_25MS (0<<0)
1145#define M98090_JDEB_50MS (1<<0)
1146#define M98090_JDEB_100MS (2<<0)
1147#define M98090_JDEB_200MS (3<<0)
1148
1149/*
1150 * M98090_REG_INPUT_ENABLE
1151 */
1152#define M98090_MBEN_MASK (1<<4)
1153#define M98090_MBEN_SHIFT 4
1154#define M98090_MBEN_WIDTH 1
1155#define M98090_LINEAEN_MASK (1<<3)
1156#define M98090_LINEAEN_SHIFT 3
1157#define M98090_LINEAEN_WIDTH 1
1158#define M98090_LINEBEN_MASK (1<<2)
1159#define M98090_LINEBEN_SHIFT 2
1160#define M98090_LINEBEN_WIDTH 1
1161#define M98090_ADREN_MASK (1<<1)
1162#define M98090_ADREN_SHIFT 1
1163#define M98090_ADREN_WIDTH 1
1164#define M98090_ADLEN_MASK (1<<0)
1165#define M98090_ADLEN_SHIFT 0
1166#define M98090_ADLEN_WIDTH 1
1167
1168/*
1169 * M98090_REG_OUTPUT_ENABLE
1170 */
1171#define M98090_HPREN_MASK (1<<7)
1172#define M98090_HPREN_SHIFT 7
1173#define M98090_HPREN_WIDTH 1
1174#define M98090_HPLEN_MASK (1<<6)
1175#define M98090_HPLEN_SHIFT 6
1176#define M98090_HPLEN_WIDTH 1
1177#define M98090_SPREN_MASK (1<<5)
1178#define M98090_SPREN_SHIFT 5
1179#define M98090_SPREN_WIDTH 1
1180#define M98090_SPLEN_MASK (1<<4)
1181#define M98090_SPLEN_SHIFT 4
1182#define M98090_SPLEN_WIDTH 1
1183#define M98090_RCVLEN_MASK (1<<3)
1184#define M98090_RCVLEN_SHIFT 3
1185#define M98090_RCVLEN_WIDTH 1
1186#define M98090_RCVREN_MASK (1<<2)
1187#define M98090_RCVREN_SHIFT 2
1188#define M98090_RCVREN_WIDTH 1
1189#define M98090_DAREN_MASK (1<<1)
1190#define M98090_DAREN_SHIFT 1
1191#define M98090_DAREN_WIDTH 1
1192#define M98090_DALEN_MASK (1<<0)
1193#define M98090_DALEN_SHIFT 0
1194#define M98090_DALEN_WIDTH 1
1195
1196/*
1197 * M98090_REG_LEVEL_CONTROL
1198 */
1199#define M98090_ZDENN_MASK (1<<2)
1200#define M98090_ZDENN_SHIFT 2
1201#define M98090_ZDENN_WIDTH 1
1202#define M98090_ZDENN_NUM (1<<M98090_ZDENN_WIDTH)
1203#define M98090_VS2ENN_MASK (1<<1)
1204#define M98090_VS2ENN_SHIFT 1
1205#define M98090_VS2ENN_WIDTH 1
1206#define M98090_VS2ENN_NUM (1<<M98090_VS2ENN_WIDTH)
1207#define M98090_VSENN_MASK (1<<0)
1208#define M98090_VSENN_SHIFT 0
1209#define M98090_VSENN_WIDTH 1
1210#define M98090_VSENN_NUM (1<<M98090_VSENN_WIDTH)
1211
1212/*
1213 * M98090_REG_DSP_FILTER_ENABLE
1214 */
1215#define M98090_DMIC34BQEN_MASK (1<<4)
1216#define M98090_DMIC34BQEN_SHIFT 4
1217#define M98090_DMIC34BQEN_WIDTH 1
1218#define M98090_DMIC34BQEN_NUM (1<<M98090_DMIC34BQEN_WIDTH)
1219#define M98090_ADCBQEN_MASK (1<<3)
1220#define M98090_ADCBQEN_SHIFT 3
1221#define M98090_ADCBQEN_WIDTH 1
1222#define M98090_ADCBQEN_NUM (1<<M98090_ADCBQEN_WIDTH)
1223#define M98090_EQ3BANDEN_MASK (1<<2)
1224#define M98090_EQ3BANDEN_SHIFT 2
1225#define M98090_EQ3BANDEN_WIDTH 1
1226#define M98090_EQ3BANDEN_NUM (1<<M98090_EQ3BANDEN_WIDTH)
1227#define M98090_EQ5BANDEN_MASK (1<<1)
1228#define M98090_EQ5BANDEN_SHIFT 1
1229#define M98090_EQ5BANDEN_WIDTH 1
1230#define M98090_EQ5BANDEN_NUM (1<<M98090_EQ5BANDEN_WIDTH)
1231#define M98090_EQ7BANDEN_MASK (1<<0)
1232#define M98090_EQ7BANDEN_SHIFT 0
1233#define M98090_EQ7BANDEN_WIDTH 1
1234#define M98090_EQ7BANDEN_NUM (1<<M98090_EQ7BANDEN_WIDTH)
1235
1236/*
1237 * M98090_REG_BIAS_CONTROL
1238 */
1239#define M98090_VCM_MODE_MASK (1<<0)
1240#define M98090_VCM_MODE_SHIFT 0
1241#define M98090_VCM_MODE_WIDTH 1
1242#define M98090_VCM_MODE_NUM (1<<M98090_VCM_MODE_WIDTH)
1243
1244/*
1245 * M98090_REG_DAC_CONTROL
1246 */
1247#define M98090_PERFMODE_MASK (1<<1)
1248#define M98090_PERFMODE_SHIFT 1
1249#define M98090_PERFMODE_WIDTH 1
1250#define M98090_PERFMODE_NUM (1<<M98090_PERFMODE_WIDTH)
1251#define M98090_DACHP_MASK (1<<0)
1252#define M98090_DACHP_SHIFT 0
1253#define M98090_DACHP_WIDTH 1
1254#define M98090_DACHP_NUM (1<<M98090_DACHP_WIDTH)
1255
1256/*
1257 * M98090_REG_ADC_CONTROL
1258 */
1259#define M98090_OSR128_MASK (1<<2)
1260#define M98090_OSR128_SHIFT 2
1261#define M98090_OSR128_WIDTH 1
1262#define M98090_ADCDITHER_MASK (1<<1)
1263#define M98090_ADCDITHER_SHIFT 1
1264#define M98090_ADCDITHER_WIDTH 1
1265#define M98090_ADCDITHER_NUM (1<<M98090_ADCDITHER_WIDTH)
1266#define M98090_ADCHP_MASK (1<<0)
1267#define M98090_ADCHP_SHIFT 0
1268#define M98090_ADCHP_WIDTH 1
1269#define M98090_ADCHP_NUM (1<<M98090_ADCHP_WIDTH)
1270
1271/*
1272 * M98090_REG_DEVICE_SHUTDOWN
1273 */
1274#define M98090_SHDNN_MASK (1<<7)
1275#define M98090_SHDNN_SHIFT 7
1276#define M98090_SHDNN_WIDTH 1
1277
1278/*
1279 * M98090_REG_EQUALIZER_BASE
1280 */
1281#define M98090_B0_1_HI_MASK (255<<0)
1282#define M98090_B0_1_HI_SHIFT 0
1283#define M98090_B0_1_HI_WIDTH 8
1284#define M98090_B0_1_MID_MASK (255<<0)
1285#define M98090_B0_1_MID_SHIFT 0
1286#define M98090_B0_1_MID_WIDTH 8
1287#define M98090_B0_1_LO_MASK (255<<0)
1288#define M98090_B0_1_LO_SHIFT 0
1289#define M98090_B0_1_LO_WIDTH 8
1290#define M98090_B1_1_HI_MASK (255<<0)
1291#define M98090_B1_1_HI_SHIFT 0
1292#define M98090_B1_1_HI_WIDTH 8
1293#define M98090_B1_1_MID_MASK (255<<0)
1294#define M98090_B1_1_MID_SHIFT 0
1295#define M98090_B1_1_MID_WIDTH 8
1296#define M98090_B1_1_LO_MASK (255<<0)
1297#define M98090_B1_1_LO_SHIFT 0
1298#define M98090_B1_1_LO_WIDTH 8
1299#define M98090_B2_1_HI_MASK (255<<0)
1300#define M98090_B2_1_HI_SHIFT 0
1301#define M98090_B2_1_HI_WIDTH 8
1302#define M98090_B2_1_MID_MASK (255<<0)
1303#define M98090_B2_1_MID_SHIFT 0
1304#define M98090_B2_1_MID_WIDTH 8
1305#define M98090_B2_1_LO_MASK (255<<0)
1306#define M98090_B2_1_LO_SHIFT 0
1307#define M98090_B2_1_LO_WIDTH 8
1308#define M98090_A1_1_HI_MASK (255<<0)
1309#define M98090_A1_1_HI_SHIFT 0
1310#define M98090_A1_1_HI_WIDTH 8
1311#define M98090_A1_1_MID_MASK (255<<0)
1312#define M98090_A1_1_MID_SHIFT 0
1313#define M98090_A1_1_MID_WIDTH 8
1314#define M98090_A1_1_LO_MASK (255<<0)
1315#define M98090_A1_1_LO_SHIFT 0
1316#define M98090_A1_1_LO_WIDTH 8
1317#define M98090_A2_1_HI_MASK (255<<0)
1318#define M98090_A2_1_HI_SHIFT 0
1319#define M98090_A2_1_HI_WIDTH 8
1320#define M98090_A2_1_MID_MASK (255<<0)
1321#define M98090_A2_1_MID_SHIFT 0
1322#define M98090_A2_1_MID_WIDTH 8
1323#define M98090_A2_1_LO_MASK (255<<0)
1324#define M98090_A2_1_LO_SHIFT 0
1325#define M98090_A2_1_LO_WIDTH 8
1326
1327#define M98090_COEFS_PER_BAND 5
1328#define M98090_COEFS_BLK_SZ (M98090_COEFS_PER_BAND * 3)
1329#define M98090_COEFS_MAX_SZ (M98090_COEFS_BLK_SZ * 7)
1330
1331/*
1332 * M98090_REG_RECORD_BIQUAD_BASE
1333 */
1334#define M98090_REC_B0_HI_MASK (255<<0)
1335#define M98090_REC_B0_HI_SHIFT 0
1336#define M98090_REC_B0_HI_WIDTH 8
1337#define M98090_REC_B0_MID_MASK (255<<0)
1338#define M98090_REC_B0_MID_SHIFT 0
1339#define M98090_REC_B0_MID_WIDTH 8
1340#define M98090_REC_B0_LO_MASK (255<<0)
1341#define M98090_REC_B0_LO_SHIFT 0
1342#define M98090_REC_B0_LO_WIDTH 8
1343#define M98090_REC_B1_HI_MASK (255<<0)
1344#define M98090_REC_B1_HI_SHIFT 0
1345#define M98090_REC_B1_HI_WIDTH 8
1346#define M98090_REC_B1_MID_MASK (255<<0)
1347#define M98090_REC_B1_MID_SHIFT 0
1348#define M98090_REC_B1_MID_WIDTH 8
1349#define M98090_REC_B1_LO_MASK (255<<0)
1350#define M98090_REC_B1_LO_SHIFT 0
1351#define M98090_REC_B1_LO_WIDTH 8
1352#define M98090_REC_B2_HI_MASK (255<<0)
1353#define M98090_REC_B2_HI_SHIFT 0
1354#define M98090_REC_B2_HI_WIDTH 8
1355#define M98090_REC_B2_MID_MASK (255<<0)
1356#define M98090_REC_B2_MID_SHIFT 0
1357#define M98090_REC_B2_MID_WIDTH 8
1358#define M98090_REC_B2_LO_MASK (255<<0)
1359#define M98090_REC_B2_LO_SHIFT 0
1360#define M98090_REC_B2_LO_WIDTH 8
1361#define M98090_REC_A1_HI_MASK (255<<0)
1362#define M98090_REC_A1_HI_SHIFT 0
1363#define M98090_REC_A1_HI_WIDTH 8
1364#define M98090_REC_A1_MID_MASK (255<<0)
1365#define M98090_REC_A1_MID_SHIFT 0
1366#define M98090_REC_A1_MID_WIDTH 8
1367#define M98090_REC_A1_LO_MASK (255<<0)
1368#define M98090_REC_A1_LO_SHIFT 0
1369#define M98090_REC_A1_LO_WIDTH 8
1370#define M98090_REC_A2_HI_MASK (255<<0)
1371#define M98090_REC_A2_HI_SHIFT 0
1372#define M98090_REC_A2_HI_WIDTH 8
1373#define M98090_REC_A2_MID_MASK (255<<0)
1374#define M98090_REC_A2_MID_SHIFT 0
1375#define M98090_REC_A2_MID_WIDTH 8
1376#define M98090_REC_A2_LO_MASK (255<<0)
1377#define M98090_REC_A2_LO_SHIFT 0
1378#define M98090_REC_A2_LO_WIDTH 8
1379
1380/*
1381 * M98090_REG_DMIC3_VOLUME
1382 */
1383#define M98090_DMIC_AV3G_MASK (7<<4)
1384#define M98090_DMIC_AV3G_SHIFT 4
1385#define M98090_DMIC_AV3G_WIDTH 3
1386#define M98090_DMIC_AV3G_NUM (1<<M98090_DMIC_AV3G_WIDTH)
1387#define M98090_DMIC_AV3_MASK (15<<0)
1388#define M98090_DMIC_AV3_SHIFT 0
1389#define M98090_DMIC_AV3_WIDTH 4
1390#define M98090_DMIC_AV3_NUM (1<<M98090_DMIC_AV3_WIDTH)
1391
1392/*
1393 * M98090_REG_DMIC4_VOLUME
1394 */
1395#define M98090_DMIC_AV4G_MASK (7<<4)
1396#define M98090_DMIC_AV4G_SHIFT 4
1397#define M98090_DMIC_AV4G_WIDTH 3
1398#define M98090_DMIC_AV4G_NUM (1<<M98090_DMIC_AV4G_WIDTH)
1399#define M98090_DMIC_AV4_MASK (15<<0)
1400#define M98090_DMIC_AV4_SHIFT 0
1401#define M98090_DMIC_AV4_WIDTH 4
1402#define M98090_DMIC_AV4_NUM (1<<M98090_DMIC_AV4_WIDTH)
1403
1404/*
1405 * M98090_REG_DMIC34_BQ_PREATTEN
1406 */
1407#define M98090_AV34BQ_MASK (15<<0)
1408#define M98090_AV34BQ_SHIFT 0
1409#define M98090_AV34BQ_WIDTH 4
1410#define M98090_AV34BQ_NUM (1<<M98090_AV34BQ_WIDTH)
1411
1412/*
1413 * M98090_REG_RECORD_TDM_SLOT
1414 */
1415#define M98090_TDM_SLOTADCL_MASK (3<<6)
1416#define M98090_TDM_SLOTADCL_SHIFT 6
1417#define M98090_TDM_SLOTADCL_WIDTH 2
1418#define M98090_TDM_SLOTADCL_NUM (1<<M98090_TDM_SLOTADCL_WIDTH)
1419#define M98090_TDM_SLOTADCR_MASK (3<<4)
1420#define M98090_TDM_SLOTADCR_SHIFT 4
1421#define M98090_TDM_SLOTADCR_WIDTH 2
1422#define M98090_TDM_SLOTADCR_NUM (1<<M98090_TDM_SLOTADCR_WIDTH)
1423#define M98090_TDM_SLOTDMIC3_MASK (3<<2)
1424#define M98090_TDM_SLOTDMIC3_SHIFT 2
1425#define M98090_TDM_SLOTDMIC3_WIDTH 2
1426#define M98090_TDM_SLOTDMIC3_NUM (1<<M98090_TDM_SLOTDMIC3_WIDTH)
1427#define M98090_TDM_SLOTDMIC4_MASK (3<<0)
1428#define M98090_TDM_SLOTDMIC4_SHIFT 0
1429#define M98090_TDM_SLOTDMIC4_WIDTH 2
1430#define M98090_TDM_SLOTDMIC4_NUM (1<<M98090_TDM_SLOTDMIC4_WIDTH)
1431
1432/*
1433 * M98090_REG_SAMPLE_RATE
1434 */
1435#define M98090_DMIC34_ZEROPAD_MASK (1<<4)
1436#define M98090_DMIC34_ZEROPAD_SHIFT 4
1437#define M98090_DMIC34_ZEROPAD_WIDTH 1
1438#define M98090_DMIC34_ZEROPAD_NUM (1<<M98090_DIGMIC4_WIDTH)
1439#define M98090_DMIC34_SRDIV_MASK (7<<0)
1440#define M98090_DMIC34_SRDIV_SHIFT 0
1441#define M98090_DMIC34_SRDIV_WIDTH 3
1442
1443/*
1444 * M98090_REG_DMIC34_BIQUAD_BASE
1445 */
1446#define M98090_DMIC34_B0_HI_MASK (255<<0)
1447#define M98090_DMIC34_B0_HI_SHIFT 0
1448#define M98090_DMIC34_B0_HI_WIDTH 8
1449#define M98090_DMIC34_B0_MID_MASK (255<<0)
1450#define M98090_DMIC34_B0_MID_SHIFT 0
1451#define M98090_DMIC34_B0_MID_WIDTH 8
1452#define M98090_DMIC34_B0_LO_MASK (255<<0)
1453#define M98090_DMIC34_B0_LO_SHIFT 0
1454#define M98090_DMIC34_B0_LO_WIDTH 8
1455#define M98090_DMIC34_B1_HI_MASK (255<<0)
1456#define M98090_DMIC34_B1_HI_SHIFT 0
1457#define M98090_DMIC34_B1_HI_WIDTH 8
1458#define M98090_DMIC34_B1_MID_MASK (255<<0)
1459#define M98090_DMIC34_B1_MID_SHIFT 0
1460#define M98090_DMIC34_B1_MID_WIDTH 8
1461#define M98090_DMIC34_B1_LO_MASK (255<<0)
1462#define M98090_DMIC34_B1_LO_SHIFT 0
1463#define M98090_DMIC34_B1_LO_WIDTH 8
1464#define M98090_DMIC34_B2_HI_MASK (255<<0)
1465#define M98090_DMIC34_B2_HI_SHIFT 0
1466#define M98090_DMIC34_B2_HI_WIDTH 8
1467#define M98090_DMIC34_B2_MID_MASK (255<<0)
1468#define M98090_DMIC34_B2_MID_SHIFT 0
1469#define M98090_DMIC34_B2_MID_WIDTH 8
1470#define M98090_DMIC34_B2_LO_MASK (255<<0)
1471#define M98090_DMIC34_B2_LO_SHIFT 0
1472#define M98090_DMIC34_B2_LO_WIDTH 8
1473#define M98090_DMIC34_A1_HI_MASK (255<<0)
1474#define M98090_DMIC34_A1_HI_SHIFT 0
1475#define M98090_DMIC34_A1_HI_WIDTH 8
1476#define M98090_DMIC34_A1_MID_MASK (255<<0)
1477#define M98090_DMIC34_A1_MID_SHIFT 0
1478#define M98090_DMIC34_A1_MID_WIDTH 8
1479#define M98090_DMIC34_A1_LO_MASK (255<<0)
1480#define M98090_DMIC34_A1_LO_SHIFT 0
1481#define M98090_DMIC34_A1_LO_WIDTH 8
1482#define M98090_DMIC34_A2_HI_MASK (255<<0)
1483#define M98090_DMIC34_A2_HI_SHIFT 0
1484#define M98090_DMIC34_A2_HI_WIDTH 8
1485#define M98090_DMIC34_A2_MID_MASK (255<<0)
1486#define M98090_DMIC34_A2_MID_SHIFT 0
1487#define M98090_DMIC34_A2_MID_WIDTH 8
1488#define M98090_DMIC34_A2_LO_MASK (255<<0)
1489#define M98090_DMIC34_A2_LO_SHIFT 0
1490#define M98090_DMIC34_A2_LO_WIDTH 8
1491
1492#define M98090_JACK_STATE_NO_HEADSET 0
1493#define M98090_JACK_STATE_NO_HEADSET_2 1
1494#define M98090_JACK_STATE_HEADPHONE 2
1495#define M98090_JACK_STATE_HEADSET 3
1496
1497/*
1498 * M98090_REG_REVISION_ID
1499 */
1500#define M98090_REVID_MASK (255<<0)
1501#define M98090_REVID_SHIFT 0
1502#define M98090_REVID_WIDTH 8
1503#define M98090_REVID_NUM (1<<M98090_REVID_WIDTH)
1504
1505#define M98090_BYTE1(w) ((w >> 8) & 0xff)
1506#define M98090_BYTE0(w) (w & 0xff)
1507
1508/* Silicon revision number */
1509#define M98090_REVA 0x40
1510#define M98091_REVA 0x50
1511
1512enum max98090_type {
1513 MAX98090,
1514 MAX98091,
1515};
1516
1517struct max98090_cdata {
1518 unsigned int rate;
1519 unsigned int fmt;
1520};
1521
1522struct max98090_priv {
1523 struct regmap *regmap;
1524 struct snd_soc_codec *codec;
1525 enum max98090_type devtype;
1526 void *control_data;
1527 struct max98090_pdata *pdata;
1528 unsigned int sysclk;
1529 unsigned int bclk;
1530 unsigned int lrclk;
1531 struct max98090_cdata dai[1];
1532 int irq;
1533 int jack_state;
1534 struct delayed_work jack_work;
1535 struct snd_soc_jack *jack;
1536 unsigned int dai_fmt;
1537 int tdm_slots;
1538 int tdm_width;
1539 u8 lin_state;
1540 unsigned int pa1en;
1541 unsigned int pa2en;
1542 unsigned int extmic_mux;
1543 unsigned int sidetone;
1544};
1545
1546int max98090_mic_detect(struct snd_soc_codec *codec,
1547 struct snd_soc_jack *jack);
1548
1549#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 11:29:11 -0400