memory: emif: handle frequency and voltage change events

Change SDRAM timings and other settings as necessary
on voltage and frequency changes. We calculate these
register settings based on data from the device data
sheet and inputs such a frequency, voltage state(stable
or ramping), temperature level etc.

TODO: frequency and voltage change handling needs to
be integrated with clock framework and regulator
framework respectively. This is not done today
due to missing pieces in the kernel.

Signed-off-by: Aneesh V <aneesh@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
[santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc]
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

2 files changed, 1020 insertions, 4 deletions

diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
index 7486d7ef0826..bd116eb8c738 100644
--- a/drivers/memory/emif.c
+++ b/drivers/memory/emif.c
@@ -21,6 +21,7 @@
 #include <linux/seq_file.h>
 #include <linux/module.h>
 #include <linux/list.h>
+#include <linux/spinlock.h>
 #include <memory/jedec_ddr.h>
 #include "emif.h"
 
@@ -37,20 +38,595 @@
  * @node:                       node in the device list
  * @base:                       base address of memory-mapped IO registers.
  * @dev:                        device pointer.
+ * @addressing                  table with addressing information from the spec
+ * @regs_cache:                 An array of 'struct emif_regs' that stores
+ *                              calculated register values for different
+ *                              frequencies, to avoid re-calculating them on
+ *                              each DVFS transition.
+ * @curr_regs:                  The set of register values used in the last
+ *                              frequency change (i.e. corresponding to the
+ *                              frequency in effect at the moment)
  * @plat_data:                  Pointer to saved platform data.
  */
 struct emif_data {
         u8                              duplicate;
         u8                              temperature_level;
+        u8                              lpmode;
         struct list_head                node;
+        unsigned long                   irq_state;
         void __iomem                    *base;
         struct device                   *dev;
+        const struct lpddr2_addressing  *addressing;
+        struct emif_regs                *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
+        struct emif_regs                *curr_regs;
         struct emif_platform_data       *plat_data;
 };
 
 static struct emif_data *emif1;
+static spinlock_t       emif_lock;
+static unsigned long    irq_state;
+static u32              t_ck; /* DDR clock period in ps */
 static LIST_HEAD(device_list);
 
+/*
+ * Calculate the period of DDR clock from frequency value
+ */
+static void set_ddr_clk_period(u32 freq)
+{
+        /* Divide 10^12 by frequency to get period in ps */
+        t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
+}
+
+/*
+ * Get the CL from SDRAM_CONFIG register
+ */
+static u32 get_cl(struct emif_data *emif)
+{
+        u32             cl;
+        void __iomem    *base = emif->base;
+
+        cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
+
+        return cl;
+}
+
+static void set_lpmode(struct emif_data *emif, u8 lpmode)
+{
+        u32 temp;
+        void __iomem *base = emif->base;
+
+        temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
+        temp &= ~LP_MODE_MASK;
+        temp |= (lpmode << LP_MODE_SHIFT);
+        writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
+}
+
+static void do_freq_update(void)
+{
+        struct emif_data *emif;
+
+        /*
+         * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
+         *
+         * i728 DESCRIPTION:
+         * The EMIF automatically puts the SDRAM into self-refresh mode
+         * after the EMIF has not performed accesses during
+         * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
+         * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
+         * to 0x2. If during a small window the following three events
+         * occur:
+         * - The SR_TIMING counter expires
+         * - And frequency change is requested
+         * - And OCP access is requested
+         * Then it causes instable clock on the DDR interface.
+         *
+         * WORKAROUND
+         * To avoid the occurrence of the three events, the workaround
+         * is to disable the self-refresh when requesting a frequency
+         * change. Before requesting a frequency change the software must
+         * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
+         * frequency change has been done, the software can reprogram
+         * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
+         */
+        list_for_each_entry(emif, &device_list, node) {
+                if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+                        set_lpmode(emif, EMIF_LP_MODE_DISABLE);
+        }
+
+        /*
+         * TODO: Do FREQ_UPDATE here when an API
+         * is available for this as part of the new
+         * clock framework
+         */
+
+        list_for_each_entry(emif, &device_list, node) {
+                if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
+                        set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
+        }
+}
+
+/* Find addressing table entry based on the device's type and density */
+static const struct lpddr2_addressing *get_addressing_table(
+        const struct ddr_device_info *device_info)
+{
+        u32             index, type, density;
+
+        type = device_info->type;
+        density = device_info->density;
+
+        switch (type) {
+        case DDR_TYPE_LPDDR2_S4:
+                index = density - 1;
+                break;
+        case DDR_TYPE_LPDDR2_S2:
+                switch (density) {
+                case DDR_DENSITY_1Gb:
+                case DDR_DENSITY_2Gb:
+                        index = density + 3;
+                        break;
+                default:
+                        index = density - 1;
+                }
+                break;
+        default:
+                return NULL;
+        }
+
+        return &lpddr2_jedec_addressing_table[index];
+}
+
+/*
+ * Find the the right timing table from the array of timing
+ * tables of the device using DDR clock frequency
+ */
+static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
+                u32 freq)
+{
+        u32                             i, min, max, freq_nearest;
+        const struct lpddr2_timings     *timings = NULL;
+        const struct lpddr2_timings     *timings_arr = emif->plat_data->timings;
+        struct                          device *dev = emif->dev;
+
+        /* Start with a very high frequency - 1GHz */
+        freq_nearest = 1000000000;
+
+        /*
+         * Find the timings table such that:
+         *  1. the frequency range covers the required frequency(safe) AND
+         *  2. the max_freq is closest to the required frequency(optimal)
+         */
+        for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
+                max = timings_arr[i].max_freq;
+                min = timings_arr[i].min_freq;
+                if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
+                        freq_nearest = max;
+                        timings = &timings_arr[i];
+                }
+        }
+
+        if (!timings)
+                dev_err(dev, "%s: couldn't find timings for - %dHz\n",
+                        __func__, freq);
+
+        dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
+                __func__, freq, freq_nearest);