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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-08-26 04:51:37 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-09-19 17:39:06 -0400
commita93c2aaf18e0e10084c099a0ba2460ab8e3c0e05 (patch)
treead39c099ed903514f6f44cc6695fbdc6270ca4b9
parent9d8907c4e8c97127c562055ac7e1a8ea39ea589c (diff)
ARM: shmobile: r8a7778: add SSI/SRU clock support
Add a platform clock for the r8a7778 SRU/SSI sound. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c43
1 files changed, 41 insertions, 2 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index c4bf2d8fb111..244a8dec4d04 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -69,6 +69,15 @@ static struct clk extal_clk = {
69 .mapping = &cpg_mapping, 69 .mapping = &cpg_mapping,
70}; 70};
71 71
72static struct clk audio_clk_a = {
73};
74
75static struct clk audio_clk_b = {
76};
77
78static struct clk audio_clk_c = {
79};
80
72/* 81/*
73 * clock ratio of these clock will be updated 82 * clock ratio of these clock will be updated
74 * on r8a7778_clock_init() 83 * on r8a7778_clock_init()
@@ -100,18 +109,23 @@ static struct clk *main_clks[] = {
100 &p_clk, 109 &p_clk,
101 &g_clk, 110 &g_clk,
102 &z_clk, 111 &z_clk,
112 &audio_clk_a,
113 &audio_clk_b,
114 &audio_clk_c,
103}; 115};
104 116
105enum { 117enum {
106 MSTP331, 118 MSTP331,
107 MSTP323, MSTP322, MSTP321, 119 MSTP323, MSTP322, MSTP321,
120 MSTP311, MSTP310,
121 MSTP309, MSTP308, MSTP307,
108 MSTP114, 122 MSTP114,
109 MSTP110, MSTP109, 123 MSTP110, MSTP109,
110 MSTP100, 124 MSTP100,
111 MSTP030, 125 MSTP030,
112 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021, 126 MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
113 MSTP016, MSTP015, 127 MSTP016, MSTP015, MSTP012, MSTP011, MSTP010,
114 MSTP007, 128 MSTP009, MSTP008, MSTP007,
115 MSTP_NR }; 129 MSTP_NR };
116 130
117static struct clk mstp_clks[MSTP_NR] = { 131static struct clk mstp_clks[MSTP_NR] = {
@@ -119,6 +133,11 @@ static struct clk mstp_clks[MSTP_NR] = {
119 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ 133 [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
120 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ 134 [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
121 [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */ 135 [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
136 [MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */
137 [MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */
138 [MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */
139 [MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */
140 [MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */
122 [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */ 141 [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
123 [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */ 142 [MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
124 [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */ 143 [MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */
@@ -135,11 +154,20 @@ static struct clk mstp_clks[MSTP_NR] = {
135 [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */ 154 [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
136 [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */ 155 [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
137 [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */ 156 [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
157 [MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */
158 [MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */
159 [MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
160 [MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */
161 [MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */
138 [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */ 162 [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */
139}; 163};
140 164
141static struct clk_lookup lookups[] = { 165static struct clk_lookup lookups[] = {
142 /* main */ 166 /* main */
167 CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
168 CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
169 CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
170 CLKDEV_CON_ID("audio_clk_internal", &s1_clk),
143 CLKDEV_CON_ID("shyway_clk", &s_clk), 171 CLKDEV_CON_ID("shyway_clk", &s_clk),
144 CLKDEV_CON_ID("peripheral_clk", &p_clk), 172 CLKDEV_CON_ID("peripheral_clk", &p_clk),
145 173
@@ -168,6 +196,17 @@ static struct clk_lookup lookups[] = {
168 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ 196 CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
169 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ 197 CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
170 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ 198 CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
199 CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
200
201 CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
202 CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
203 CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
204 CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]),
205 CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]),
206 CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]),
207 CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
208 CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
209 CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
171}; 210};
172 211
173void __init r8a7778_clock_init(void) 212void __init r8a7778_clock_init(void)