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authorBjorn Helgaas <bhelgaas@google.com>2012-12-05 15:51:19 -0500
committerBjorn Helgaas <bhelgaas@google.com>2012-12-07 14:10:50 -0500
commita875621ec15318f0ba35907726ee2cb9e9e0c6b7 (patch)
tree25c8ccf69d97b845bc534b5be498ee0affe429d5
parent438a0f0a1faa3dd00c0460e8232cd712215a6d46 (diff)
ath9k: Use standard #defines for PCIe Capability ASPM fields
Use the standard #defines for PCIe Capability ASPM fields. Previously we used PCIE_LINK_STATE_L0S and PCIE_LINK_STATE_L1 directly, but these are defined for the Linux ASPM interfaces, e.g., pci_disable_link_state(), and only coincidentally match the actual register bits. PCIE_LINK_STATE_CLKPM, also part of that interface, does not match the register bit. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index f088f4bf9a26..71d82078fc7f 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -125,23 +125,23 @@ static void ath_pci_aspm_init(struct ath_common *common)
125 125
126 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && 126 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
127 (AR_SREV_9285(ah))) { 127 (AR_SREV_9285(ah))) {
128 /* Bluetooth coexistance requires disabling ASPM. */ 128 /* Bluetooth coexistence requires disabling ASPM. */
129 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, 129 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
130 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 130 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
131 131
132 /* 132 /*
133 * Both upstream and downstream PCIe components should 133 * Both upstream and downstream PCIe components should
134 * have the same ASPM settings. 134 * have the same ASPM settings.
135 */ 135 */
136 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 136 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
137 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 137 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
138 138
139 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 139 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
140 return; 140 return;
141 } 141 }
142 142
143 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); 143 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
144 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 144 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
145 ah->aspm_enabled = true; 145 ah->aspm_enabled = true;
146 /* Initialize PCIe PM and SERDES registers. */ 146 /* Initialize PCIe PM and SERDES registers. */
147 ath9k_hw_configpcipowersave(ah, false); 147 ath9k_hw_configpcipowersave(ah, false);