drm/i915/bdw: conservative SBE VUE cache mode

Hold vertex data in cache until last reference

BDW-A workaround

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 5 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c0b398572c2a..e1a1bb71896a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4133,6 +4133,8 @@
 /* GEN7 chicken */
 #define GEN7_COMMON_SLICE_CHICKEN1              0x7010
 # define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC      ((1<<10) | (1<<26))
+#define COMMON_SLICE_CHICKEN2                   0x7014
+# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE   (1<<0)
 
 #define GEN7_L3CNTLREG1                         0xB01C
 #define  GEN7_WA_FOR_GEN7_L3_CONTROL                    0x3C4FFF8C
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5dceb56f6ceb..ccd1b88bc24a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5297,6 +5297,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
         I915_WRITE(_3D_CHICKEN3,
                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
 
+        I915_WRITE(COMMON_SLICE_CHICKEN2,
+                   _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
+
         /* WaSwitchSolVfFArbitrationPriority */
         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);