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authorYuval Mintz <yuvalmin@broadcom.com>2013-01-14 00:11:41 -0500
committerDavid S. Miller <davem@davemloft.net>2013-01-15 15:07:58 -0500
commita74801c59ec1e463d93fbb670d16e4f8f4044c7d (patch)
tree2f28502a7d0435d23383a2b691722882b8def988
parent4b87f922598acf91eee18f71688a33f54f57bcde (diff)
bnx2x: Clear dirty status when booting after UNDI
Self-tests following boot from SAN have failed as the UNDI driver might leave some NIG interrupt indications. This patch does the clean-up, clearing those indications and allowing the test to pass. Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Ariel Elior <ariele@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c2
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index f808ed031ee7..6578e410cee0 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -9854,6 +9854,8 @@ static int bnx2x_prev_unload_common(struct bnx2x *bp)
9854 prev_undi = true; 9854 prev_undi = true;
9855 /* clear the UNDI indication */ 9855 /* clear the UNDI indication */
9856 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); 9856 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9857 /* clear possible idle check errors */
9858 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9857 } 9859 }
9858 } 9860 }
9859 /* wait until BRB is empty */ 9861 /* wait until BRB is empty */
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
index a01596561d68..765e2dcadbdb 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -2154,6 +2154,8 @@
2154/* [R 32] Interrupt register #0 read */ 2154/* [R 32] Interrupt register #0 read */
2155#define NIG_REG_NIG_INT_STS_0 0x103b0 2155#define NIG_REG_NIG_INT_STS_0 0x103b0
2156#define NIG_REG_NIG_INT_STS_1 0x103c0 2156#define NIG_REG_NIG_INT_STS_1 0x103c0
2157/* [RC 32] Interrupt register #0 read clear */
2158#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
2157/* [R 32] Legacy E1 and E1H location for parity error mask register. */ 2159/* [R 32] Legacy E1 and E1H location for parity error mask register. */
2158#define NIG_REG_NIG_PRTY_MASK 0x103dc 2160#define NIG_REG_NIG_PRTY_MASK 0x103dc
2159/* [RW 32] Parity mask register #0 read/write */ 2161/* [RW 32] Parity mask register #0 read/write */