diff options
author | Olof Johansson <olof@lixom.net> | 2014-02-20 03:52:24 -0500 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2014-02-20 03:52:39 -0500 |
commit | a671d255afb47bd2f83b94355b2848a0d46a1a92 (patch) | |
tree | deab7c0c89c8f9070a6d3e436d95dbe07d038687 | |
parent | 4a179c1f3784ac3fad626a4a2e67a559bcba3ad3 (diff) | |
parent | cf1e8f0cd665e2a9966d2bee4e11ecc0938ff166 (diff) |
Merge tag 'qcom-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/cleanup
Merge "General cleanups for MSM/QCOM for 3.15" from Kumar Gala:
Split of the multiplatform support for the Qualcomm SoCs into a mach-qcom
while we leave mach-msm as legacy support. Also, some smp and device tree
related cleanups.
* tag 'qcom-cleanup-for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
ARM: qcom: Rename various msm prefixed functions to qcom
clocksource: qcom: split building of legacy vs multiplatform support
ARM: qcom: Split Qualcomm support into legacy and multiplatform
clocksource: qcom: Move clocksource code out of mach-msm
ARM: msm: kill off hotplug.c
ARM: msm: Remove pen_release usage
ARM: dts: msm: split out msm8660 and msm8960 soc into dts include
Signed-off-by: Olof Johansson <olof@lixom.net>
25 files changed, 240 insertions, 370 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index fb08dcececf1..9dbf7f1898c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
@@ -1167,6 +1167,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | |||
1167 | W: http://www.arm.linux.org.uk/ | 1167 | W: http://www.arm.linux.org.uk/ |
1168 | S: Maintained | 1168 | S: Maintained |
1169 | 1169 | ||
1170 | ARM/QUALCOMM SUPPORT | ||
1171 | M: Kumar Gala <galak@codeaurora.org> | ||
1172 | M: David Brown <davidb@codeaurora.org> | ||
1173 | L: linux-arm-msm@vger.kernel.org | ||
1174 | S: Maintained | ||
1175 | F: arch/arm/mach-qcom/ | ||
1176 | T: git git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git | ||
1177 | |||
1170 | ARM/RADISYS ENP2611 MACHINE SUPPORT | 1178 | ARM/RADISYS ENP2611 MACHINE SUPPORT |
1171 | M: Lennert Buytenhek <kernel@wantstofly.org> | 1179 | M: Lennert Buytenhek <kernel@wantstofly.org> |
1172 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) | 1180 | L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) |
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e25419817791..f093f2030c1c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -657,9 +657,8 @@ config ARCH_PXA | |||
657 | help | 657 | help |
658 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | 658 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
659 | 659 | ||
660 | config ARCH_MSM_NODT | 660 | config ARCH_MSM |
661 | bool "Qualcomm MSM" | 661 | bool "Qualcomm MSM (non-multiplatform)" |
662 | select ARCH_MSM | ||
663 | select ARCH_REQUIRE_GPIOLIB | 662 | select ARCH_REQUIRE_GPIOLIB |
664 | select COMMON_CLK | 663 | select COMMON_CLK |
665 | select GENERIC_CLOCKEVENTS | 664 | select GENERIC_CLOCKEVENTS |
@@ -1005,6 +1004,8 @@ source "arch/arm/plat-pxa/Kconfig" | |||
1005 | 1004 | ||
1006 | source "arch/arm/mach-mmp/Kconfig" | 1005 | source "arch/arm/mach-mmp/Kconfig" |
1007 | 1006 | ||
1007 | source "arch/arm/mach-qcom/Kconfig" | ||
1008 | |||
1008 | source "arch/arm/mach-realview/Kconfig" | 1009 | source "arch/arm/mach-realview/Kconfig" |
1009 | 1010 | ||
1010 | source "arch/arm/mach-rockchip/Kconfig" | 1011 | source "arch/arm/mach-rockchip/Kconfig" |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 0531da8e5216..4491c7b05275 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -956,7 +956,7 @@ config DEBUG_STI_UART | |||
956 | 956 | ||
957 | config DEBUG_MSM_UART | 957 | config DEBUG_MSM_UART |
958 | bool | 958 | bool |
959 | depends on ARCH_MSM | 959 | depends on ARCH_MSM || ARCH_QCOM |
960 | 960 | ||
961 | config DEBUG_LL_INCLUDE | 961 | config DEBUG_LL_INCLUDE |
962 | string | 962 | string |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 08a9ef58d9c3..51e5bede657f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 | |||
180 | machine-$(CONFIG_ARCH_ORION5X) += orion5x | 180 | machine-$(CONFIG_ARCH_ORION5X) += orion5x |
181 | machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell | 181 | machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell |
182 | machine-$(CONFIG_ARCH_PXA) += pxa | 182 | machine-$(CONFIG_ARCH_PXA) += pxa |
183 | machine-$(CONFIG_ARCH_QCOM) += qcom | ||
183 | machine-$(CONFIG_ARCH_REALVIEW) += realview | 184 | machine-$(CONFIG_ARCH_REALVIEW) += realview |
184 | machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip | 185 | machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip |
185 | machine-$(CONFIG_ARCH_RPC) += rpc | 186 | machine-$(CONFIG_ARCH_RPC) += rpc |
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6d1e43d46187..3269029a1ce6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
@@ -119,9 +119,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \ | |||
119 | kirkwood-ts219-6282.dtb | 119 | kirkwood-ts219-6282.dtb |
120 | dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb | 120 | dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb |
121 | dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb | 121 | dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb |
122 | dtb-$(CONFIG_ARCH_MSM) += qcom-msm8660-surf.dtb \ | ||
123 | qcom-msm8960-cdp.dtb \ | ||
124 | qcom-apq8074-dragonboard.dtb | ||
125 | dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ | 122 | dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ |
126 | armada-370-mirabox.dtb \ | 123 | armada-370-mirabox.dtb \ |
127 | armada-370-netgear-rn102.dtb \ | 124 | armada-370-netgear-rn102.dtb \ |
@@ -233,6 +230,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ | |||
233 | dra7-evm.dtb | 230 | dra7-evm.dtb |
234 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb | 231 | dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb |
235 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb | 232 | dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb |
233 | dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \ | ||
234 | qcom-msm8960-cdp.dtb \ | ||
235 | qcom-apq8074-dragonboard.dtb | ||
236 | dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ | 236 | dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ |
237 | ste-hrefprev60-stuib.dtb \ | 237 | ste-hrefprev60-stuib.dtb \ |
238 | ste-hrefprev60-tvk.dtb \ | 238 | ste-hrefprev60-tvk.dtb \ |
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 68a72f5507b9..169bad90dac9 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts | |||
@@ -1,63 +1,6 @@ | |||
1 | /dts-v1/; | 1 | #include "qcom-msm8660.dtsi" |
2 | |||
3 | /include/ "skeleton.dtsi" | ||
4 | |||
5 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> | ||
6 | 2 | ||
7 | / { | 3 | / { |
8 | model = "Qualcomm MSM8660 SURF"; | 4 | model = "Qualcomm MSM8660 SURF"; |
9 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; | 5 | compatible = "qcom,msm8660-surf", "qcom,msm8660"; |
10 | interrupt-parent = <&intc>; | ||
11 | |||
12 | intc: interrupt-controller@2080000 { | ||
13 | compatible = "qcom,msm-8660-qgic"; | ||
14 | interrupt-controller; | ||
15 | #interrupt-cells = <3>; | ||
16 | reg = < 0x02080000 0x1000 >, | ||
17 | < 0x02081000 0x1000 >; | ||
18 | }; | ||
19 | |||
20 | timer@2000000 { | ||
21 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | ||
22 | interrupts = <1 0 0x301>, | ||
23 | <1 1 0x301>, | ||
24 | <1 2 0x301>; | ||
25 | reg = <0x02000000 0x100>; | ||
26 | clock-frequency = <27000000>, | ||
27 | <32768>; | ||
28 | cpu-offset = <0x40000>; | ||
29 | }; | ||
30 | |||
31 | msmgpio: gpio@800000 { | ||
32 | compatible = "qcom,msm-gpio"; | ||
33 | reg = <0x00800000 0x4000>; | ||
34 | gpio-controller; | ||
35 | #gpio-cells = <2>; | ||
36 | ngpio = <173>; | ||
37 | interrupts = <0 16 0x4>; | ||
38 | interrupt-controller; | ||
39 | #interrupt-cells = <2>; | ||
40 | }; | ||
41 | |||
42 | gcc: clock-controller@900000 { | ||
43 | compatible = "qcom,gcc-msm8660"; | ||
44 | #clock-cells = <1>; | ||
45 | #reset-cells = <1>; | ||
46 | reg = <0x900000 0x4000>; | ||
47 | }; | ||
48 | |||
49 | serial@19c40000 { | ||
50 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
51 | reg = <0x19c40000 0x1000>, | ||
52 | <0x19c00000 0x1000>; | ||
53 | interrupts = <0 195 0x0>; | ||
54 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | ||
55 | clock-names = "core", "iface"; | ||
56 | }; | ||
57 | |||
58 | qcom,ssbi@500000 { | ||
59 | compatible = "qcom,ssbi"; | ||
60 | reg = <0x500000 0x1000>; | ||
61 | qcom,controller-type = "pmic-arbiter"; | ||
62 | }; | ||
63 | }; | 6 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi new file mode 100644 index 000000000000..69d6c4edea30 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi | |||
@@ -0,0 +1,63 @@ | |||
1 | /dts-v1/; | ||
2 | |||
3 | /include/ "skeleton.dtsi" | ||
4 | |||
5 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> | ||
6 | |||
7 | / { | ||
8 | model = "Qualcomm MSM8660"; | ||
9 | compatible = "qcom,msm8660"; | ||
10 | interrupt-parent = <&intc>; | ||
11 | |||
12 | intc: interrupt-controller@2080000 { | ||
13 | compatible = "qcom,msm-8660-qgic"; | ||
14 | interrupt-controller; | ||
15 | #interrupt-cells = <3>; | ||
16 | reg = < 0x02080000 0x1000 >, | ||
17 | < 0x02081000 0x1000 >; | ||
18 | }; | ||
19 | |||
20 | timer@2000000 { | ||
21 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | ||
22 | interrupts = <1 0 0x301>, | ||
23 | <1 1 0x301>, | ||
24 | <1 2 0x301>; | ||
25 | reg = <0x02000000 0x100>; | ||
26 | clock-frequency = <27000000>, | ||
27 | <32768>; | ||
28 | cpu-offset = <0x40000>; | ||
29 | }; | ||
30 | |||
31 | msmgpio: gpio@800000 { | ||
32 | compatible = "qcom,msm-gpio"; | ||
33 | reg = <0x00800000 0x4000>; | ||
34 | gpio-controller; | ||
35 | #gpio-cells = <2>; | ||
36 | ngpio = <173>; | ||
37 | interrupts = <0 16 0x4>; | ||
38 | interrupt-controller; | ||
39 | #interrupt-cells = <2>; | ||
40 | }; | ||
41 | |||
42 | gcc: clock-controller@900000 { | ||
43 | compatible = "qcom,gcc-msm8660"; | ||
44 | #clock-cells = <1>; | ||
45 | #reset-cells = <1>; | ||
46 | reg = <0x900000 0x4000>; | ||
47 | }; | ||
48 | |||
49 | serial@19c40000 { | ||
50 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
51 | reg = <0x19c40000 0x1000>, | ||
52 | <0x19c00000 0x1000>; | ||
53 | interrupts = <0 195 0x0>; | ||
54 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | ||
55 | clock-names = "core", "iface"; | ||
56 | }; | ||
57 | |||
58 | qcom,ssbi@500000 { | ||
59 | compatible = "qcom,ssbi"; | ||
60 | reg = <0x500000 0x1000>; | ||
61 | qcom,controller-type = "pmic-arbiter"; | ||
62 | }; | ||
63 | }; | ||
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 7c30de4fa302..a58fb88315f6 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts | |||
@@ -1,70 +1,6 @@ | |||
1 | /dts-v1/; | 1 | #include "qcom-msm8960.dtsi" |
2 | |||
3 | /include/ "skeleton.dtsi" | ||
4 | |||
5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | ||
6 | 2 | ||
7 | / { | 3 | / { |
8 | model = "Qualcomm MSM8960 CDP"; | 4 | model = "Qualcomm MSM8960 CDP"; |
9 | compatible = "qcom,msm8960-cdp", "qcom,msm8960"; | 5 | compatible = "qcom,msm8960-cdp", "qcom,msm8960"; |
10 | interrupt-parent = <&intc>; | ||
11 | |||
12 | intc: interrupt-controller@2000000 { | ||
13 | compatible = "qcom,msm-qgic2"; | ||
14 | interrupt-controller; | ||
15 | #interrupt-cells = <3>; | ||
16 | reg = < 0x02000000 0x1000 >, | ||
17 | < 0x02002000 0x1000 >; | ||
18 | }; | ||
19 | |||
20 | timer@200a000 { | ||
21 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | ||
22 | interrupts = <1 1 0x301>, | ||
23 | <1 2 0x301>, | ||
24 | <1 3 0x301>; | ||
25 | reg = <0x0200a000 0x100>; | ||
26 | clock-frequency = <27000000>, | ||
27 | <32768>; | ||
28 | cpu-offset = <0x80000>; | ||
29 | }; | ||
30 | |||
31 | msmgpio: gpio@800000 { | ||
32 | compatible = "qcom,msm-gpio"; | ||
33 | gpio-controller; | ||
34 | #gpio-cells = <2>; | ||
35 | ngpio = <150>; | ||
36 | interrupts = <0 16 0x4>; | ||
37 | interrupt-controller; | ||
38 | #interrupt-cells = <2>; | ||
39 | reg = <0x800000 0x4000>; | ||
40 | }; | ||
41 | |||
42 | gcc: clock-controller@900000 { | ||
43 | compatible = "qcom,gcc-msm8960"; | ||
44 | #clock-cells = <1>; | ||
45 | #reset-cells = <1>; | ||
46 | reg = <0x900000 0x4000>; | ||
47 | }; | ||
48 | |||
49 | clock-controller@4000000 { | ||
50 | compatible = "qcom,mmcc-msm8960"; | ||
51 | reg = <0x4000000 0x1000>; | ||
52 | #clock-cells = <1>; | ||
53 | #reset-cells = <1>; | ||
54 | }; | ||
55 | |||
56 | serial@16440000 { | ||
57 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
58 | reg = <0x16440000 0x1000>, | ||
59 | <0x16400000 0x1000>; | ||
60 | interrupts = <0 154 0x0>; | ||
61 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | ||
62 | clock-names = "core", "iface"; | ||
63 | }; | ||
64 | |||
65 | qcom,ssbi@500000 { | ||
66 | compatible = "qcom,ssbi"; | ||
67 | reg = <0x500000 0x1000>; | ||
68 | qcom,controller-type = "pmic-arbiter"; | ||
69 | }; | ||
70 | }; | 6 | }; |
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi new file mode 100644 index 000000000000..ff002826552a --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi | |||
@@ -0,0 +1,70 @@ | |||
1 | /dts-v1/; | ||
2 | |||
3 | /include/ "skeleton.dtsi" | ||
4 | |||
5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | ||
6 | |||
7 | / { | ||
8 | model = "Qualcomm MSM8960"; | ||
9 | compatible = "qcom,msm8960"; | ||
10 | interrupt-parent = <&intc>; | ||
11 | |||
12 | intc: interrupt-controller@2000000 { | ||
13 | compatible = "qcom,msm-qgic2"; | ||
14 | interrupt-controller; | ||
15 | #interrupt-cells = <3>; | ||
16 | reg = < 0x02000000 0x1000 >, | ||
17 | < 0x02002000 0x1000 >; | ||
18 | }; | ||
19 | |||
20 | timer@200a000 { | ||
21 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | ||
22 | interrupts = <1 1 0x301>, | ||
23 | <1 2 0x301>, | ||
24 | <1 3 0x301>; | ||
25 | reg = <0x0200a000 0x100>; | ||
26 | clock-frequency = <27000000>, | ||
27 | <32768>; | ||
28 | cpu-offset = <0x80000>; | ||
29 | }; | ||
30 | |||
31 | msmgpio: gpio@800000 { | ||
32 | compatible = "qcom,msm-gpio"; | ||
33 | gpio-controller; | ||
34 | #gpio-cells = <2>; | ||
35 | ngpio = <150>; | ||
36 | interrupts = <0 16 0x4>; | ||
37 | interrupt-controller; | ||
38 | #interrupt-cells = <2>; | ||
39 | reg = <0x800000 0x4000>; | ||
40 | }; | ||
41 | |||
42 | gcc: clock-controller@900000 { | ||
43 | compatible = "qcom,gcc-msm8960"; | ||
44 | #clock-cells = <1>; | ||
45 | #reset-cells = <1>; | ||
46 | reg = <0x900000 0x4000>; | ||
47 | }; | ||
48 | |||
49 | clock-controller@4000000 { | ||
50 | compatible = "qcom,mmcc-msm8960"; | ||
51 | reg = <0x4000000 0x1000>; | ||
52 | #clock-cells = <1>; | ||
53 | #reset-cells = <1>; | ||
54 | }; | ||
55 | |||
56 | serial@16440000 { | ||
57 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | ||
58 | reg = <0x16440000 0x1000>, | ||
59 | <0x16400000 0x1000>; | ||
60 | interrupts = <0 154 0x0>; | ||
61 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | ||
62 | clock-names = "core", "iface"; | ||
63 | }; | ||
64 | |||
65 | qcom,ssbi@500000 { | ||
66 | compatible = "qcom,ssbi"; | ||
67 | reg = <0x500000 0x1000>; | ||
68 | qcom,controller-type = "pmic-arbiter"; | ||
69 | }; | ||
70 | }; | ||
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 9625cf378931..a7f959e58c3d 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig | |||
@@ -1,50 +1,9 @@ | |||
1 | config ARCH_MSM | ||
2 | bool | ||
3 | |||
4 | config ARCH_MSM_DT | ||
5 | bool "Qualcomm MSM DT Support" if ARCH_MULTI_V7 | ||
6 | select ARCH_MSM | ||
7 | select ARCH_REQUIRE_GPIOLIB | ||
8 | select CLKSRC_OF | ||
9 | select GENERIC_CLOCKEVENTS | ||
10 | help | ||
11 | Support for Qualcomm's devicetree based MSM systems. | ||
12 | |||
13 | if ARCH_MSM | 1 | if ARCH_MSM |
14 | 2 | ||
15 | menu "Qualcomm MSM SoC Selection" | ||
16 | depends on ARCH_MSM_DT | ||
17 | |||
18 | config ARCH_MSM8X60 | ||
19 | bool "Enable support for MSM8X60" | ||
20 | select ARM_GIC | ||
21 | select CPU_V7 | ||
22 | select HAVE_SMP | ||
23 | select MSM_SCM if SMP | ||
24 | select MSM_TIMER | ||
25 | |||
26 | config ARCH_MSM8960 | ||
27 | bool "Enable support for MSM8960" | ||
28 | select ARM_GIC | ||
29 | select CPU_V7 | ||
30 | select HAVE_SMP | ||
31 | select MSM_SCM if SMP | ||
32 | select MSM_TIMER | ||
33 | |||
34 | config ARCH_MSM8974 | ||
35 | bool "Enable support for MSM8974" | ||
36 | select ARM_GIC | ||
37 | select CPU_V7 | ||
38 | select HAVE_ARM_ARCH_TIMER | ||
39 | select HAVE_SMP | ||
40 | select MSM_SCM if SMP | ||
41 | |||
42 | endmenu | ||
43 | |||
44 | choice | 3 | choice |
45 | prompt "Qualcomm MSM SoC Type" | 4 | prompt "Qualcomm MSM SoC Type" |
46 | default ARCH_MSM7X00A | 5 | default ARCH_MSM7X00A |
47 | depends on ARCH_MSM_NODT | 6 | depends on ARCH_MSM |
48 | 7 | ||
49 | config ARCH_MSM7X00A | 8 | config ARCH_MSM7X00A |
50 | bool "MSM7x00A / MSM7x01A" | 9 | bool "MSM7x00A / MSM7x01A" |
@@ -54,7 +13,7 @@ config ARCH_MSM7X00A | |||
54 | select MACH_TROUT if !MACH_HALIBUT | 13 | select MACH_TROUT if !MACH_HALIBUT |
55 | select MSM_PROC_COMM | 14 | select MSM_PROC_COMM |
56 | select MSM_SMD | 15 | select MSM_SMD |
57 | select MSM_TIMER | 16 | select CLKSRC_QCOM |
58 | select MSM_SMD_PKG3 | 17 | select MSM_SMD_PKG3 |
59 | 18 | ||
60 | config ARCH_MSM7X30 | 19 | config ARCH_MSM7X30 |
@@ -66,7 +25,7 @@ config ARCH_MSM7X30 | |||
66 | select MSM_GPIOMUX | 25 | select MSM_GPIOMUX |
67 | select MSM_PROC_COMM | 26 | select MSM_PROC_COMM |
68 | select MSM_SMD | 27 | select MSM_SMD |
69 | select MSM_TIMER | 28 | select CLKSRC_QCOM |
70 | select MSM_VIC | 29 | select MSM_VIC |
71 | 30 | ||
72 | config ARCH_QSD8X50 | 31 | config ARCH_QSD8X50 |
@@ -78,7 +37,7 @@ config ARCH_QSD8X50 | |||
78 | select MSM_GPIOMUX | 37 | select MSM_GPIOMUX |
79 | select MSM_PROC_COMM | 38 | select MSM_PROC_COMM |
80 | select MSM_SMD | 39 | select MSM_SMD |
81 | select MSM_TIMER | 40 | select CLKSRC_QCOM |
82 | select MSM_VIC | 41 | select MSM_VIC |
83 | 42 | ||
84 | endchoice | 43 | endchoice |
@@ -99,7 +58,7 @@ config MSM_VIC | |||
99 | bool | 58 | bool |
100 | 59 | ||
101 | menu "Qualcomm MSM Board Type" | 60 | menu "Qualcomm MSM Board Type" |
102 | depends on ARCH_MSM_NODT | 61 | depends on ARCH_MSM |
103 | 62 | ||
104 | config MACH_HALIBUT | 63 | config MACH_HALIBUT |
105 | depends on ARCH_MSM | 64 | depends on ARCH_MSM |
@@ -153,7 +112,4 @@ config MSM_GPIOMUX | |||
153 | config MSM_SCM | 112 | config MSM_SCM |
154 | bool | 113 | bool |
155 | 114 | ||
156 | config MSM_TIMER | ||
157 | bool | ||
158 | |||
159 | endif | 115 | endif |
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile index 8e307a10d3c3..27c078a568df 100644 --- a/arch/arm/mach-msm/Makefile +++ b/arch/arm/mach-msm/Makefile | |||
@@ -1,4 +1,3 @@ | |||
1 | obj-$(CONFIG_MSM_TIMER) += timer.o | ||
2 | obj-$(CONFIG_MSM_PROC_COMM) += clock.o | 1 | obj-$(CONFIG_MSM_PROC_COMM) += clock.o |
3 | 2 | ||
4 | obj-$(CONFIG_MSM_VIC) += irq-vic.o | 3 | obj-$(CONFIG_MSM_VIC) += irq-vic.o |
@@ -14,18 +13,11 @@ obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o | |||
14 | 13 | ||
15 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o | 14 | obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o |
16 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o | 15 | obj-$(CONFIG_MSM_SMD) += last_radio_log.o |
17 | obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o | ||
18 | |||
19 | CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) | ||
20 | |||
21 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | ||
22 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o | ||
23 | 16 | ||
24 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o | 17 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o devices-msm7x00.o |
25 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o | 18 | obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o board-trout-panel.o devices-msm7x00.o |
26 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o | 19 | obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o |
27 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o | 20 | obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o |
28 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o | 21 | obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o |
29 | obj-$(CONFIG_ARCH_MSM_DT) += board-dt.o | ||
30 | obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o | 22 | obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o |
31 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o | 23 | obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o |
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h index 33c7725adae2..0a4899b7d85c 100644 --- a/arch/arm/mach-msm/common.h +++ b/arch/arm/mach-msm/common.h | |||
@@ -24,7 +24,6 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, | |||
24 | unsigned int mtype, void *caller); | 24 | unsigned int mtype, void *caller); |
25 | 25 | ||
26 | extern struct smp_operations msm_smp_ops; | 26 | extern struct smp_operations msm_smp_ops; |
27 | extern void msm_cpu_die(unsigned int cpu); | ||
28 | 27 | ||
29 | struct msm_mmc_platform_data; | 28 | struct msm_mmc_platform_data; |
30 | 29 | ||
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S deleted file mode 100644 index 6c62c3f82fe6..000000000000 --- a/arch/arm/mach-msm/headsmp.S +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-realview/headsmp.S | ||
3 | * | ||
4 | * Copyright (c) 2003 ARM Limited | ||
5 | * All Rights Reserved | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | #include <linux/linkage.h> | ||
12 | #include <linux/init.h> | ||
13 | |||
14 | /* | ||
15 | * MSM specific entry point for secondary CPUs. This provides | ||
16 | * a "holding pen" into which all secondary cores are held until we're | ||
17 | * ready for them to initialise. | ||
18 | */ | ||
19 | ENTRY(msm_secondary_startup) | ||
20 | mrc p15, 0, r0, c0, c0, 5 | ||
21 | and r0, r0, #15 | ||
22 | adr r4, 1f | ||
23 | ldmia r4, {r5, r6} | ||
24 | sub r4, r4, r5 | ||
25 | add r6, r6, r4 | ||
26 | pen: ldr r7, [r6] | ||
27 | cmp r7, r0 | ||
28 | bne pen | ||
29 | |||
30 | /* | ||
31 | * we've been released from the holding pen: secondary_stack | ||
32 | * should now contain the SVC stack for this core | ||
33 | */ | ||
34 | b secondary_startup | ||
35 | ENDPROC(msm_secondary_startup) | ||
36 | |||
37 | .align | ||
38 | 1: .long . | ||
39 | .long pen_release | ||
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c deleted file mode 100644 index 326a87261f9a..000000000000 --- a/arch/arm/mach-msm/hotplug.c +++ /dev/null | |||
@@ -1,74 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2002 ARM Ltd. | ||
3 | * All Rights Reserved | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | #include <linux/kernel.h> | ||
10 | #include <linux/errno.h> | ||
11 | #include <linux/smp.h> | ||
12 | |||
13 | #include <asm/smp_plat.h> | ||
14 | |||
15 | #include "common.h" | ||
16 | |||
17 | static inline void cpu_enter_lowpower(void) | ||
18 | { | ||
19 | } | ||
20 | |||
21 | static inline void cpu_leave_lowpower(void) | ||
22 | { | ||
23 | } | ||
24 | |||
25 | static inline void platform_do_lowpower(unsigned int cpu) | ||
26 | { | ||
27 | /* Just enter wfi for now. TODO: Properly shut off the cpu. */ | ||
28 | for (;;) { | ||
29 | /* | ||
30 | * here's the WFI | ||
31 | */ | ||
32 | asm("wfi" | ||
33 | : | ||
34 | : | ||
35 | : "memory", "cc"); | ||
36 | |||
37 | if (pen_release == cpu_logical_map(cpu)) { | ||
38 | /* | ||
39 | * OK, proper wakeup, we're done | ||
40 | */ | ||
41 | break; | ||
42 | } | ||
43 | |||
44 | /* | ||
45 | * getting here, means that we have come out of WFI without | ||
46 | * having been woken up - this shouldn't happen | ||
47 | * | ||
48 | * The trouble is, letting people know about this is not really | ||
49 | * possible, since we are currently running incoherently, and | ||
50 | * therefore cannot safely call printk() or anything else | ||
51 | */ | ||
52 | pr_debug("CPU%u: spurious wakeup call\n", cpu); | ||
53 | } | ||
54 | } | ||
55 | |||
56 | /* | ||
57 | * platform-specific code to shutdown a CPU | ||
58 | * | ||
59 | * Called with IRQs disabled | ||
60 | */ | ||
61 | void __ref msm_cpu_die(unsigned int cpu) | ||
62 | { | ||
63 | /* | ||
64 | * we're ready for shutdown now, so do it | ||
65 | */ | ||
66 | cpu_enter_lowpower(); | ||
67 | platform_do_lowpower(cpu); | ||
68 | |||
69 | /* | ||
70 | * bring this CPU back into the world of cache | ||
71 | * coherency, and then restore interrupts | ||
72 | */ | ||
73 | cpu_leave_lowpower(); | ||
74 | } | ||
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig new file mode 100644 index 000000000000..a028be234334 --- /dev/null +++ b/arch/arm/mach-qcom/Kconfig | |||
@@ -0,0 +1,33 @@ | |||
1 | config ARCH_QCOM | ||
2 | bool "Qualcomm Support" if ARCH_MULTI_V7 | ||
3 | select ARCH_REQUIRE_GPIOLIB | ||
4 | select ARM_GIC | ||
5 | select CLKSRC_OF | ||
6 | select GENERIC_CLOCKEVENTS | ||
7 | select HAVE_SMP | ||
8 | select QCOM_SCM if SMP | ||
9 | help | ||
10 | Support for Qualcomm's devicetree based systems. | ||
11 | |||
12 | if ARCH_QCOM | ||
13 | |||
14 | menu "Qualcomm SoC Selection" | ||
15 | |||
16 | config ARCH_MSM8X60 | ||
17 | bool "Enable support for MSM8X60" | ||
18 | select CLKSRC_QCOM | ||
19 | |||
20 | config ARCH_MSM8960 | ||
21 | bool "Enable support for MSM8960" | ||
22 | select CLKSRC_QCOM | ||
23 | |||
24 | config ARCH_MSM8974 | ||
25 | bool "Enable support for MSM8974" | ||
26 | select HAVE_ARM_ARCH_TIMER | ||
27 | |||
28 | endmenu | ||
29 | |||
30 | config QCOM_SCM | ||
31 | bool | ||
32 | |||
33 | endif | ||
diff --git a/arch/arm/mach-qcom/Makefile b/arch/arm/mach-qcom/Makefile new file mode 100644 index 000000000000..8f756ae1ae31 --- /dev/null +++ b/arch/arm/mach-qcom/Makefile | |||
@@ -0,0 +1,5 @@ | |||
1 | obj-y := board.o | ||
2 | obj-$(CONFIG_SMP) += platsmp.o | ||
3 | obj-$(CONFIG_QCOM_SCM) += scm.o scm-boot.o | ||
4 | |||
5 | CFLAGS_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) | ||
diff --git a/arch/arm/mach-msm/board-dt.c b/arch/arm/mach-qcom/board.c index 1f11d93e700e..830f69c3a3ce 100644 --- a/arch/arm/mach-msm/board-dt.c +++ b/arch/arm/mach-qcom/board.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* Copyright (c) 2010-2012,2013 The Linux Foundation. All rights reserved. | 1 | /* Copyright (c) 2010-2014 The Linux Foundation. All rights reserved. |
2 | * | 2 | * |
3 | * This program is free software; you can redistribute it and/or modify | 3 | * This program is free software; you can redistribute it and/or modify |
4 | * it under the terms of the GNU General Public License version 2 and | 4 | * it under the terms of the GNU General Public License version 2 and |
@@ -17,10 +17,9 @@ | |||
17 | #include <asm/mach/arch.h> | 17 | #include <asm/mach/arch.h> |
18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
19 | 19 | ||
20 | #include "common.h" | 20 | extern struct smp_operations qcom_smp_ops; |
21 | 21 | ||
22 | static const char * const msm_dt_match[] __initconst = { | 22 | static const char * const qcom_dt_match[] __initconst = { |
23 | "qcom,msm8660-fluid", | ||
24 | "qcom,msm8660-surf", | 23 | "qcom,msm8660-surf", |
25 | "qcom,msm8960-cdp", | 24 | "qcom,msm8960-cdp", |
26 | NULL | 25 | NULL |
@@ -31,11 +30,11 @@ static const char * const apq8074_dt_match[] __initconst = { | |||
31 | NULL | 30 | NULL |
32 | }; | 31 | }; |
33 | 32 | ||
34 | DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") | 33 | DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)") |
35 | .smp = smp_ops(msm_smp_ops), | 34 | .smp = smp_ops(qcom_smp_ops), |
36 | .dt_compat = msm_dt_match, | 35 | .dt_compat = qcom_dt_match, |
37 | MACHINE_END | 36 | MACHINE_END |
38 | 37 | ||
39 | DT_MACHINE_START(APQ_DT, "Qualcomm MSM (Flattened Device Tree)") | 38 | DT_MACHINE_START(APQ_DT, "Qualcomm (Flattened Device Tree)") |
40 | .dt_compat = apq8074_dt_match, | 39 | .dt_compat = apq8074_dt_match, |
41 | MACHINE_END | 40 | MACHINE_END |
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-qcom/platsmp.c index f10a1f58fde9..9c53ea70550d 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-qcom/platsmp.c | |||
@@ -2,6 +2,7 @@ | |||
2 | * Copyright (C) 2002 ARM Ltd. | 2 | * Copyright (C) 2002 ARM Ltd. |
3 | * All Rights Reserved | 3 | * All Rights Reserved |
4 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | 4 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. |
5 | * Copyright (c) 2014 The Linux Foundation. All rights reserved. | ||
5 | * | 6 | * |
6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
@@ -12,42 +13,38 @@ | |||
12 | #include <linux/errno.h> | 13 | #include <linux/errno.h> |
13 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
14 | #include <linux/device.h> | 15 | #include <linux/device.h> |
15 | #include <linux/jiffies.h> | ||
16 | #include <linux/smp.h> | 16 | #include <linux/smp.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | 18 | ||
19 | #include <asm/cacheflush.h> | ||
20 | #include <asm/cputype.h> | 19 | #include <asm/cputype.h> |
21 | #include <asm/mach-types.h> | ||
22 | #include <asm/smp_plat.h> | 20 | #include <asm/smp_plat.h> |
23 | 21 | ||
24 | #include "scm-boot.h" | 22 | #include "scm-boot.h" |
25 | #include "common.h" | ||
26 | 23 | ||
27 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 | 24 | #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0 |
28 | #define SCSS_CPU1CORE_RESET 0xD80 | 25 | #define SCSS_CPU1CORE_RESET 0xD80 |
29 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 | 26 | #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64 |
30 | 27 | ||
31 | extern void msm_secondary_startup(void); | 28 | extern void secondary_startup(void); |
32 | 29 | ||
33 | static DEFINE_SPINLOCK(boot_lock); | 30 | static DEFINE_SPINLOCK(boot_lock); |
34 | 31 | ||
32 | #ifdef CONFIG_HOTPLUG_CPU | ||
33 | static void __ref qcom_cpu_die(unsigned int cpu) | ||
34 | { | ||
35 | wfi(); | ||
36 | } | ||
37 | #endif | ||
38 | |||
35 | static inline int get_core_count(void) | 39 | static inline int get_core_count(void) |
36 | { | 40 | { |
37 | /* 1 + the PART[1:0] field of MIDR */ | 41 | /* 1 + the PART[1:0] field of MIDR */ |
38 | return ((read_cpuid_id() >> 4) & 3) + 1; | 42 | return ((read_cpuid_id() >> 4) & 3) + 1; |
39 | } | 43 | } |
40 | 44 | ||
41 | static void msm_secondary_init(unsigned int cpu) | 45 | static void qcom_secondary_init(unsigned int cpu) |
42 | { | 46 | { |
43 | /* | 47 | /* |
44 | * let the primary processor know we're out of the | ||
45 | * pen, then head off into the C entry point | ||
46 | */ | ||
47 | pen_release = -1; | ||
48 | smp_wmb(); | ||
49 | |||
50 | /* | ||
51 | * Synchronise with the boot thread. | 48 | * Synchronise with the boot thread. |
52 | */ | 49 | */ |
53 | spin_lock(&boot_lock); | 50 | spin_lock(&boot_lock); |
@@ -57,7 +54,7 @@ static void msm_secondary_init(unsigned int cpu) | |||
57 | static void prepare_cold_cpu(unsigned int cpu) | 54 | static void prepare_cold_cpu(unsigned int cpu) |
58 | { | 55 | { |
59 | int ret; | 56 | int ret; |
60 | ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup), | 57 | ret = scm_set_boot_addr(virt_to_phys(secondary_startup), |
61 | SCM_FLAG_COLDBOOT_CPU1); | 58 | SCM_FLAG_COLDBOOT_CPU1); |
62 | if (ret == 0) { | 59 | if (ret == 0) { |
63 | void __iomem *sc1_base_ptr; | 60 | void __iomem *sc1_base_ptr; |
@@ -73,9 +70,8 @@ static void prepare_cold_cpu(unsigned int cpu) | |||
73 | "address\n"); | 70 | "address\n"); |
74 | } | 71 | } |
75 | 72 | ||
76 | static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) | 73 | static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle) |
77 | { | 74 | { |
78 | unsigned long timeout; | ||
79 | static int cold_boot_done; | 75 | static int cold_boot_done; |
80 | 76 | ||
81 | /* Only need to bring cpu out of reset this way once */ | 77 | /* Only need to bring cpu out of reset this way once */ |
@@ -91,39 +87,19 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
91 | spin_lock(&boot_lock); | 87 | spin_lock(&boot_lock); |
92 | 88 | ||
93 | /* | 89 | /* |
94 | * The secondary processor is waiting to be released from | ||
95 | * the holding pen - release it, then wait for it to flag | ||
96 | * that it has been released by resetting pen_release. | ||
97 | * | ||
98 | * Note that "pen_release" is the hardware CPU ID, whereas | ||
99 | * "cpu" is Linux's internal ID. | ||
100 | */ | ||
101 | pen_release = cpu_logical_map(cpu); | ||
102 | sync_cache_w(&pen_release); | ||
103 | |||
104 | /* | ||
105 | * Send the secondary CPU a soft interrupt, thereby causing | 90 | * Send the secondary CPU a soft interrupt, thereby causing |
106 | * the boot monitor to read the system wide flags register, | 91 | * the boot monitor to read the system wide flags register, |
107 | * and branch to the address found there. | 92 | * and branch to the address found there. |
108 | */ | 93 | */ |
109 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); | 94 | arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
110 | 95 | ||
111 | timeout = jiffies + (1 * HZ); | ||
112 | while (time_before(jiffies, timeout)) { | ||
113 | smp_rmb(); | ||
114 | if (pen_release == -1) | ||
115 | break; | ||
116 | |||
117 | udelay(10); | ||
118 | } | ||
119 | |||
120 | /* | 96 | /* |
121 | * now the secondary core is starting up let it run its | 97 | * now the secondary core is starting up let it run its |
122 | * calibrations, then wait for it to finish | 98 | * calibrations, then wait for it to finish |
123 | */ | 99 | */ |
124 | spin_unlock(&boot_lock); | 100 | spin_unlock(&boot_lock); |
125 | 101 | ||
126 | return pen_release != -1 ? -ENOSYS : 0; | 102 | return 0; |
127 | } | 103 | } |
128 | 104 | ||
129 | /* | 105 | /* |
@@ -132,7 +108,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
132 | * does not support the ARM SCU, so just set the possible cpu mask to | 108 | * does not support the ARM SCU, so just set the possible cpu mask to |
133 | * NR_CPUS. | 109 | * NR_CPUS. |
134 | */ | 110 | */ |
135 | static void __init msm_smp_init_cpus(void) | 111 | static void __init qcom_smp_init_cpus(void) |
136 | { | 112 | { |
137 | unsigned int i, ncores = get_core_count(); | 113 | unsigned int i, ncores = get_core_count(); |
138 | 114 | ||
@@ -146,16 +122,16 @@ static void __init msm_smp_init_cpus(void) | |||
146 | set_cpu_possible(i, true); | 122 | set_cpu_possible(i, true); |
147 | } | 123 | } |
148 | 124 | ||
149 | static void __init msm_smp_prepare_cpus(unsigned int max_cpus) | 125 | static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) |
150 | { | 126 | { |
151 | } | 127 | } |
152 | 128 | ||
153 | struct smp_operations msm_smp_ops __initdata = { | 129 | struct smp_operations qcom_smp_ops __initdata = { |
154 | .smp_init_cpus = msm_smp_init_cpus, | 130 | .smp_init_cpus = qcom_smp_init_cpus, |
155 | .smp_prepare_cpus = msm_smp_prepare_cpus, | 131 | .smp_prepare_cpus = qcom_smp_prepare_cpus, |
156 | .smp_secondary_init = msm_secondary_init, | 132 | .smp_secondary_init = qcom_secondary_init, |
157 | .smp_boot_secondary = msm_boot_secondary, | 133 | .smp_boot_secondary = qcom_boot_secondary, |
158 | #ifdef CONFIG_HOTPLUG_CPU | 134 | #ifdef CONFIG_HOTPLUG_CPU |
159 | .cpu_die = msm_cpu_die, | 135 | .cpu_die = qcom_cpu_die, |
160 | #endif | 136 | #endif |
161 | }; | 137 | }; |
diff --git a/arch/arm/mach-msm/scm-boot.c b/arch/arm/mach-qcom/scm-boot.c index 45cee3e469a5..45cee3e469a5 100644 --- a/arch/arm/mach-msm/scm-boot.c +++ b/arch/arm/mach-qcom/scm-boot.c | |||
diff --git a/arch/arm/mach-msm/scm-boot.h b/arch/arm/mach-qcom/scm-boot.h index 7be32ff5d687..7be32ff5d687 100644 --- a/arch/arm/mach-msm/scm-boot.h +++ b/arch/arm/mach-qcom/scm-boot.h | |||
diff --git a/arch/arm/mach-msm/scm.c b/arch/arm/mach-qcom/scm.c index c536fd6bf827..c536fd6bf827 100644 --- a/arch/arm/mach-msm/scm.c +++ b/arch/arm/mach-qcom/scm.c | |||
diff --git a/arch/arm/mach-msm/scm.h b/arch/arm/mach-qcom/scm.h index 00b31ea58f29..00b31ea58f29 100644 --- a/arch/arm/mach-msm/scm.h +++ b/arch/arm/mach-qcom/scm.h | |||
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index cd6950fd8caf..6510ec4f45ff 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig | |||
@@ -140,3 +140,6 @@ config VF_PIT_TIMER | |||
140 | bool | 140 | bool |
141 | help | 141 | help |
142 | Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. | 142 | Support for Period Interrupt Timer on Freescale Vybrid Family SoCs. |
143 | |||
144 | config CLKSRC_QCOM | ||
145 | bool | ||
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index c7ca50a9c232..2e0c0cc0a014 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile | |||
@@ -32,6 +32,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o | |||
32 | obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o | 32 | obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o |
33 | obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o | 33 | obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o |
34 | obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o | 34 | obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o |
35 | obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o | ||
35 | 36 | ||
36 | obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o | 37 | obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o |
37 | obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o | 38 | obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o |
diff --git a/arch/arm/mach-msm/timer.c b/drivers/clocksource/qcom-timer.c index fd1644987534..e807acf4c665 100644 --- a/arch/arm/mach-msm/timer.c +++ b/drivers/clocksource/qcom-timer.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * | 2 | * |
3 | * Copyright (C) 2007 Google, Inc. | 3 | * Copyright (C) 2007 Google, Inc. |
4 | * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved. | 4 | * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved. |
5 | * | 5 | * |
6 | * This software is licensed under the terms of the GNU General Public | 6 | * This software is licensed under the terms of the GNU General Public |
7 | * License version 2, as published by the Free Software Foundation, and | 7 | * License version 2, as published by the Free Software Foundation, and |
@@ -26,10 +26,6 @@ | |||
26 | #include <linux/of_irq.h> | 26 | #include <linux/of_irq.h> |
27 | #include <linux/sched_clock.h> | 27 | #include <linux/sched_clock.h> |
28 | 28 | ||
29 | #include <asm/mach/time.h> | ||
30 | |||
31 | #include "common.h" | ||
32 | |||
33 | #define TIMER_MATCH_VAL 0x0000 | 29 | #define TIMER_MATCH_VAL 0x0000 |
34 | #define TIMER_COUNT_VAL 0x0004 | 30 | #define TIMER_COUNT_VAL 0x0004 |
35 | #define TIMER_ENABLE 0x0008 | 31 | #define TIMER_ENABLE 0x0008 |
@@ -110,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs) | |||
110 | return readl_relaxed(source_base + TIMER_COUNT_VAL); | 106 | return readl_relaxed(source_base + TIMER_COUNT_VAL); |
111 | } | 107 | } |
112 | 108 | ||
113 | static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs) | ||
114 | { | ||
115 | /* | ||
116 | * Shift timer count down by a constant due to unreliable lower bits | ||
117 | * on some targets. | ||
118 | */ | ||
119 | return msm_read_timer_count(cs) >> MSM_DGT_SHIFT; | ||
120 | } | ||
121 | |||
122 | static struct clocksource msm_clocksource = { | 109 | static struct clocksource msm_clocksource = { |
123 | .name = "dg_timer", | 110 | .name = "dg_timer", |
124 | .rating = 300, | 111 | .rating = 300, |
@@ -232,7 +219,7 @@ err: | |||
232 | sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); | 219 | sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); |
233 | } | 220 | } |
234 | 221 | ||
235 | #ifdef CONFIG_OF | 222 | #ifdef CONFIG_ARCH_QCOM |
236 | static void __init msm_dt_timer_init(struct device_node *np) | 223 | static void __init msm_dt_timer_init(struct device_node *np) |
237 | { | 224 | { |
238 | u32 freq; | 225 | u32 freq; |
@@ -285,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np) | |||
285 | } | 272 | } |
286 | CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); | 273 | CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); |
287 | CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); | 274 | CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); |
288 | #endif | 275 | #else |
289 | 276 | ||
290 | static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, | 277 | static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, |
291 | u32 sts) | 278 | u32 sts) |
@@ -305,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, | |||
305 | return 0; | 292 | return 0; |
306 | } | 293 | } |
307 | 294 | ||
295 | static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs) | ||
296 | { | ||
297 | /* | ||
298 | * Shift timer count down by a constant due to unreliable lower bits | ||
299 | * on some targets. | ||
300 | */ | ||
301 | return msm_read_timer_count(cs) >> MSM_DGT_SHIFT; | ||
302 | } | ||
303 | |||
308 | void __init msm7x01_timer_init(void) | 304 | void __init msm7x01_timer_init(void) |
309 | { | 305 | { |
310 | struct clocksource *cs = &msm_clocksource; | 306 | struct clocksource *cs = &msm_clocksource; |
@@ -331,3 +327,4 @@ void __init qsd8x50_timer_init(void) | |||
331 | return; | 327 | return; |
332 | msm_timer_init(19200000 / 4, 32, 7, false); | 328 | msm_timer_init(19200000 / 4, 32, 7, false); |
333 | } | 329 | } |
330 | #endif | ||