aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorOndrej Zary <linux@rainbow-software.org>2014-11-11 11:54:55 -0500
committerUlf Hansson <ulf.hansson@linaro.org>2014-11-26 08:30:58 -0500
commita5eb8bbd66ccf9f169419f9652544aec771b7c57 (patch)
tree1115b188a5317df46254c7c08d47a263ccb86808
parent89ad2be75a4287126f9f5473ecf167bd9b91093d (diff)
mmc: add Toshiba PCI SD controller driver
This patch resurrects an old never-finished driver for Toshiba PCI SD controllers found in some older Toshiba laptops (such as Portege R100): 02:0d.0 System peripheral [0880]: Toshiba America Info Systems SD TypA Controller [1179:0805] (rev 05) The code is fixed, cleaned up and successfully tested with SD, SDHC, SDXC and MMC cards on Portege R100. (MMC cards don't even work in Windows!) SDIO probably does not work (don't have any SDIO card). The hardware is slow (around 2 MB/s - same in Windows) because it does not support bus mastering (busmaster enable bit cannot be set in PCI control reg). Also the card clock is limited to 16MHz (33MHz PCI clock divided by 2). Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat
-rw-r--r--drivers/mmc/host/Kconfig5
-rw-r--r--drivers/mmc/host/Makefile1
-rw-r--r--drivers/mmc/host/toshsd.c717
-rw-r--r--drivers/mmc/host/toshsd.h176
4 files changed, 899 insertions, 0 deletions
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 13860656104b..882bfe53fa38 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -748,3 +748,8 @@ config MMC_SUNXI
748 help 748 help
749 This selects support for the SD/MMC Host Controller on 749 This selects support for the SD/MMC Host Controller on
750 Allwinner sunxi SoCs. 750 Allwinner sunxi SoCs.
751
752config MMC_TOSHIBA_PCI
753 tristate "Toshiba Type A SD/MMC Card Interface Driver"
754 depends on PCI
755 help
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index b09ecfb88269..f7b0a77cf419 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -55,6 +55,7 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
55obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o 55obj-$(CONFIG_MMC_MOXART) += moxart-mmc.o
56obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o 56obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
57obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o 57obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o
58obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o
58 59
59obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o 60obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
60obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o 61obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
diff --git a/drivers/mmc/host/toshsd.c b/drivers/mmc/host/toshsd.c
new file mode 100644
index 000000000000..edb06d67c2f5
--- /dev/null
+++ b/drivers/mmc/host/toshsd.c
@@ -0,0 +1,717 @@
1/*
2 * Toshiba PCI Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2014 Ondrej Zary
5 * Copyright (C) 2007 Richard Betts, All Rights Reserved.
6 *
7 * Based on asic3_mmc.c, copyright (c) 2005 SDG Systems, LLC and,
8 * sdhci.c, copyright (C) 2005-2006 Pierre Ossman
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 */
15
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/module.h>
19#include <linux/pci.h>
20#include <linux/scatterlist.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/pm.h>
24#include <linux/mmc/host.h>
25#include <linux/mmc/mmc.h>
26
27#include "toshsd.h"
28
29#define DRIVER_NAME "toshsd"
30
31static const struct pci_device_id pci_ids[] = {
32 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA, 0x0805) },
33 { /* end: all zeroes */ },
34};
35
36MODULE_DEVICE_TABLE(pci, pci_ids);
37
38static void toshsd_init(struct toshsd_host *host)
39{
40 /* enable clock */
41 pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP,
42 SD_PCICFG_CLKSTOP_ENABLE_ALL);
43 pci_write_config_byte(host->pdev, SD_PCICFG_CARDDETECT, 2);
44
45 /* reset */
46 iowrite16(0, host->ioaddr + SD_SOFTWARERESET); /* assert */
47 mdelay(2);
48 iowrite16(1, host->ioaddr + SD_SOFTWARERESET); /* deassert */
49 mdelay(2);
50
51 /* Clear card registers */
52 iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
53 iowrite32(0, host->ioaddr + SD_CARDSTATUS);
54 iowrite32(0, host->ioaddr + SD_ERRORSTATUS0);
55 iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
56
57 /* SDIO clock? */
58 iowrite16(0x100, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
59
60 /* enable LED */
61 pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE1,
62 SD_PCICFG_LED_ENABLE1_START);
63 pci_write_config_byte(host->pdev, SD_PCICFG_SDLED_ENABLE2,
64 SD_PCICFG_LED_ENABLE2_START);
65
66 /* set interrupt masks */
67 iowrite32(~(u32)(SD_CARD_RESP_END | SD_CARD_RW_END
68 | SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0
69 | SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE
70 | SD_BUF_CMD_TIMEOUT),
71 host->ioaddr + SD_INTMASKCARD);
72
73 iowrite16(0x1000, host->ioaddr + SD_TRANSACTIONCTRL);
74}
75
76/* Set MMC clock / power.
77 * Note: This controller uses a simple divider scheme therefore it cannot run
78 * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
79 * and the next slowest is 16MHz (div=2).
80 */
81static void __toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
82{
83 struct toshsd_host *host = mmc_priv(mmc);
84
85 if (ios->clock) {
86 u16 clk;
87 int div = 1;
88
89 while (ios->clock < HCLK / div)
90 div *= 2;
91
92 clk = div >> 2;
93
94 if (div == 1) { /* disable the divider */
95 pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE,
96 SD_PCICFG_CLKMODE_DIV_DISABLE);
97 clk |= SD_CARDCLK_DIV_DISABLE;
98 } else
99 pci_write_config_byte(host->pdev, SD_PCICFG_CLKMODE, 0);
100
101 clk |= SD_CARDCLK_ENABLE_CLOCK;
102 iowrite16(clk, host->ioaddr + SD_CARDCLOCKCTRL);
103
104 mdelay(10);
105 } else
106 iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
107
108 switch (ios->power_mode) {
109 case MMC_POWER_OFF:
110 pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
111 SD_PCICFG_PWR1_OFF);
112 mdelay(1);
113 break;
114 case MMC_POWER_UP:
115 break;
116 case MMC_POWER_ON:
117 pci_write_config_byte(host->pdev, SD_PCICFG_POWER1,
118 SD_PCICFG_PWR1_33V);
119 pci_write_config_byte(host->pdev, SD_PCICFG_POWER2,
120 SD_PCICFG_PWR2_AUTO);
121 mdelay(20);
122 break;
123 }
124
125 switch (ios->bus_width) {
126 case MMC_BUS_WIDTH_1:
127 iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
128 | SD_CARDOPT_C2_MODULE_ABSENT
129 | SD_CARDOPT_DATA_XFR_WIDTH_1,
130 host->ioaddr + SD_CARDOPTIONSETUP);
131 break;
132 case MMC_BUS_WIDTH_4:
133 iowrite16(SD_CARDOPT_REQUIRED | SD_CARDOPT_DATA_RESP_TIMEOUT(14)
134 | SD_CARDOPT_C2_MODULE_ABSENT
135 | SD_CARDOPT_DATA_XFR_WIDTH_4,
136 host->ioaddr + SD_CARDOPTIONSETUP);
137 break;
138 }
139}
140
141static void toshsd_set_led(struct toshsd_host *host, unsigned char state)
142{
143 iowrite16(state, host->ioaddr + SDIO_BASE + SDIO_LEDCTRL);
144}
145
146static void toshsd_finish_request(struct toshsd_host *host)
147{
148 struct mmc_request *mrq = host->mrq;
149
150 /* Write something to end the command */
151 host->mrq = NULL;
152 host->cmd = NULL;
153 host->data = NULL;
154
155 toshsd_set_led(host, 0);
156 mmc_request_done(host->mmc, mrq);
157}
158
159static irqreturn_t toshsd_thread_irq(int irq, void *dev_id)
160{
161 struct toshsd_host *host = dev_id;
162 struct mmc_data *data = host->data;
163 struct sg_mapping_iter *sg_miter = &host->sg_miter;
164 unsigned short *buf;
165 int count;
166 unsigned long flags;
167
168 if (!data) {
169 dev_warn(&host->pdev->dev, "Spurious Data IRQ\n");
170 if (host->cmd) {
171 host->cmd->error = -EIO;
172 toshsd_finish_request(host);
173 }
174 return IRQ_NONE;
175 }
176 spin_lock_irqsave(&host->lock, flags);
177
178 if (!sg_miter_next(sg_miter))
179 return IRQ_HANDLED;
180 buf = sg_miter->addr;
181
182 /* Ensure we dont read more than one block. The chip will interrupt us
183 * When the next block is available.
184 */
185 count = sg_miter->length;
186 if (count > data->blksz)
187 count = data->blksz;
188
189 dev_dbg(&host->pdev->dev, "count: %08x, flags %08x\n", count,
190 data->flags);
191
192 /* Transfer the data */
193 if (data->flags & MMC_DATA_READ)
194 ioread32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
195 else
196 iowrite32_rep(host->ioaddr + SD_DATAPORT, buf, count >> 2);
197
198 sg_miter->consumed = count;
199 sg_miter_stop(sg_miter);
200
201 spin_unlock_irqrestore(&host->lock, flags);
202
203 return IRQ_HANDLED;
204}
205
206static void toshsd_cmd_irq(struct toshsd_host *host)
207{
208 struct mmc_command *cmd = host->cmd;
209 u8 *buf = (u8 *) cmd->resp;
210 u16 data;
211
212 if (!host->cmd) {
213 dev_warn(&host->pdev->dev, "Spurious CMD irq\n");
214 return;
215 }
216
217 host->cmd = NULL;
218
219 if (cmd->flags & MMC_RSP_PRESENT && cmd->flags & MMC_RSP_136) {
220 /* R2 */
221 buf[12] = 0xff;
222 data = ioread16(host->ioaddr + SD_RESPONSE0);
223 buf[13] = data & 0xff;
224 buf[14] = data >> 8;
225 data = ioread16(host->ioaddr + SD_RESPONSE1);
226 buf[15] = data & 0xff;
227 buf[8] = data >> 8;
228 data = ioread16(host->ioaddr + SD_RESPONSE2);
229 buf[9] = data & 0xff;
230 buf[10] = data >> 8;
231 data = ioread16(host->ioaddr + SD_RESPONSE3);
232 buf[11] = data & 0xff;
233 buf[4] = data >> 8;
234 data = ioread16(host->ioaddr + SD_RESPONSE4);
235 buf[5] = data & 0xff;
236 buf[6] = data >> 8;
237 data = ioread16(host->ioaddr + SD_RESPONSE5);
238 buf[7] = data & 0xff;
239 buf[0] = data >> 8;
240 data = ioread16(host->ioaddr + SD_RESPONSE6);
241 buf[1] = data & 0xff;
242 buf[2] = data >> 8;
243 data = ioread16(host->ioaddr + SD_RESPONSE7);
244 buf[3] = data & 0xff;
245 } else if (cmd->flags & MMC_RSP_PRESENT) {
246 /* R1, R1B, R3, R6, R7 */
247 data = ioread16(host->ioaddr + SD_RESPONSE0);
248 buf[0] = data & 0xff;
249 buf[1] = data >> 8;
250 data = ioread16(host->ioaddr + SD_RESPONSE1);
251 buf[2] = data & 0xff;
252 buf[3] = data >> 8;
253 }
254
255 dev_dbg(&host->pdev->dev, "Command IRQ complete %d %d %x\n",
256 cmd->opcode, cmd->error, cmd->flags);
257
258 /* If there is data to handle we will
259 * finish the request in the mmc_data_end_irq handler.*/
260 if (host->data)
261 return;
262
263 toshsd_finish_request(host);
264}
265
266static void toshsd_data_end_irq(struct toshsd_host *host)
267{
268 struct mmc_data *data = host->data;
269
270 host->data = NULL;
271
272 if (!data) {
273 dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
274 return;
275 }
276
277 if (data->error == 0)
278 data->bytes_xfered = data->blocks * data->blksz;
279 else
280 data->bytes_xfered = 0;
281
282 dev_dbg(&host->pdev->dev, "Completed data request xfr=%d\n",
283 data->bytes_xfered);
284
285 iowrite16(0, host->ioaddr + SD_STOPINTERNAL);
286
287 toshsd_finish_request(host);
288}
289
290static irqreturn_t toshsd_irq(int irq, void *dev_id)
291{
292 struct toshsd_host *host = dev_id;
293 u32 int_reg, int_mask, int_status, detail;
294 int error = 0, ret = IRQ_HANDLED;
295
296 spin_lock(&host->lock);
297 int_status = ioread32(host->ioaddr + SD_CARDSTATUS);
298 int_mask = ioread32(host->ioaddr + SD_INTMASKCARD);
299 int_reg = int_status & ~int_mask & ~IRQ_DONT_CARE_BITS;
300
301 dev_dbg(&host->pdev->dev, "IRQ status:%x mask:%x\n",
302 int_status, int_mask);
303
304 /* nothing to do: it's not our IRQ */
305 if (!int_reg) {
306 ret = IRQ_NONE;
307 goto irq_end;
308 }
309
310 if (int_reg & SD_BUF_CMD_TIMEOUT) {
311 error = -ETIMEDOUT;
312 dev_dbg(&host->pdev->dev, "Timeout\n");
313 } else if (int_reg & SD_BUF_CRC_ERR) {
314 error = -EILSEQ;
315 dev_err(&host->pdev->dev, "BadCRC\n");
316 } else if (int_reg & (SD_BUF_ILLEGAL_ACCESS
317 | SD_BUF_CMD_INDEX_ERR
318 | SD_BUF_STOP_BIT_END_ERR
319 | SD_BUF_OVERFLOW
320 | SD_BUF_UNDERFLOW
321 | SD_BUF_DATA_TIMEOUT)) {
322 dev_err(&host->pdev->dev, "Buffer status error: { %s%s%s%s%s%s}\n",
323 int_reg & SD_BUF_ILLEGAL_ACCESS ? "ILLEGAL_ACC " : "",
324 int_reg & SD_BUF_CMD_INDEX_ERR ? "CMD_INDEX " : "",
325 int_reg & SD_BUF_STOP_BIT_END_ERR ? "STOPBIT_END " : "",
326 int_reg & SD_BUF_OVERFLOW ? "OVERFLOW " : "",
327 int_reg & SD_BUF_UNDERFLOW ? "UNDERFLOW " : "",
328 int_reg & SD_BUF_DATA_TIMEOUT ? "DATA_TIMEOUT " : "");
329
330 detail = ioread32(host->ioaddr + SD_ERRORSTATUS0);
331 dev_err(&host->pdev->dev, "detail error status { %s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
332 detail & SD_ERR0_RESP_CMD_ERR ? "RESP_CMD " : "",
333 detail & SD_ERR0_RESP_NON_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
334 detail & SD_ERR0_RESP_CMD12_END_BIT_ERR ? "RESP_END_BIT " : "",
335 detail & SD_ERR0_READ_DATA_END_BIT_ERR ? "READ_DATA_END_BIT " : "",
336 detail & SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR ? "WRITE_CMD_END_BIT " : "",
337 detail & SD_ERR0_RESP_NON_CMD12_CRC_ERR ? "RESP_CRC " : "",
338 detail & SD_ERR0_RESP_CMD12_CRC_ERR ? "RESP_CRC " : "",
339 detail & SD_ERR0_READ_DATA_CRC_ERR ? "READ_DATA_CRC " : "",
340 detail & SD_ERR0_WRITE_CMD_CRC_ERR ? "WRITE_CMD_CRC " : "",
341 detail & SD_ERR1_NO_CMD_RESP ? "NO_CMD_RESP " : "",
342 detail & SD_ERR1_TIMEOUT_READ_DATA ? "READ_DATA_TIMEOUT " : "",
343 detail & SD_ERR1_TIMEOUT_CRS_STATUS ? "CRS_STATUS_TIMEOUT " : "",
344 detail & SD_ERR1_TIMEOUT_CRC_BUSY ? "CRC_BUSY_TIMEOUT " : "");
345 error = -EIO;
346 }
347
348 if (error) {
349 if (host->cmd)
350 host->cmd->error = error;
351
352 if (error == -ETIMEDOUT) {
353 iowrite32(int_status &
354 ~(SD_BUF_CMD_TIMEOUT | SD_CARD_RESP_END),
355 host->ioaddr + SD_CARDSTATUS);
356 } else {
357 toshsd_init(host);
358 __toshsd_set_ios(host->mmc, &host->mmc->ios);
359 goto irq_end;
360 }
361 }
362
363 /* Card insert/remove. The mmc controlling code is stateless. */
364 if (int_reg & (SD_CARD_CARD_INSERTED_0 | SD_CARD_CARD_REMOVED_0)) {
365 iowrite32(int_status &
366 ~(SD_CARD_CARD_REMOVED_0 | SD_CARD_CARD_INSERTED_0),
367 host->ioaddr + SD_CARDSTATUS);
368
369 if (int_reg & SD_CARD_CARD_INSERTED_0)
370 toshsd_init(host);
371
372 mmc_detect_change(host->mmc, 1);
373 }
374
375 /* Data transfer */
376 if (int_reg & (SD_BUF_READ_ENABLE | SD_BUF_WRITE_ENABLE)) {
377 iowrite32(int_status &
378 ~(SD_BUF_WRITE_ENABLE | SD_BUF_READ_ENABLE),
379 host->ioaddr + SD_CARDSTATUS);
380
381 ret = IRQ_WAKE_THREAD;
382 goto irq_end;
383 }
384
385 /* Command completion */
386 if (int_reg & SD_CARD_RESP_END) {
387 iowrite32(int_status & ~(SD_CARD_RESP_END),
388 host->ioaddr + SD_CARDSTATUS);
389 toshsd_cmd_irq(host);
390 }
391
392 /* Data transfer completion */
393 if (int_reg & SD_CARD_RW_END) {
394 iowrite32(int_status & ~(SD_CARD_RW_END),
395 host->ioaddr + SD_CARDSTATUS);
396 toshsd_data_end_irq(host);
397 }
398irq_end:
399 spin_unlock(&host->lock);
400 return ret;
401}
402
403static void toshsd_start_cmd(struct toshsd_host *host, struct mmc_command *cmd)
404{
405 struct mmc_data *data = host->data;
406 int c = cmd->opcode;
407
408 dev_dbg(&host->pdev->dev, "Command opcode: %d\n", cmd->opcode);
409
410 if (cmd->opcode == MMC_STOP_TRANSMISSION) {
411 iowrite16(SD_STOPINT_ISSUE_CMD12,
412 host->ioaddr + SD_STOPINTERNAL);
413
414 cmd->resp[0] = cmd->opcode;
415 cmd->resp[1] = 0;
416 cmd->resp[2] = 0;
417 cmd->resp[3] = 0;
418
419 toshsd_finish_request(host);
420 return;
421 }
422
423 switch (mmc_resp_type(cmd)) {
424 case MMC_RSP_NONE:
425 c |= SD_CMD_RESP_TYPE_NONE;
426 break;
427
428 case MMC_RSP_R1:
429 c |= SD_CMD_RESP_TYPE_EXT_R1;
430 break;
431 case MMC_RSP_R1B:
432 c |= SD_CMD_RESP_TYPE_EXT_R1B;
433 break;
434 case MMC_RSP_R2:
435 c |= SD_CMD_RESP_TYPE_EXT_R2;
436 break;
437 case MMC_RSP_R3:
438 c |= SD_CMD_RESP_TYPE_EXT_R3;
439 break;
440
441 default:
442 dev_err(&host->pdev->dev, "Unknown response type %d\n",
443 mmc_resp_type(cmd));
444 break;
445 }
446
447 host->cmd = cmd;
448
449 if (cmd->opcode == MMC_APP_CMD)
450 c |= SD_CMD_TYPE_ACMD;
451
452 if (cmd->opcode == MMC_GO_IDLE_STATE)
453 c |= (3 << 8); /* removed from ipaq-asic3.h for some reason */
454
455 if (data) {
456 c |= SD_CMD_DATA_PRESENT;
457
458 if (data->blocks > 1) {
459 iowrite16(SD_STOPINT_AUTO_ISSUE_CMD12,
460 host->ioaddr + SD_STOPINTERNAL);
461 c |= SD_CMD_MULTI_BLOCK;
462 }
463
464 if (data->flags & MMC_DATA_READ)
465 c |= SD_CMD_TRANSFER_READ;
466
467 /* MMC_DATA_WRITE does not require a bit to be set */
468 }
469
470 /* Send the command */
471 iowrite32(cmd->arg, host->ioaddr + SD_ARG0);
472 iowrite16(c, host->ioaddr + SD_CMD);
473}
474
475static void toshsd_start_data(struct toshsd_host *host, struct mmc_data *data)
476{
477 unsigned int flags = SG_MITER_ATOMIC;
478
479 dev_dbg(&host->pdev->dev, "setup data transfer: blocksize %08x nr_blocks %d, offset: %08x\n",
480 data->blksz, data->blocks, data->sg->offset);
481
482 host->data = data;
483
484 if (data->flags & MMC_DATA_READ)
485 flags |= SG_MITER_TO_SG;
486 else
487 flags |= SG_MITER_FROM_SG;
488
489 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
490
491 /* Set transfer length and blocksize */
492 iowrite16(data->blocks, host->ioaddr + SD_BLOCKCOUNT);
493 iowrite16(data->blksz, host->ioaddr + SD_CARDXFERDATALEN);
494}
495
496/* Process requests from the MMC layer */
497static void toshsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
498{
499 struct toshsd_host *host = mmc_priv(mmc);
500 unsigned long flags;
501
502 /* abort if card not present */
503 if (!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0)) {
504 mrq->cmd->error = -ENOMEDIUM;
505 mmc_request_done(mmc, mrq);
506 return;
507 }
508
509 spin_lock_irqsave(&host->lock, flags);
510
511 WARN_ON(host->mrq != NULL);
512
513 host->mrq = mrq;
514
515 if (mrq->data)
516 toshsd_start_data(host, mrq->data);
517
518 toshsd_set_led(host, 1);
519
520 toshsd_start_cmd(host, mrq->cmd);
521
522 spin_unlock_irqrestore(&host->lock, flags);
523}
524
525static void toshsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
526{
527 struct toshsd_host *host = mmc_priv(mmc);
528 unsigned long flags;
529
530 spin_lock_irqsave(&host->lock, flags);
531 __toshsd_set_ios(mmc, ios);
532 spin_unlock_irqrestore(&host->lock, flags);
533}
534
535static int toshsd_get_ro(struct mmc_host *mmc)
536{
537 struct toshsd_host *host = mmc_priv(mmc);
538
539 /* active low */
540 return !(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_WRITE_PROTECT);
541}
542
543static int toshsd_get_cd(struct mmc_host *mmc)
544{
545 struct toshsd_host *host = mmc_priv(mmc);
546
547 return !!(ioread16(host->ioaddr + SD_CARDSTATUS) & SD_CARD_PRESENT_0);
548}
549
550static struct mmc_host_ops toshsd_ops = {
551 .request = toshsd_request,
552 .set_ios = toshsd_set_ios,
553 .get_ro = toshsd_get_ro,
554 .get_cd = toshsd_get_cd,
555};
556
557
558static void toshsd_powerdown(struct toshsd_host *host)
559{
560 /* mask all interrupts */
561 iowrite32(0xffffffff, host->ioaddr + SD_INTMASKCARD);
562 /* disable card clock */
563 iowrite16(0x000, host->ioaddr + SDIO_BASE + SDIO_CLOCKNWAITCTRL);
564 iowrite16(0, host->ioaddr + SD_CARDCLOCKCTRL);
565 /* power down card */
566 pci_write_config_byte(host->pdev, SD_PCICFG_POWER1, SD_PCICFG_PWR1_OFF);
567 /* disable clock */
568 pci_write_config_byte(host->pdev, SD_PCICFG_CLKSTOP, 0);
569}
570
571#ifdef CONFIG_PM_SLEEP
572static int toshsd_pm_suspend(struct device *dev)
573{
574 struct pci_dev *pdev = to_pci_dev(dev);
575 struct toshsd_host *host = pci_get_drvdata(pdev);
576
577 toshsd_powerdown(host);
578
579 pci_save_state(pdev);
580 pci_enable_wake(pdev, PCI_D3hot, 0);
581 pci_disable_device(pdev);
582 pci_set_power_state(pdev, PCI_D3hot);
583
584 return 0;
585}
586
587static int toshsd_pm_resume(struct device *dev)
588{
589 struct pci_dev *pdev = to_pci_dev(dev);
590 struct toshsd_host *host = pci_get_drvdata(pdev);
591 int ret;
592
593 pci_set_power_state(pdev, PCI_D0);
594 pci_restore_state(pdev);
595 ret = pci_enable_device(pdev);
596 if (ret)
597 return ret;
598
599 toshsd_init(host);
600
601 return 0;
602}
603#endif /* CONFIG_PM_SLEEP */
604
605static int toshsd_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
606{
607 int ret;
608 struct toshsd_host *host;
609 struct mmc_host *mmc;
610 resource_size_t base;
611
612 ret = pci_enable_device(pdev);
613 if (ret)
614 return ret;
615
616 mmc = mmc_alloc_host(sizeof(struct toshsd_host), &pdev->dev);
617 if (!mmc) {
618 ret = -ENOMEM;
619 goto err;
620 }
621
622 host = mmc_priv(mmc);
623 host->mmc = mmc;
624
625 host->pdev = pdev;
626 pci_set_drvdata(pdev, host);
627
628 ret = pci_request_regions(pdev, DRIVER_NAME);
629 if (ret)
630 goto free;
631
632 host->ioaddr = pci_iomap(pdev, 0, 0);
633 if (!host->ioaddr) {
634 ret = -ENOMEM;
635 goto release;
636 }
637
638 /* Set MMC host parameters */
639 mmc->ops = &toshsd_ops;
640 mmc->caps = MMC_CAP_4_BIT_DATA;
641 mmc->ocr_avail = MMC_VDD_32_33;
642
643 mmc->f_min = HCLK / 512;
644 mmc->f_max = HCLK;
645
646 spin_lock_init(&host->lock);
647
648 toshsd_init(host);
649
650 ret = request_threaded_irq(pdev->irq, toshsd_irq, toshsd_thread_irq,
651 IRQF_SHARED, DRIVER_NAME, host);
652 if (ret)
653 goto unmap;
654
655 mmc_add_host(mmc);
656
657 base = pci_resource_start(pdev, 0);
658 dev_dbg(&pdev->dev, "MMIO %pa, IRQ %d\n", &base, pdev->irq);
659
660 pm_suspend_ignore_children(&pdev->dev, 1);
661
662 return 0;
663
664unmap:
665 pci_iounmap(pdev, host->ioaddr);
666release:
667 pci_release_regions(pdev);
668free:
669 mmc_free_host(mmc);
670 pci_set_drvdata(pdev, NULL);
671err:
672 pci_disable_device(pdev);
673 return ret;
674}
675
676static void toshsd_remove(struct pci_dev *pdev)
677{
678 struct toshsd_host *host = pci_get_drvdata(pdev);
679
680 mmc_remove_host(host->mmc);
681 toshsd_powerdown(host);
682 free_irq(pdev->irq, host);
683 pci_iounmap(pdev, host->ioaddr);
684 pci_release_regions(pdev);
685 mmc_free_host(host->mmc);
686 pci_set_drvdata(pdev, NULL);
687 pci_disable_device(pdev);
688}
689
690static const struct dev_pm_ops toshsd_pm_ops = {
691 SET_SYSTEM_SLEEP_PM_OPS(toshsd_pm_suspend, toshsd_pm_resume)
692};
693
694static struct pci_driver toshsd_driver = {
695 .name = DRIVER_NAME,
696 .id_table = pci_ids,
697 .probe = toshsd_probe,
698 .remove = toshsd_remove,
699 .driver.pm = &toshsd_pm_ops,
700};
701
702static int __init toshsd_drv_init(void)
703{
704 return pci_register_driver(&toshsd_driver);
705}
706
707static void __exit toshsd_drv_exit(void)
708{
709 pci_unregister_driver(&toshsd_driver);
710}
711
712module_init(toshsd_drv_init);
713module_exit(toshsd_drv_exit);
714
715MODULE_AUTHOR("Ondrej Zary, Richard Betts");
716MODULE_DESCRIPTION("Toshiba PCI Secure Digital Host Controller Interface driver");
717MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/toshsd.h b/drivers/mmc/host/toshsd.h
new file mode 100644
index 000000000000..b6c0d89e53a6
--- /dev/null
+++ b/drivers/mmc/host/toshsd.h
@@ -0,0 +1,176 @@
1/*
2 * Toshiba PCI Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2014 Ondrej Zary
5 * Copyright (C) 2007 Richard Betts, All Rights Reserved.
6 *
7 * Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or (at
12 * your option) any later version.
13 */
14
15#define HCLK 33000000 /* 33 MHz (PCI clock) */
16
17#define SD_PCICFG_CLKSTOP 0x40 /* 0x1f = clock controller, 0 = stop */
18#define SD_PCICFG_GATEDCLK 0x41 /* Gated clock */
19#define SD_PCICFG_CLKMODE 0x42 /* Control clock of SD controller */
20#define SD_PCICFG_PINSTATUS 0x44 /* R/O: read status of SD pins */
21#define SD_PCICFG_POWER1 0x48
22#define SD_PCICFG_POWER2 0x49
23#define SD_PCICFG_POWER3 0x4a
24#define SD_PCICFG_CARDDETECT 0x4c
25#define SD_PCICFG_SLOTS 0x50 /* R/O: define support slot number */
26#define SD_PCICFG_EXTGATECLK1 0xf0 /* Could be used for gated clock */
27#define SD_PCICFG_EXTGATECLK2 0xf1 /* Could be used for gated clock */
28#define SD_PCICFG_EXTGATECLK3 0xf9 /* Bit 1: double buffer/single buffer */
29#define SD_PCICFG_SDLED_ENABLE1 0xfa
30#define SD_PCICFG_SDLED_ENABLE2 0xfe
31
32#define SD_PCICFG_CLKMODE_DIV_DISABLE BIT(0)
33#define SD_PCICFG_CLKSTOP_ENABLE_ALL 0x1f
34#define SD_PCICFG_LED_ENABLE1_START 0x12
35#define SD_PCICFG_LED_ENABLE2_START 0x80
36
37#define SD_PCICFG_PWR1_33V 0x08 /* Set for 3.3 volts */
38#define SD_PCICFG_PWR1_OFF 0x00 /* Turn off power */
39#define SD_PCICFG_PWR2_AUTO 0x02
40
41#define SD_CMD 0x00 /* also for SDIO */
42#define SD_ARG0 0x04 /* also for SDIO */
43#define SD_ARG1 0x06 /* also for SDIO */
44#define SD_STOPINTERNAL 0x08
45#define SD_BLOCKCOUNT 0x0a /* also for SDIO */
46#define SD_RESPONSE0 0x0c /* also for SDIO */
47#define SD_RESPONSE1 0x0e /* also for SDIO */
48#define SD_RESPONSE2 0x10 /* also for SDIO */
49#define SD_RESPONSE3 0x12 /* also for SDIO */
50#define SD_RESPONSE4 0x14 /* also for SDIO */
51#define SD_RESPONSE5 0x16 /* also for SDIO */
52#define SD_RESPONSE6 0x18 /* also for SDIO */
53#define SD_RESPONSE7 0x1a /* also for SDIO */
54#define SD_CARDSTATUS 0x1c /* also for SDIO */
55#define SD_BUFFERCTRL 0x1e /* also for SDIO */
56#define SD_INTMASKCARD 0x20 /* also for SDIO */
57#define SD_INTMASKBUFFER 0x22 /* also for SDIO */
58#define SD_CARDCLOCKCTRL 0x24
59#define SD_CARDXFERDATALEN 0x26 /* also for SDIO */
60#define SD_CARDOPTIONSETUP 0x28 /* also for SDIO */
61#define SD_ERRORSTATUS0 0x2c /* also for SDIO */
62#define SD_ERRORSTATUS1 0x2e /* also for SDIO */
63#define SD_DATAPORT 0x30 /* also for SDIO */
64#define SD_TRANSACTIONCTRL 0x34 /* also for SDIO */
65#define SD_SOFTWARERESET 0xe0 /* also for SDIO */
66
67/* registers above marked "also for SDIO" and all SDIO registers below can be
68 * accessed at SDIO_BASE + reg address */
69#define SDIO_BASE 0x100
70
71#define SDIO_CARDPORTSEL 0x02
72#define SDIO_CARDINTCTRL 0x36
73#define SDIO_CLOCKNWAITCTRL 0x38
74#define SDIO_HOSTINFORMATION 0x3a
75#define SDIO_ERRORCTRL 0x3c
76#define SDIO_LEDCTRL 0x3e
77
78#define SD_TRANSCTL_SET BIT(8)
79
80#define SD_CARDCLK_DIV_DISABLE BIT(15)
81#define SD_CARDCLK_ENABLE_CLOCK BIT(8)
82#define SD_CARDCLK_CLK_DIV_512 BIT(7)
83#define SD_CARDCLK_CLK_DIV_256 BIT(6)
84#define SD_CARDCLK_CLK_DIV_128 BIT(5)
85#define SD_CARDCLK_CLK_DIV_64 BIT(4)
86#define SD_CARDCLK_CLK_DIV_32 BIT(3)
87#define SD_CARDCLK_CLK_DIV_16 BIT(2)
88#define SD_CARDCLK_CLK_DIV_8 BIT(1)
89#define SD_CARDCLK_CLK_DIV_4 BIT(0)
90#define SD_CARDCLK_CLK_DIV_2 0
91
92#define SD_CARDOPT_REQUIRED 0x000e
93#define SD_CARDOPT_DATA_RESP_TIMEOUT(x) (((x) & 0x0f) << 4) /* 4 bits */
94#define SD_CARDOPT_C2_MODULE_ABSENT BIT(14)
95#define SD_CARDOPT_DATA_XFR_WIDTH_1 (1 << 15)
96#define SD_CARDOPT_DATA_XFR_WIDTH_4 (0 << 15)
97
98#define SD_CMD_TYPE_CMD (0 << 6)
99#define SD_CMD_TYPE_ACMD (1 << 6)
100#define SD_CMD_TYPE_AUTHEN (2 << 6)
101#define SD_CMD_RESP_TYPE_NONE (3 << 8)
102#define SD_CMD_RESP_TYPE_EXT_R1 (4 << 8)
103#define SD_CMD_RESP_TYPE_EXT_R1B (5 << 8)
104#define SD_CMD_RESP_TYPE_EXT_R2 (6 << 8)
105#define SD_CMD_RESP_TYPE_EXT_R3 (7 << 8)
106#define SD_CMD_RESP_TYPE_EXT_R6 (4 << 8)
107#define SD_CMD_RESP_TYPE_EXT_R7 (4 << 8)
108#define SD_CMD_DATA_PRESENT BIT(11)
109#define SD_CMD_TRANSFER_READ BIT(12)
110#define SD_CMD_MULTI_BLOCK BIT(13)
111#define SD_CMD_SECURITY_CMD BIT(14)
112
113#define SD_STOPINT_ISSUE_CMD12 BIT(0)
114#define SD_STOPINT_AUTO_ISSUE_CMD12 BIT(8)
115
116#define SD_CARD_RESP_END BIT(0)
117#define SD_CARD_RW_END BIT(2)
118#define SD_CARD_CARD_REMOVED_0 BIT(3)
119#define SD_CARD_CARD_INSERTED_0 BIT(4)
120#define SD_CARD_PRESENT_0 BIT(5)
121#define SD_CARD_UNK6 BIT(6)
122#define SD_CARD_WRITE_PROTECT BIT(7)
123#define SD_CARD_CARD_REMOVED_3 BIT(8)
124#define SD_CARD_CARD_INSERTED_3 BIT(9)
125#define SD_CARD_PRESENT_3 BIT(10)
126
127#define SD_BUF_CMD_INDEX_ERR BIT(16)
128#define SD_BUF_CRC_ERR BIT(17)
129#define SD_BUF_STOP_BIT_END_ERR BIT(18)
130#define SD_BUF_DATA_TIMEOUT BIT(19)
131#define SD_BUF_OVERFLOW BIT(20)
132#define SD_BUF_UNDERFLOW BIT(21)
133#define SD_BUF_CMD_TIMEOUT BIT(22)
134#define SD_BUF_UNK7 BIT(23)
135#define SD_BUF_READ_ENABLE BIT(24)
136#define SD_BUF_WRITE_ENABLE BIT(25)
137#define SD_BUF_ILLEGAL_FUNCTION BIT(29)
138#define SD_BUF_CMD_BUSY BIT(30)
139#define SD_BUF_ILLEGAL_ACCESS BIT(31)
140
141#define SD_ERR0_RESP_CMD_ERR BIT(0)
142#define SD_ERR0_RESP_NON_CMD12_END_BIT_ERR BIT(2)
143#define SD_ERR0_RESP_CMD12_END_BIT_ERR BIT(3)
144#define SD_ERR0_READ_DATA_END_BIT_ERR BIT(4)
145#define SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR BIT(5)
146#define SD_ERR0_RESP_NON_CMD12_CRC_ERR BIT(8)
147#define SD_ERR0_RESP_CMD12_CRC_ERR BIT(9)
148#define SD_ERR0_READ_DATA_CRC_ERR BIT(10)
149#define SD_ERR0_WRITE_CMD_CRC_ERR BIT(11)
150
151#define SD_ERR1_NO_CMD_RESP BIT(16)
152#define SD_ERR1_TIMEOUT_READ_DATA BIT(20)
153#define SD_ERR1_TIMEOUT_CRS_STATUS BIT(21)
154#define SD_ERR1_TIMEOUT_CRC_BUSY BIT(22)
155
156#define IRQ_DONT_CARE_BITS (SD_CARD_PRESENT_3 \
157 | SD_CARD_WRITE_PROTECT \
158 | SD_CARD_UNK6 \
159 | SD_CARD_PRESENT_0 \
160 | SD_BUF_UNK7 \
161 | SD_BUF_CMD_BUSY)
162
163struct toshsd_host {
164 struct pci_dev *pdev;
165 struct mmc_host *mmc;
166
167 spinlock_t lock;
168
169 struct mmc_request *mrq;/* Current request */
170 struct mmc_command *cmd;/* Current command */
171 struct mmc_data *data; /* Current data request */
172
173 struct sg_mapping_iter sg_miter; /* for PIO */
174
175 void __iomem *ioaddr; /* mapped address */
176};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-08 11:48:51 -0400