diff options
| author | Dinh Nguyen <dinguyen@altera.com> | 2013-12-03 15:32:10 -0500 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2013-12-03 17:19:53 -0500 |
| commit | a5c6e87a7b224bdbf57875a9da8f340f5a6abc5a (patch) | |
| tree | 576ee8ba1d6fae188d433684bed319214c700ae4 | |
| parent | 725dd7eb170af813407ee45409590941a5ac626e (diff) | |
arm: dts: socfpga: Change some clocks of gate-clk type to perip-clk
Some of the clocks that were designated gate-clk do not have a gate, so
change those clocks to be of periph-clk type.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 6d09b8d42fdd..f936476c2753 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -245,14 +245,14 @@ | |||
| 245 | 245 | ||
| 246 | mpu_periph_clk: mpu_periph_clk { | 246 | mpu_periph_clk: mpu_periph_clk { |
| 247 | #clock-cells = <0>; | 247 | #clock-cells = <0>; |
| 248 | compatible = "altr,socfpga-gate-clk"; | 248 | compatible = "altr,socfpga-perip-clk"; |
| 249 | clocks = <&mpuclk>; | 249 | clocks = <&mpuclk>; |
| 250 | fixed-divider = <4>; | 250 | fixed-divider = <4>; |
| 251 | }; | 251 | }; |
| 252 | 252 | ||
| 253 | mpu_l2_ram_clk: mpu_l2_ram_clk { | 253 | mpu_l2_ram_clk: mpu_l2_ram_clk { |
| 254 | #clock-cells = <0>; | 254 | #clock-cells = <0>; |
| 255 | compatible = "altr,socfpga-gate-clk"; | 255 | compatible = "altr,socfpga-perip-clk"; |
| 256 | clocks = <&mpuclk>; | 256 | clocks = <&mpuclk>; |
| 257 | fixed-divider = <2>; | 257 | fixed-divider = <2>; |
| 258 | }; | 258 | }; |
| @@ -266,8 +266,9 @@ | |||
| 266 | 266 | ||
| 267 | l3_main_clk: l3_main_clk { | 267 | l3_main_clk: l3_main_clk { |
| 268 | #clock-cells = <0>; | 268 | #clock-cells = <0>; |
| 269 | compatible = "altr,socfpga-gate-clk"; | 269 | compatible = "altr,socfpga-perip-clk"; |
| 270 | clocks = <&mainclk>; | 270 | clocks = <&mainclk>; |
| 271 | fixed-divider = <1>; | ||
| 271 | }; | 272 | }; |
| 272 | 273 | ||
| 273 | l3_mp_clk: l3_mp_clk { | 274 | l3_mp_clk: l3_mp_clk { |