diff options
| author | Luciano Coelho <coelho@ti.com> | 2012-06-26 15:43:29 -0400 |
|---|---|---|
| committer | Luciano Coelho <coelho@ti.com> | 2012-06-26 15:43:29 -0400 |
| commit | a572ac1a3d37440dc9daf69f9ad63243bef6893f (patch) | |
| tree | 4f2f66f8849118c4e7d0288825e779e9b8fcfef0 | |
| parent | 6bcfe67f9865fb51ec78fc9b09887375db7e08b5 (diff) | |
| parent | 680c6055b9bebdf07fc2d5ebe816a14c7daecdc1 (diff) | |
Merge branch 'wl12xx-next' into for-linville
22 files changed, 1257 insertions, 475 deletions
diff --git a/drivers/net/wireless/ti/wl12xx/main.c b/drivers/net/wireless/ti/wl12xx/main.c index 0d2fdca2aa32..47ba2e0017f4 100644 --- a/drivers/net/wireless/ti/wl12xx/main.c +++ b/drivers/net/wireless/ti/wl12xx/main.c | |||
| @@ -598,8 +598,10 @@ static const int wl12xx_rtable[REG_TABLE_LEN] = { | |||
| 598 | #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-4-sr.bin" | 598 | #define WL128X_FW_NAME_SINGLE "ti-connectivity/wl128x-fw-4-sr.bin" |
| 599 | #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-4-plt.bin" | 599 | #define WL128X_PLT_FW_NAME "ti-connectivity/wl128x-fw-4-plt.bin" |
| 600 | 600 | ||
| 601 | static void wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len) | 601 | static int wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len) |
| 602 | { | 602 | { |
| 603 | int ret; | ||
| 604 | |||
| 603 | if (wl->chip.id != CHIP_ID_1283_PG20) { | 605 | if (wl->chip.id != CHIP_ID_1283_PG20) { |
| 604 | struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map; | 606 | struct wl1271_acx_mem_map *wl_mem_map = wl->target_mem_map; |
| 605 | struct wl127x_rx_mem_pool_addr rx_mem_addr; | 607 | struct wl127x_rx_mem_pool_addr rx_mem_addr; |
| @@ -616,9 +618,13 @@ static void wl127x_prepare_read(struct wl1271 *wl, u32 rx_desc, u32 len) | |||
| 616 | 618 | ||
| 617 | rx_mem_addr.addr_extra = rx_mem_addr.addr + 4; | 619 | rx_mem_addr.addr_extra = rx_mem_addr.addr + 4; |
| 618 | 620 | ||
| 619 | wl1271_write(wl, WL1271_SLV_REG_DATA, | 621 | ret = wlcore_write(wl, WL1271_SLV_REG_DATA, &rx_mem_addr, |
| 620 | &rx_mem_addr, sizeof(rx_mem_addr), false); | 622 | sizeof(rx_mem_addr), false); |
| 623 | if (ret < 0) | ||
| 624 | return ret; | ||
| 621 | } | 625 | } |
| 626 | |||
| 627 | return 0; | ||
| 622 | } | 628 | } |
| 623 | 629 | ||
| 624 | static int wl12xx_identify_chip(struct wl1271 *wl) | 630 | static int wl12xx_identify_chip(struct wl1271 *wl) |
| @@ -682,64 +688,95 @@ out: | |||
| 682 | return ret; | 688 | return ret; |
| 683 | } | 689 | } |
| 684 | 690 | ||
| 685 | static void wl12xx_top_reg_write(struct wl1271 *wl, int addr, u16 val) | 691 | static int __must_check wl12xx_top_reg_write(struct wl1271 *wl, int addr, |
| 692 | u16 val) | ||
| 686 | { | 693 | { |
| 694 | int ret; | ||
| 695 | |||
| 687 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ | 696 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ |
| 688 | addr = (addr >> 1) + 0x30000; | 697 | addr = (addr >> 1) + 0x30000; |
| 689 | wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr); | 698 | ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr); |
| 699 | if (ret < 0) | ||
| 700 | goto out; | ||
| 690 | 701 | ||
| 691 | /* write value to OCP_POR_WDATA */ | 702 | /* write value to OCP_POR_WDATA */ |
| 692 | wl1271_write32(wl, WL12XX_OCP_DATA_WRITE, val); | 703 | ret = wlcore_write32(wl, WL12XX_OCP_DATA_WRITE, val); |
| 704 | if (ret < 0) | ||
| 705 | goto out; | ||
| 693 | 706 | ||
| 694 | /* write 1 to OCP_CMD */ | 707 | /* write 1 to OCP_CMD */ |
| 695 | wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE); | 708 | ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_WRITE); |
| 709 | if (ret < 0) | ||
| 710 | goto out; | ||
| 711 | |||
| 712 | out: | ||
| 713 | return ret; | ||
| 696 | } | 714 | } |
| 697 | 715 | ||
| 698 | static u16 wl12xx_top_reg_read(struct wl1271 *wl, int addr) | 716 | static int __must_check wl12xx_top_reg_read(struct wl1271 *wl, int addr, |
| 717 | u16 *out) | ||
| 699 | { | 718 | { |
| 700 | u32 val; | 719 | u32 val; |
| 701 | int timeout = OCP_CMD_LOOP; | 720 | int timeout = OCP_CMD_LOOP; |
| 721 | int ret; | ||
| 702 | 722 | ||
| 703 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ | 723 | /* write address >> 1 + 0x30000 to OCP_POR_CTR */ |
| 704 | addr = (addr >> 1) + 0x30000; | 724 | addr = (addr >> 1) + 0x30000; |
| 705 | wl1271_write32(wl, WL12XX_OCP_POR_CTR, addr); | 725 | ret = wlcore_write32(wl, WL12XX_OCP_POR_CTR, addr); |
| 726 | if (ret < 0) | ||
| 727 | return ret; | ||
| 706 | 728 | ||
| 707 | /* write 2 to OCP_CMD */ | 729 | /* write 2 to OCP_CMD */ |
| 708 | wl1271_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ); | 730 | ret = wlcore_write32(wl, WL12XX_OCP_CMD, OCP_CMD_READ); |
| 731 | if (ret < 0) | ||
| 732 | return ret; | ||
| 709 | 733 | ||
| 710 | /* poll for data ready */ | 734 | /* poll for data ready */ |
| 711 | do { | 735 | do { |
| 712 | val = wl1271_read32(wl, WL12XX_OCP_DATA_READ); | 736 | ret = wlcore_read32(wl, WL12XX_OCP_DATA_READ, &val); |
| 737 | if (ret < 0) | ||
| 738 | return ret; | ||
| 713 | } while (!(val & OCP_READY_MASK) && --timeout); | 739 | } while (!(val & OCP_READY_MASK) && --timeout); |
| 714 | 740 | ||
| 715 | if (!timeout) { | 741 | if (!timeout) { |
| 716 | wl1271_warning("Top register access timed out."); | 742 | wl1271_warning("Top register access timed out."); |
| 717 | return 0xffff; | 743 | return -ETIMEDOUT; |
| 718 | } | 744 | } |
| 719 | 745 | ||
| 720 | /* check data status and return if OK */ | 746 | /* check data status and return if OK */ |
| 721 | if ((val & OCP_STATUS_MASK) == OCP_STATUS_OK) | 747 | if ((val & OCP_STATUS_MASK) != OCP_STATUS_OK) { |
| 722 | return val & 0xffff; | ||
| 723 | else { | ||
| 724 | wl1271_warning("Top register access returned error."); | 748 | wl1271_warning("Top register access returned error."); |
| 725 | return 0xffff; | 749 | return -EIO; |
| 726 | } | 750 | } |
| 751 | |||
| 752 | if (out) | ||
| 753 | *out = val & 0xffff; | ||
| 754 | |||
| 755 | return 0; | ||
| 727 | } | 756 | } |
| 728 | 757 | ||
| 729 | static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl) | 758 | static int wl128x_switch_tcxo_to_fref(struct wl1271 *wl) |
| 730 | { | 759 | { |
| 731 | u16 spare_reg; | 760 | u16 spare_reg; |
| 761 | int ret; | ||
| 732 | 762 | ||
| 733 | /* Mask bits [2] & [8:4] in the sys_clk_cfg register */ | 763 | /* Mask bits [2] & [8:4] in the sys_clk_cfg register */ |
| 734 | spare_reg = wl12xx_top_reg_read(wl, WL_SPARE_REG); | 764 | ret = wl12xx_top_reg_read(wl, WL_SPARE_REG, &spare_reg); |
| 765 | if (ret < 0) | ||
| 766 | return ret; | ||
| 767 | |||
| 735 | if (spare_reg == 0xFFFF) | 768 | if (spare_reg == 0xFFFF) |
| 736 | return -EFAULT; | 769 | return -EFAULT; |
| 737 | spare_reg |= (BIT(3) | BIT(5) | BIT(6)); | 770 | spare_reg |= (BIT(3) | BIT(5) | BIT(6)); |
| 738 | wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg); | 771 | ret = wl12xx_top_reg_write(wl, WL_SPARE_REG, spare_reg); |
| 772 | if (ret < 0) | ||
