diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2011-01-06 21:19:33 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2011-01-06 23:11:42 -0500 |
| commit | a43b7665de7b1adbda5ce19d57cb65add0982c8f (patch) | |
| tree | 36b4e267c68e3526d5dd360fd943374a19999ef5 | |
| parent | ed18a3603f5b466e0300fc5e0c349dbcce376861 (diff) | |
drm/radeon/kms: add radeon_asic struct for NI asics
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 53c62404795d..3a1b16186224 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
| @@ -836,6 +836,52 @@ static struct radeon_asic sumo_asic = { | |||
| 836 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | 836 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, |
| 837 | }; | 837 | }; |
| 838 | 838 | ||
| 839 | static struct radeon_asic btc_asic = { | ||
| 840 | .init = &evergreen_init, | ||
| 841 | .fini = &evergreen_fini, | ||
| 842 | .suspend = &evergreen_suspend, | ||
| 843 | .resume = &evergreen_resume, | ||
| 844 | .cp_commit = &r600_cp_commit, | ||
| 845 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | ||
| 846 | .asic_reset = &evergreen_asic_reset, | ||
| 847 | .vga_set_state = &r600_vga_set_state, | ||
| 848 | .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush, | ||
| 849 | .gart_set_page = &rs600_gart_set_page, | ||
| 850 | .ring_test = &r600_ring_test, | ||
| 851 | .ring_ib_execute = &r600_ring_ib_execute, | ||
| 852 | .irq_set = &evergreen_irq_set, | ||
| 853 | .irq_process = &evergreen_irq_process, | ||
| 854 | .get_vblank_counter = &evergreen_get_vblank_counter, | ||
| 855 | .fence_ring_emit = &r600_fence_ring_emit, | ||
| 856 | .cs_parse = &evergreen_cs_parse, | ||
| 857 | .copy_blit = &evergreen_copy_blit, | ||
| 858 | .copy_dma = &evergreen_copy_blit, | ||
| 859 | .copy = &evergreen_copy_blit, | ||
| 860 | .get_engine_clock = &radeon_atom_get_engine_clock, | ||
| 861 | .set_engine_clock = &radeon_atom_set_engine_clock, | ||
| 862 | .get_memory_clock = &radeon_atom_get_memory_clock, | ||
| 863 | .set_memory_clock = &radeon_atom_set_memory_clock, | ||
| 864 | .get_pcie_lanes = NULL, | ||
| 865 | .set_pcie_lanes = NULL, | ||
| 866 | .set_clock_gating = NULL, | ||
| 867 | .set_surface_reg = r600_set_surface_reg, | ||
| 868 | .clear_surface_reg = r600_clear_surface_reg, | ||
| 869 | .bandwidth_update = &evergreen_bandwidth_update, | ||
| 870 | .hpd_init = &evergreen_hpd_init, | ||
| 871 | .hpd_fini = &evergreen_hpd_fini, | ||
| 872 | .hpd_sense = &evergreen_hpd_sense, | ||
| 873 | .hpd_set_polarity = &evergreen_hpd_set_polarity, | ||
| 874 | .gui_idle = &r600_gui_idle, | ||
| 875 | .pm_misc = &evergreen_pm_misc, | ||
| 876 | .pm_prepare = &evergreen_pm_prepare, | ||
| 877 | .pm_finish = &evergreen_pm_finish, | ||
| 878 | .pm_init_profile = &r600_pm_init_profile, | ||
| 879 | .pm_get_dynpm_state = &r600_pm_get_dynpm_state, | ||
| 880 | .pre_page_flip = &evergreen_pre_page_flip, | ||
| 881 | .page_flip = &evergreen_page_flip, | ||
| 882 | .post_page_flip = &evergreen_post_page_flip, | ||
| 883 | }; | ||
| 884 | |||
| 839 | int radeon_asic_init(struct radeon_device *rdev) | 885 | int radeon_asic_init(struct radeon_device *rdev) |
| 840 | { | 886 | { |
| 841 | radeon_register_accessor_init(rdev); | 887 | radeon_register_accessor_init(rdev); |
| @@ -923,6 +969,11 @@ int radeon_asic_init(struct radeon_device *rdev) | |||
| 923 | case CHIP_PALM: | 969 | case CHIP_PALM: |
| 924 | rdev->asic = &sumo_asic; | 970 | rdev->asic = &sumo_asic; |
| 925 | break; | 971 | break; |
| 972 | case CHIP_BARTS: | ||
| 973 | case CHIP_TURKS: | ||
| 974 | case CHIP_CAICOS: | ||
| 975 | rdev->asic = &btc_asic; | ||
| 976 | break; | ||
| 926 | default: | 977 | default: |
| 927 | /* FIXME: not supported yet */ | 978 | /* FIXME: not supported yet */ |
| 928 | return -EINVAL; | 979 | return -EINVAL; |
