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authorFelix Fietkau <nbd@openwrt.org>2012-07-15 13:53:33 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-07-17 15:11:34 -0400
commita364517b1ed6010bc2bbb98af493d18339d058e9 (patch)
tree07ff5d04a92e6a4ce6f540c6b35e56615c2c9520
parentb05a01110ed10a93203d936a06aa01bf80837c39 (diff)
ath9k_hw: remove redundant arguments to INIT_INI_ARRAY
The row/column sizes can be derived from the array argument within the macro itself, which is less error prone. In a few cases the supplied column size was actually wrong. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_hw.c159
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9003_hw.c541
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.h6
3 files changed, 201 insertions, 505 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 0e6ee60aed00..648da3e885e9 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -26,106 +26,74 @@
26static void ar9002_hw_init_mode_regs(struct ath_hw *ah) 26static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
27{ 27{
28 if (AR_SREV_9271(ah)) { 28 if (AR_SREV_9271(ah)) {
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271, 29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
30 ARRAY_SIZE(ar9271Modes_9271), 5); 30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
31 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271, 31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
32 ARRAY_SIZE(ar9271Common_9271), 2);
33 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
34 ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
35 return; 32 return;
36 } 33 }
37 34
38 if (ah->config.pcie_clock_req) 35 if (ah->config.pcie_clock_req)
39 INIT_INI_ARRAY(&ah->iniPcieSerdes, 36 INIT_INI_ARRAY(&ah->iniPcieSerdes,
40 ar9280PciePhy_clkreq_off_L1_9280, 37 ar9280PciePhy_clkreq_off_L1_9280);
41 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
42 else 38 else
43 INIT_INI_ARRAY(&ah->iniPcieSerdes, 39 INIT_INI_ARRAY(&ah->iniPcieSerdes,
44 ar9280PciePhy_clkreq_always_on_L1_9280, 40 ar9280PciePhy_clkreq_always_on_L1_9280);
45 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
46#ifdef CONFIG_PM_SLEEP 41#ifdef CONFIG_PM_SLEEP
47 INIT_INI_ARRAY(&ah->iniPcieSerdesWow, 42 INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
48 ar9280PciePhy_awow, 43 ar9280PciePhy_awow);
49 ARRAY_SIZE(ar9280PciePhy_awow), 2);
50#endif 44#endif
51 45
52 if (AR_SREV_9287_11_OR_LATER(ah)) { 46 if (AR_SREV_9287_11_OR_LATER(ah)) {
53 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1, 47 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
54 ARRAY_SIZE(ar9287Modes_9287_1_1), 5); 48 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
55 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
56 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
57 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 49 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
58 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2, 50 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
59 ARRAY_SIZE(ar9285Modes_9285_1_2), 5); 51 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
60 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
61 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
62 } else if (AR_SREV_9280_20_OR_LATER(ah)) { 52 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
63 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2, 53 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
64 ARRAY_SIZE(ar9280Modes_9280_2), 5); 54 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
65 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
66 ARRAY_SIZE(ar9280Common_9280_2), 2);
67 55
68 INIT_INI_ARRAY(&ah->iniModesFastClock, 56 INIT_INI_ARRAY(&ah->iniModesFastClock,
69 ar9280Modes_fast_clock_9280_2, 57 ar9280Modes_fast_clock_9280_2);
70 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
71 } else if (AR_SREV_9160_10_OR_LATER(ah)) { 58 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
72 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160, 59 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
73 ARRAY_SIZE(ar5416Modes_9160), 5); 60 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
74 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
75 ARRAY_SIZE(ar5416Common_9160), 2);
76 if (AR_SREV_9160_11(ah)) { 61 if (AR_SREV_9160_11(ah)) {
77 INIT_INI_ARRAY(&ah->iniAddac, 62 INIT_INI_ARRAY(&ah->iniAddac,
78 ar5416Addac_9160_1_1, 63 ar5416Addac_9160_1_1);
79 ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
80 } else { 64 } else {
81 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160, 65 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
82 ARRAY_SIZE(ar5416Addac_9160), 2);
83 } 66 }
84 } else if (AR_SREV_9100_OR_LATER(ah)) { 67 } else if (AR_SREV_9100_OR_LATER(ah)) {
85 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100, 68 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
86 ARRAY_SIZE(ar5416Modes_9100), 5); 69 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
87 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100, 70 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
88 ARRAY_SIZE(ar5416Common_9100), 2); 71 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
89 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
90 ARRAY_SIZE(ar5416Bank6_9100), 3);
91 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
92 ARRAY_SIZE(ar5416Addac_9100), 2);
93 } else { 72 } else {
94 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes, 73 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
95 ARRAY_SIZE(ar5416Modes), 5); 74 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
96 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common, 75 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
97 ARRAY_SIZE(ar5416Common), 2); 76 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
98 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
99 ARRAY_SIZE(ar5416Bank6TPC), 3);
100 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
101 ARRAY_SIZE(ar5416Addac), 2);
102 } 77 }
103 78
104 if (!AR_SREV_9280_20_OR_LATER(ah)) { 79 if (!AR_SREV_9280_20_OR_LATER(ah)) {
105 /* Common for AR5416, AR913x, AR9160 */ 80 /* Common for AR5416, AR913x, AR9160 */
106 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain, 81 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
107 ARRAY_SIZE(ar5416BB_RfGain), 3); 82
108 83 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
109 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0, 84 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
110 ARRAY_SIZE(ar5416Bank0), 2); 85 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
111 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1, 86 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
112 ARRAY_SIZE(ar5416Bank1), 2); 87 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
113 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
114 ARRAY_SIZE(ar5416Bank2), 2);
115 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
116 ARRAY_SIZE(ar5416Bank3), 3);
117 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
118 ARRAY_SIZE(ar5416Bank7), 2);
119 88
120 /* Common for AR5416, AR9160 */ 89 /* Common for AR5416, AR9160 */
121 if (!AR_SREV_9100(ah)) 90 if (!AR_SREV_9100(ah))
122 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6, 91 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
123 ARRAY_SIZE(ar5416Bank6), 3);
124 92
125 /* Common for AR913x, AR9160 */ 93 /* Common for AR913x, AR9160 */
126 if (!AR_SREV_5416(ah)) 94 if (!AR_SREV_5416(ah))
127 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100, 95 INIT_INI_ARRAY(&ah->iniBank6TPC,
128 ARRAY_SIZE(ar5416Bank6TPC_9100), 3); 96 ar5416Bank6TPC_9100);
129 } 97 }
130 98
131 /* iniAddac needs to be modified for these chips */ 99 /* iniAddac needs to be modified for these chips */
@@ -148,13 +116,9 @@ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
148 } 116 }
149 if (AR_SREV_9287_11_OR_LATER(ah)) { 117 if (AR_SREV_9287_11_OR_LATER(ah)) {
150 INIT_INI_ARRAY(&ah->iniCckfirNormal, 118 INIT_INI_ARRAY(&ah->iniCckfirNormal,
151 ar9287Common_normal_cck_fir_coeff_9287_1_1, 119 ar9287Common_normal_cck_fir_coeff_9287_1_1);
152 ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
153 2);
154 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 120 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
155 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 121 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
156 ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
157 2);
158 } 122 }
159} 123}
160 124
@@ -168,20 +132,16 @@ static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah)
168 132
169 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF) 133 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
170 INIT_INI_ARRAY(&ah->iniModesRxGain, 134 INIT_INI_ARRAY(&ah->iniModesRxGain,
171 ar9280Modes_backoff_13db_rxgain_9280_2, 135 ar9280Modes_backoff_13db_rxgain_9280_2);
172 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
173 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF) 136 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
174 INIT_INI_ARRAY(&ah->iniModesRxGain, 137 INIT_INI_ARRAY(&ah->iniModesRxGain,
175 ar9280Modes_backoff_23db_rxgain_9280_2, 138 ar9280Modes_backoff_23db_rxgain_9280_2);
176 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
177 else 139 else
178 INIT_INI_ARRAY(&ah->iniModesRxGain, 140 INIT_INI_ARRAY(&ah->iniModesRxGain,
179 ar9280Modes_original_rxgain_9280_2, 141 ar9280Modes_original_rxgain_9280_2);
180 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
181 } else { 142 } else {
182 INIT_INI_ARRAY(&ah->iniModesRxGain, 143 INIT_INI_ARRAY(&ah->iniModesRxGain,
183 ar9280Modes_original_rxgain_9280_2, 144 ar9280Modes_original_rxgain_9280_2);
184 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
185 } 145 }
186} 146}
187 147
@@ -191,16 +151,13 @@ static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
191 AR5416_EEP_MINOR_VER_19) { 151 AR5416_EEP_MINOR_VER_19) {
192 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 152 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
193 INIT_INI_ARRAY(&ah->iniModesTxGain, 153 INIT_INI_ARRAY(&ah->iniModesTxGain,
194 ar9280Modes_high_power_tx_gain_9280_2, 154 ar9280Modes_high_power_tx_gain_9280_2);
195 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
196 else 155 else
197 INIT_INI_ARRAY(&ah->iniModesTxGain, 156 INIT_INI_ARRAY(&ah->iniModesTxGain,
198 ar9280Modes_original_tx_gain_9280_2, 157 ar9280Modes_original_tx_gain_9280_2);
199 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
200 } else { 158 } else {
201 INIT_INI_ARRAY(&ah->iniModesTxGain, 159 INIT_INI_ARRAY(&ah->iniModesTxGain,
202 ar9280Modes_original_tx_gain_9280_2, 160 ar9280Modes_original_tx_gain_9280_2);
203 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
204 } 161 }
205} 162}
206 163
@@ -208,12 +165,10 @@ static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type)
208{ 165{
209 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) 166 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
210 INIT_INI_ARRAY(&ah->iniModesTxGain, 167 INIT_INI_ARRAY(&ah->iniModesTxGain,
211 ar9271Modes_high_power_tx_gain_9271, 168 ar9271Modes_high_power_tx_gain_9271);
212 ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
213 else 169 else
214 INIT_INI_ARRAY(&ah->iniModesTxGain, 170 INIT_INI_ARRAY(&ah->iniModesTxGain,
215 ar9271Modes_normal_power_tx_gain_9271, 171 ar9271Modes_normal_power_tx_gain_9271);
216 ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
217} 172}
218 173
219static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) 174static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
@@ -222,8 +177,7 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
222 177
223 if (AR_SREV_9287_11_OR_LATER(ah)) 178 if (AR_SREV_9287_11_OR_LATER(ah))
224 INIT_INI_ARRAY(&ah->iniModesRxGain, 179 INIT_INI_ARRAY(&ah->iniModesRxGain,
225 ar9287Modes_rx_gain_9287_1_1, 180 ar9287Modes_rx_gain_9287_1_1);
226 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
227 else if (AR_SREV_9280_20(ah)) 181 else if (AR_SREV_9280_20(ah))
228 ar9280_20_hw_init_rxgain_ini(ah); 182 ar9280_20_hw_init_rxgain_ini(ah);
229 183
@@ -231,8 +185,7 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
231 ar9271_hw_init_txgain_ini(ah, txgain_type); 185 ar9271_hw_init_txgain_ini(ah, txgain_type);
232 } else if (AR_SREV_9287_11_OR_LATER(ah)) { 186 } else if (AR_SREV_9287_11_OR_LATER(ah)) {
233 INIT_INI_ARRAY(&ah->iniModesTxGain, 187 INIT_INI_ARRAY(&ah->iniModesTxGain,
234 ar9287Modes_tx_gain_9287_1_1, 188 ar9287Modes_tx_gain_9287_1_1);
235 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
236 } else if (AR_SREV_9280_20(ah)) { 189 } else if (AR_SREV_9280_20(ah)) {
237 ar9280_20_hw_init_txgain_ini(ah, txgain_type); 190 ar9280_20_hw_init_txgain_ini(ah, txgain_type);
238 } else if (AR_SREV_9285_12_OR_LATER(ah)) { 191 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
@@ -240,26 +193,18 @@ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
240 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) { 193 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
241 if (AR_SREV_9285E_20(ah)) { 194 if (AR_SREV_9285E_20(ah)) {
242 INIT_INI_ARRAY(&ah->iniModesTxGain, 195 INIT_INI_ARRAY(&ah->iniModesTxGain,
243 ar9285Modes_XE2_0_high_power, 196 ar9285Modes_XE2_0_high_power);
244 ARRAY_SIZE(
245 ar9285Modes_XE2_0_high_power), 5);
246 } else { 197 } else {
247 INIT_INI_ARRAY(&ah->iniModesTxGain, 198 INIT_INI_ARRAY(&ah->iniModesTxGain,
248 ar9285Modes_high_power_tx_gain_9285_1_2, 199 ar9285Modes_high_power_tx_gain_9285_1_2);
249 ARRAY_SIZE(
250 ar9285Modes_high_power_tx_gain_9285_1_2), 5);
251 } 200 }
252 } else { 201 } else {
253 if (AR_SREV_9285E_20(ah)) { 202 if (AR_SREV_9285E_20(ah)) {
254 INIT_INI_ARRAY(&ah->iniModesTxGain, 203 INIT_INI_ARRAY(&ah->iniModesTxGain,
255 ar9285Modes_XE2_0_normal_power, 204 ar9285Modes_XE2_0_normal_power);
256 ARRAY_SIZE(
257 ar9285Modes_XE2_0_normal_power), 5);
258 } else { 205 } else {
259 INIT_INI_ARRAY(&ah->iniModesTxGain, 206 INIT_INI_ARRAY(&ah->iniModesTxGain,
260 ar9285Modes_original_tx_gain_9285_1_2, 207 ar9285Modes_original_tx_gain_9285_1_2);
261 ARRAY_SIZE(
262 ar9285Modes_original_tx_gain_9285_1_2), 5);
263 } 208 }
264 } 209 }
265 } 210 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 718241d4ec49..1e8a4da5952f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484 44 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
45 if (AR_SREV_9330_11(ah)) { 45 if (AR_SREV_9330_11(ah)) {
46 /* mac */ 46 /* mac */
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
48 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
49 ar9331_1p1_mac_core, 48 ar9331_1p1_mac_core);
50 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
51 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 49 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
52 ar9331_1p1_mac_postamble, 50 ar9331_1p1_mac_postamble);
53 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
54 51
55 /* bb */ 52 /* bb */
56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
57 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 53 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
58 ar9331_1p1_baseband_core, 54 ar9331_1p1_baseband_core);
59 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
60 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
61 ar9331_1p1_baseband_postamble, 56 ar9331_1p1_baseband_postamble);
62 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
63 57
64 /* radio */ 58 /* radio */
65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
66 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 59 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
67 ar9331_1p1_radio_core, 60 ar9331_1p1_radio_core);
68 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
69 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
70 61
71 /* soc */ 62 /* soc */
72 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 63 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
73 ar9331_1p1_soc_preamble, 64 ar9331_1p1_soc_preamble);
74 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
75 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
76 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 65 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
77 ar9331_1p1_soc_postamble, 66 ar9331_1p1_soc_postamble);
78 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
79 67
80 /* rx/tx gain */ 68 /* rx/tx gain */
81 INIT_INI_ARRAY(&ah->iniModesRxGain, 69 INIT_INI_ARRAY(&ah->iniModesRxGain,
82 ar9331_common_rx_gain_1p1, 70 ar9331_common_rx_gain_1p1);
83 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
84 INIT_INI_ARRAY(&ah->iniModesTxGain, 71 INIT_INI_ARRAY(&ah->iniModesTxGain,
85 ar9331_modes_lowest_ob_db_tx_gain_1p1, 72 ar9331_modes_lowest_ob_db_tx_gain_1p1);
86 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
87 5);
88 73
89 /* additional clock settings */ 74 /* additional clock settings */
90 if (ah->is_clk_25mhz) 75 if (ah->is_clk_25mhz)
91 INIT_INI_ARRAY(&ah->iniAdditional, 76 INIT_INI_ARRAY(&ah->iniAdditional,
92 ar9331_1p1_xtal_25M, 77 ar9331_1p1_xtal_25M);
93 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
94 else 78 else
95 INIT_INI_ARRAY(&ah->iniAdditional, 79 INIT_INI_ARRAY(&ah->iniAdditional,
96 ar9331_1p1_xtal_40M, 80 ar9331_1p1_xtal_40M);
97 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
98 } else if (AR_SREV_9330_12(ah)) { 81 } else if (AR_SREV_9330_12(ah)) {
99 /* mac */ 82 /* mac */
100 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
101 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 83 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
102 ar9331_1p2_mac_core, 84 ar9331_1p2_mac_core);
103 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
104 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 85 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
105 ar9331_1p2_mac_postamble, 86 ar9331_1p2_mac_postamble);
106 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
107 87
108 /* bb */ 88 /* bb */
109 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
110 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 89 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
111 ar9331_1p2_baseband_core, 90 ar9331_1p2_baseband_core);
112 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
113 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 91 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
114 ar9331_1p2_baseband_postamble, 92 ar9331_1p2_baseband_postamble);
115 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
116 93
117 /* radio */ 94 /* radio */
118 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
119 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 95 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
120 ar9331_1p2_radio_core, 96 ar9331_1p2_radio_core);
121 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
122 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
123 97
124 /* soc */ 98 /* soc */
125 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 99 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
126 ar9331_1p2_soc_preamble, 100 ar9331_1p2_soc_preamble);
127 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
128 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
129 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 101 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
130 ar9331_1p2_soc_postamble, 102 ar9331_1p2_soc_postamble);
131 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
132 103
133 /* rx/tx gain */ 104 /* rx/tx gain */
134 INIT_INI_ARRAY(&ah->iniModesRxGain, 105 INIT_INI_ARRAY(&ah->iniModesRxGain,
135 ar9331_common_rx_gain_1p2, 106 ar9331_common_rx_gain_1p2);
136 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
137 INIT_INI_ARRAY(&ah->iniModesTxGain, 107 INIT_INI_ARRAY(&ah->iniModesTxGain,
138 ar9331_modes_lowest_ob_db_tx_gain_1p2, 108 ar9331_modes_lowest_ob_db_tx_gain_1p2);
139 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
140 5);
141 109
142 /* additional clock settings */ 110 /* additional clock settings */
143 if (ah->is_clk_25mhz) 111 if (ah->is_clk_25mhz)
144 INIT_INI_ARRAY(&ah->iniAdditional, 112 INIT_INI_ARRAY(&ah->iniAdditional,
145 ar9331_1p2_xtal_25M, 113 ar9331_1p2_xtal_25M);
146 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
147 else 114 else
148 INIT_INI_ARRAY(&ah->iniAdditional, 115 INIT_INI_ARRAY(&ah->iniAdditional,
149 ar9331_1p2_xtal_40M, 116 ar9331_1p2_xtal_40M);
150 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
151 } else if (AR_SREV_9340(ah)) { 117 } else if (AR_SREV_9340(ah)) {
152 /* mac */ 118 /* mac */
153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
154 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 119 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
155 ar9340_1p0_mac_core, 120 ar9340_1p0_mac_core);
156 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
157 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 121 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
158 ar9340_1p0_mac_postamble, 122 ar9340_1p0_mac_postamble);
159 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
160 123
161 /* bb */ 124 /* bb */
162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
163 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 125 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
164 ar9340_1p0_baseband_core, 126 ar9340_1p0_baseband_core);
165 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
166 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 127 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
167 ar9340_1p0_baseband_postamble, 128 ar9340_1p0_baseband_postamble);
168 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
169 129
170 /* radio */ 130 /* radio */
171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
172 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 131 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
173 ar9340_1p0_radio_core, 132 ar9340_1p0_radio_core);
174 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
175 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 133 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
176 ar9340_1p0_radio_postamble, 134 ar9340_1p0_radio_postamble);
177 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
178 135
179 /* soc */ 136 /* soc */
180 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 137 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
181 ar9340_1p0_soc_preamble, 138 ar9340_1p0_soc_preamble);
182 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
183 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
184 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 139 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
185 ar9340_1p0_soc_postamble, 140 ar9340_1p0_soc_postamble);
186 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
187 141
188 /* rx/tx gain */ 142 /* rx/tx gain */
189 INIT_INI_ARRAY(&ah->iniModesRxGain, 143 INIT_INI_ARRAY(&ah->iniModesRxGain,
190 ar9340Common_wo_xlna_rx_gain_table_1p0, 144 ar9340Common_wo_xlna_rx_gain_table_1p0);
191 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
192 5);
193 INIT_INI_ARRAY(&ah->iniModesTxGain, 145 INIT_INI_ARRAY(&ah->iniModesTxGain,
194 ar9340Modes_high_ob_db_tx_gain_table_1p0, 146 ar9340Modes_high_ob_db_tx_gain_table_1p0);
195 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
196 5);
197 147
198 INIT_INI_ARRAY(&ah->iniModesFastClock, 148 INIT_INI_ARRAY(&ah->iniModesFastClock,
199 ar9340Modes_fast_clock_1p0, 149 ar9340Modes_fast_clock_1p0);
200 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
201 3);
202 150
203 if (!ah->is_clk_25mhz) 151 if (!ah->is_clk_25mhz)
204 INIT_INI_ARRAY(&ah->iniAdditional, 152 INIT_INI_ARRAY(&ah->iniAdditional,
205 ar9340_1p0_radio_core_40M, 153 ar9340_1p0_radio_core_40M);
206 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
207 2);
208 } else if (AR_SREV_9485_11(ah)) { 154 } else if (AR_SREV_9485_11(ah)) {
209 /* mac */ 155 /* mac */
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
211 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 156 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
212 ar9485_1_1_mac_core, 157 ar9485_1_1_mac_core);
213 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
214 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 158 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
215 ar9485_1_1_mac_postamble, 159 ar9485_1_1_mac_postamble);
216 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
217 160
218 /* bb */ 161 /* bb */
219 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1, 162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
220 ARRAY_SIZE(ar9485_1_1), 2);
221 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 163 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
222 ar9485_1_1_baseband_core, 164 ar9485_1_1_baseband_core);
223 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
224 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
225 ar9485_1_1_baseband_postamble, 166 ar9485_1_1_baseband_postamble);
226 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
227 167
228 /* radio */ 168 /* radio */
229 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
230 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 169 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
231 ar9485_1_1_radio_core, 170 ar9485_1_1_radio_core);
232 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
233 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
234 ar9485_1_1_radio_postamble, 172 ar9485_1_1_radio_postamble);
235 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
236 173
237 /* soc */ 174 /* soc */
238 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 175 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
239 ar9485_1_1_soc_preamble, 176 ar9485_1_1_soc_preamble);
240 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
241 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
242 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
243 177
244 /* rx/tx gain */ 178 /* rx/tx gain */
245 INIT_INI_ARRAY(&ah->iniModesRxGain, 179 INIT_INI_ARRAY(&ah->iniModesRxGain,
246 ar9485Common_wo_xlna_rx_gain_1_1, 180 ar9485Common_wo_xlna_rx_gain_1_1);
247 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
248 INIT_INI_ARRAY(&ah->iniModesTxGain, 181 INIT_INI_ARRAY(&ah->iniModesTxGain,
249 ar9485_modes_lowest_ob_db_tx_gain_1_1, 182 ar9485_modes_lowest_ob_db_tx_gain_1_1);
250 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
251 5);
252 183
253 /* Load PCIE SERDES settings from INI */ 184 /* Load PCIE SERDES settings from INI */
254 185
255 /* Awake Setting */ 186 /* Awake Setting */
256 187
257 INIT_INI_ARRAY(&ah->iniPcieSerdes, 188 INIT_INI_ARRAY(&ah->iniPcieSerdes,
258 ar9485_1_1_pcie_phy_clkreq_disable_L1, 189 ar9485_1_1_pcie_phy_clkreq_disable_L1);
259 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
260 2);
261 190
262 /* Sleep Setting */ 191 /* Sleep Setting */
263 192
264 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 193 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
265 ar9485_1_1_pcie_phy_clkreq_disable_L1, 194 ar9485_1_1_pcie_phy_clkreq_disable_L1);
266 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
267 2);
268 } else if (AR_SREV_9462_20(ah)) { 195 } else if (AR_SREV_9462_20(ah)) {
269 196
270 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0); 197 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
271 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
272 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
273 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 198 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
274 ar9462_2p0_mac_postamble, 199 ar9462_2p0_mac_postamble);
275 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
276 200
277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
278 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 201 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
279 ar9462_2p0_baseband_core, 202 ar9462_2p0_baseband_core);
280 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
281 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 203 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
282 ar9462_2p0_baseband_postamble, 204 ar9462_2p0_baseband_postamble);
283 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
284 205
285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 206 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
287 ar9462_2p0_radio_core, 207 ar9462_2p0_radio_core);
288 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
289 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 208 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
290 ar9462_2p0_radio_postamble, 209 ar9462_2p0_radio_postamble);
291 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
292 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant, 210 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
293 ar9462_2p0_radio_postamble_sys2ant, 211 ar9462_2p0_radio_postamble_sys2ant);
294 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
295 5);
296 212
297 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 213 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
298 ar9462_2p0_soc_preamble, 214 ar9462_2p0_soc_preamble);
299 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
300 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
301 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 215 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
302 ar9462_2p0_soc_postamble, 216 ar9462_2p0_soc_postamble);
303 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
304 217
305 INIT_INI_ARRAY(&ah->iniModesRxGain, 218 INIT_INI_ARRAY(&ah->iniModesRxGain,
306 ar9462_common_rx_gain_table_2p0, 219 ar9462_common_rx_gain_table_2p0);
307 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
308 220
309 /* Awake -> Sleep Setting */ 221 /* Awake -> Sleep Setting */
310 INIT_INI_ARRAY(&ah->iniPcieSerdes, 222 INIT_INI_ARRAY(&ah->iniPcieSerdes,
311 PCIE_PLL_ON_CREQ_DIS_L1_2P0, 223 PCIE_PLL_ON_CREQ_DIS_L1_2P0);
312 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
313 2);
314 /* Sleep -> Awake Setting */ 224 /* Sleep -> Awake Setting */
315 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 225 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
316 PCIE_PLL_ON_CREQ_DIS_L1_2P0, 226 PCIE_PLL_ON_CREQ_DIS_L1_2P0);
317 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
318 2);
319 227
320 /* Fast clock modal settings */ 228 /* Fast clock modal settings */
321 INIT_INI_ARRAY(&ah->iniModesFastClock, 229 INIT_INI_ARRAY(&ah->iniModesFastClock,
322 ar9462_modes_fast_clock_2p0, 230 ar9462_modes_fast_clock_2p0);
323 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
324 231
325 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, 232 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
326 AR9462_BB_CTX_COEFJ(2p0), 233 AR9462_BB_CTX_COEFJ(2p0));
327 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
328 234
329 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ, 235 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
330 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
331 } else if (AR_SREV_9550(ah)) { 236 } else if (AR_SREV_9550(ah)) {
332 /* mac */ 237 /* mac */
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
334 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 238 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
335 ar955x_1p0_mac_core, 239 ar955x_1p0_mac_core);
336 ARRAY_SIZE(ar955x_1p0_mac_core), 2);
337 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 240 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
338 ar955x_1p0_mac_postamble, 241 ar955x_1p0_mac_postamble);
339 ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
340 242
341 /* bb */ 243 /* bb */
342 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 244 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
344 ar955x_1p0_baseband_core, 245 ar955x_1p0_baseband_core);
345 ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
346 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 246 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
347 ar955x_1p0_baseband_postamble, 247 ar955x_1p0_baseband_postamble);
348 ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
349 248
350 /* radio */ 249 /* radio */
351 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
352 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 250 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
353 ar955x_1p0_radio_core, 251 ar955x_1p0_radio_core);
354 ARRAY_SIZE(ar955x_1p0_radio_core), 2);
355 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 252 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
356 ar955x_1p0_radio_postamble, 253 ar955x_1p0_radio_postamble);
357 ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
358 254
359 /* soc */ 255 /* soc */
360 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 256 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
361 ar955x_1p0_soc_preamble, 257 ar955x_1p0_soc_preamble);
362 ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
363 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
364 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 258 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
365 ar955x_1p0_soc_postamble, 259 ar955x_1p0_soc_postamble);
366 ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
367 260
368 /* rx/tx gain */ 261 /* rx/tx gain */
369 INIT_INI_ARRAY(&ah->iniModesRxGain, 262 INIT_INI_ARRAY(&ah->iniModesRxGain,
370 ar955x_1p0_common_wo_xlna_rx_gain_table, 263 ar955x_1p0_common_wo_xlna_rx_gain_table);
371 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
372 2);
373 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 264 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
374 ar955x_1p0_common_wo_xlna_rx_gain_bounds, 265 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
375 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
376 5);
377 INIT_INI_ARRAY(&ah->iniModesTxGain, 266 INIT_INI_ARRAY(&ah->iniModesTxGain,
378 ar955x_1p0_modes_xpa_tx_gain_table, 267 ar955x_1p0_modes_xpa_tx_gain_table);
379 ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
380 9);
381 268
382 /* Fast clock modal settings */ 269 /* Fast clock modal settings */
383 INIT_INI_ARRAY(&ah->iniModesFastClock, 270 INIT_INI_ARRAY(&ah->iniModesFastClock,
384 ar955x_1p0_modes_fast_clock, 271 ar955x_1p0_modes_fast_clock);
385 ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
386 } else if (AR_SREV_9580(ah)) { 272 } else if (AR_SREV_9580(ah)) {
387 /* mac */ 273 /* mac */
388 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
389 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 274 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
390 ar9580_1p0_mac_core, 275 ar9580_1p0_mac_core);
391 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
392 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 276 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
393 ar9580_1p0_mac_postamble, 277 ar9580_1p0_mac_postamble);
394 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
395 278
396 /* bb */ 279 /* bb */
397 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
398 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 280 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
399 ar9580_1p0_baseband_core, 281 ar9580_1p0_baseband_core);
400 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
401 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 282 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
402 ar9580_1p0_baseband_postamble, 283 ar9580_1p0_baseband_postamble);
403 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
404 284
405 /* radio */ 285 /* radio */
406 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
407 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 286 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
408 ar9580_1p0_radio_core, 287 ar9580_1p0_radio_core);
409 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
410 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 288 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
411 ar9580_1p0_radio_postamble, 289 ar9580_1p0_radio_postamble);
412 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
413 290
414 /* soc */ 291 /* soc */
415 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 292 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
416 ar9580_1p0_soc_preamble, 293 ar9580_1p0_soc_preamble);
417 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
418 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
419 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 294 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
420 ar9580_1p0_soc_postamble, 295 ar9580_1p0_soc_postamble);
421 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
422 296
423 /* rx/tx gain */ 297 /* rx/tx gain */
424 INIT_INI_ARRAY(&ah->iniModesRxGain, 298 INIT_INI_ARRAY(&ah->iniModesRxGain,
425 ar9580_1p0_rx_gain_table, 299 ar9580_1p0_rx_gain_table);
426 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
427 INIT_INI_ARRAY(&ah->iniModesTxGain, 300 INIT_INI_ARRAY(&ah->iniModesTxGain,
428 ar9580_1p0_low_ob_db_tx_gain_table, 301 ar9580_1p0_low_ob_db_tx_gain_table);
429 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
430 5);
431 302
432 INIT_INI_ARRAY(&ah->iniModesFastClock, 303 INIT_INI_ARRAY(&ah->iniModesFastClock,
433 ar9580_1p0_modes_fast_clock, 304 ar9580_1p0_modes_fast_clock);
434 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
435 3);
436 } else { 305 } else {
437 /* mac */ 306 /* mac */
438 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
439 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], 307 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
440 ar9300_2p2_mac_core, 308 ar9300_2p2_mac_core);
441 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
442 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], 309 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
443 ar9300_2p2_mac_postamble, 310 ar9300_2p2_mac_postamble);
444 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
445 311
446 /* bb */ 312 /* bb */
447 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
448 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], 313 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
449 ar9300_2p2_baseband_core, 314 ar9300_2p2_baseband_core);
450 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
451 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], 315 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
452 ar9300_2p2_baseband_postamble, 316 ar9300_2p2_baseband_postamble);
453 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
454 317
455 /* radio */ 318 /* radio */
456 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
457 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], 319 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
458 ar9300_2p2_radio_core, 320 ar9300_2p2_radio_core);
459 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
460 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], 321 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
461 ar9300_2p2_radio_postamble, 322 ar9300_2p2_radio_postamble);
462 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
463 323
464 /* soc */ 324 /* soc */
465 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], 325 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
466 ar9300_2p2_soc_preamble, 326 ar9300_2p2_soc_preamble);
467 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
468 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
469 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], 327 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
470 ar9300_2p2_soc_postamble, 328 ar9300_2p2_soc_postamble);
471 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
472 329
473 /* rx/tx gain */ 330 /* rx/tx gain */
474 INIT_INI_ARRAY(&ah->iniModesRxGain, 331 INIT_INI_ARRAY(&ah->iniModesRxGain,
475 ar9300Common_rx_gain_table_2p2, 332 ar9300Common_rx_gain_table_2p2);
476 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
477 INIT_INI_ARRAY(&ah->iniModesTxGain, 333 INIT_INI_ARRAY(&ah->iniModesTxGain,
478 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 334 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
479 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
480 5);
481 335
482 /* Load PCIE SERDES settings from INI */ 336 /* Load PCIE SERDES settings from INI */
483 337
484 /* Awake Setting */ 338 /* Awake Setting */
485 339
486 INIT_INI_ARRAY(&ah->iniPcieSerdes, 340 INIT_INI_ARRAY(&ah->iniPcieSerdes,
487 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, 341 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
488 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
489 2);
490 342
491 /* Sleep Setting */ 343 /* Sleep Setting */
492 344
493 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower, 345 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
494 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2, 346 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
495 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
496 2);
497 347
498 /* Fast clock modal settings */ 348 /* Fast clock modal settings */
499 INIT_INI_ARRAY(&ah->iniModesFastClock, 349 INIT_INI_ARRAY(&ah->iniModesFastClock,
500 ar9300Modes_fast_clock_2p2, 350 ar9300Modes_fast_clock_2p2);
501 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
502 3);
503 } 351 }
504} 352}
505 353
@@ -507,170 +355,110 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
507{ 355{
508 if (AR_SREV_9330_12(ah)) 356 if (AR_SREV_9330_12(ah))
509 INIT_INI_ARRAY(&ah->iniModesTxGain, 357 INIT_INI_ARRAY(&ah->iniModesTxGain,
510 ar9331_modes_lowest_ob_db_tx_gain_1p2, 358 ar9331_modes_lowest_ob_db_tx_gain_1p2);
511 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
512 5);
513 else if (AR_SREV_9330_11(ah)) 359 else if (AR_SREV_9330_11(ah))
514 INIT_INI_ARRAY(&ah->iniModesTxGain, 360 INIT_INI_ARRAY(&ah->iniModesTxGain,
515 ar9331_modes_lowest_ob_db_tx_gain_1p1, 361 ar9331_modes_lowest_ob_db_tx_gain_1p1);
516 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
517 5);
518 else if (AR_SREV_9340(ah)) 362 else if (AR_SREV_9340(ah))
519 INIT_INI_ARRAY(&ah->iniModesTxGain, 363 INIT_INI_ARRAY(&ah->iniModesTxGain,
520 ar9340Modes_lowest_ob_db_tx_gain_table_1p0, 364 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
521 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
522 5);
523 else if (AR_SREV_9485_11(ah)) 365 else if (AR_SREV_9485_11(ah))
524 INIT_INI_ARRAY(&ah->iniModesTxGain, 366 INIT_INI_ARRAY(&ah->iniModesTxGain,
525 ar9485_modes_lowest_ob_db_tx_gain_1_1, 367 ar9485_modes_lowest_ob_db_tx_gain_1_1);
526 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
527 5);
528 else if (AR_SREV_9550(ah)) 368 else if (AR_SREV_9550(ah))
529 INIT_INI_ARRAY(&ah->iniModesTxGain, 369 INIT_INI_ARRAY(&ah->iniModesTxGain,
530 ar955x_1p0_modes_xpa_tx_gain_table, 370 ar955x_1p0_modes_xpa_tx_gain_table);
531 ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
532 9);
533 else if (AR_SREV_9580(ah)) 371 else if (AR_SREV_9580(ah))
534 INIT_INI_ARRAY(&ah->iniModesTxGain, 372 INIT_INI_ARRAY(&ah->iniModesTxGain,
535 ar9580_1p0_lowest_ob_db_tx_gain_table, 373 ar9580_1p0_lowest_ob_db_tx_gain_table);
536 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
537 5);
538 else if (AR_SREV_9462_20(ah)) 374 else if (AR_SREV_9462_20(ah))
539 INIT_INI_ARRAY(&ah->iniModesTxGain, 375 INIT_INI_ARRAY(&ah->iniModesTxGain,
540 ar9462_modes_low_ob_db_tx_gain_table_2p0, 376 ar9462_modes_low_ob_db_tx_gain_table_2p0);
541 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
542 5);
543 else 377 else
544 INIT_INI_ARRAY(&ah->iniModesTxGain, 378 INIT_INI_ARRAY(&ah->iniModesTxGain,
545 ar9300Modes_lowest_ob_db_tx_gain_table_2p2, 379 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
546 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
547 5);
548} 380}
549 381
550static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) 382static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
551{ 383{
552 if (AR_SREV_9330_12(ah)) 384 if (AR_SREV_9330_12(ah))
553 INIT_INI_ARRAY(&ah->iniModesTxGain, 385 INIT_INI_ARRAY(&ah->iniModesTxGain,
554 ar9331_modes_high_ob_db_tx_gain_1p2, 386 ar9331_modes_high_ob_db_tx_gain_1p2);
555 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
556 5);
557 else if (AR_SREV_9330_11(ah)) 387 else if (AR_SREV_9330_11(ah))
558 INIT_INI_ARRAY(&ah->iniModesTxGain, 388 INIT_INI_ARRAY(&ah->iniModesTxGain,
559 ar9331_modes_high_ob_db_tx_gain_1p1, 389 ar9331_modes_high_ob_db_tx_gain_1p1);
560 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
561 5);
562 else if (AR_SREV_9340(ah)) 390 else if (AR_SREV_9340(ah))
563 INIT_INI_ARRAY(&ah->iniModesTxGain, 391 INIT_INI_ARRAY(&ah->iniModesTxGain,
564 ar9340Modes_high_ob_db_tx_gain_table_1p0, 392 ar9340Modes_high_ob_db_tx_gain_table_1p0);
565 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
566 5);
567 else if (AR_SREV_9485_11(ah)) 393 else if (AR_SREV_9485_11(ah))
568 INIT_INI_ARRAY(&ah->iniModesTxGain, 394 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9485Modes_high_ob_db_tx_gain_1_1, 395 ar9485Modes_high_ob_db_tx_gain_1_1);
570 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
571 5);
572 else if (AR_SREV_9580(ah)) 396 else if (AR_SREV_9580(ah))
573 INIT_INI_ARRAY(&ah->iniModesTxGain, 397 INIT_INI_ARRAY(&ah->iniModesTxGain,
574 ar9580_1p0_high_ob_db_tx_gain_table, 398 ar9580_1p0_high_ob_db_tx_gain_table);
575 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
576 5);
577 else if (AR_SREV_9550(ah)) 399 else if (AR_SREV_9550(ah))
578 INIT_INI_ARRAY(&ah->iniModesTxGain, 400 INIT_INI_ARRAY(&ah->iniModesTxGain,
579 ar955x_1p0_modes_no_xpa_tx_gain_table, 401 ar955x_1p0_modes_no_xpa_tx_gain_table);
580 ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
581 9);
582 else if (AR_SREV_9462_20(ah)) 402 else if (AR_SREV_9462_20(ah))
583 INIT_INI_ARRAY(&ah->iniModesTxGain, 403 INIT_INI_ARRAY(&ah->iniModesTxGain,
584 ar9462_modes_high_ob_db_tx_gain_table_2p0, 404 ar9462_modes_high_ob_db_tx_gain_table_2p0);
585 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
586 5);
587 else 405 else
588 INIT_INI_ARRAY(&ah->iniModesTxGain, 406 INIT_INI_ARRAY(&ah->iniModesTxGain,
589 ar9300Modes_high_ob_db_tx_gain_table_2p2, 407 ar9300Modes_high_ob_db_tx_gain_table_2p2);
590 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
591 5);
592} 408}
593 409
594static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) 410static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
595{ 411{
596 if (AR_SREV_9330_12(ah)) 412 if (AR_SREV_9330_12(ah))
597 INIT_INI_ARRAY(&ah->iniModesTxGain, 413 INIT_INI_ARRAY(&ah->iniModesTxGain,
598 ar9331_modes_low_ob_db_tx_gain_1p2, 414 ar9331_modes_low_ob_db_tx_gain_1p2);
599 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
600 5);
601 else if (AR_SREV_9330_11(ah)) 415 else if (AR_SREV_9330_11(ah))
602 INIT_INI_ARRAY(&ah->iniModesTxGain, 416 INIT_INI_ARRAY(&ah->iniModesTxGain,
603 ar9331_modes_low_ob_db_tx_gain_1p1, 417 ar9331_modes_low_ob_db_tx_gain_1p1);
604 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
605 5);
606 else if (AR_SREV_9340(ah)) 418 else if (AR_SREV_9340(ah))
607 INIT_INI_ARRAY(&ah->iniModesTxGain, 419 INIT_INI_ARRAY(&ah->iniModesTxGain,
608 ar9340Modes_low_ob_db_tx_gain_table_1p0, 420 ar9340Modes_low_ob_db_tx_gain_table_1p0);
609 ARRAY_SIZE(ar9340Modes_low_ob_db_tx_gain_table_1p0),
610 5);
611 else if (AR_SREV_9485_11(ah)) 421 else if (AR_SREV_9485_11(ah))
612 INIT_INI_ARRAY(&ah->iniModesTxGain, 422 INIT_INI_ARRAY(&ah->iniModesTxGain,
613 ar9485Modes_low_ob_db_tx_gain_1_1, 423 ar9485Modes_low_ob_db_tx_gain_1_1);
614 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
615 5);
616 else if (AR_SREV_9580(ah)) 424 else if (AR_SREV_9580(ah))
617 INIT_INI_ARRAY(&ah->iniModesTxGain, 425 INIT_INI_ARRAY(&ah->iniModesTxGain,
618 ar9580_1p0_low_ob_db_tx_gain_table, 426 ar9580_1p0_low_ob_db_tx_gain_table);
619 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
620 5);
621 else 427 else
622 INIT_INI_ARRAY(&ah->iniModesTxGain, 428 INIT_INI_ARRAY(&ah->iniModesTxGain,
623 ar9300Modes_low_ob_db_tx_gain_table_2p2, 429 ar9300Modes_low_ob_db_tx_gain_table_2p2);
624 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
625 5);
626} 430}
627 431
628static void ar9003_tx_gain_table_mode3(struct ath_hw *ah) 432static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
629{ 433{
630 if (AR_SREV_9330_12(ah)) 434 if (AR_SREV_9330_12(ah))
631 INIT_INI_ARRAY(&ah->iniModesTxGain, 435 INIT_INI_ARRAY(&ah->iniModesTxGain,
632 ar9331_modes_high_power_tx_gain_1p2, 436 ar9331_modes_high_power_tx_gain_1p2);
633 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
634 5);
635 else if (AR_SREV_9330_11(ah)) 437 else if (AR_SREV_9330_11(ah))
636 INIT_INI_ARRAY(&ah->iniModesTxGain, 438 INIT_INI_ARRAY(&ah->iniModesTxGain,
637 ar9331_modes_high_power_tx_gain_1p1, 439 ar9331_modes_high_power_tx_gain_1p1);
638 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
639 5);
640 else if (AR_SREV_9340(ah)) 440 else if (AR_SREV_9340(ah))
641 INIT_INI_ARRAY(&ah->iniModesTxGain, 441 INIT_INI_ARRAY(&ah->iniModesTxGain,
642 ar9340Modes_high_power_tx_gain_table_1p0, 442 ar9340Modes_high_power_tx_gain_table_1p0);
643 ARRAY_SIZE(ar9340Modes_high_power_tx_gain_table_1p0),
644 5);
645 else if (AR_SREV_9485_11(ah)) 443 else if (AR_SREV_9485_11(ah))
646 INIT_INI_ARRAY(&ah->iniModesTxGain, 444 INIT_INI_ARRAY(&ah->iniModesTxGain,
647 ar9485Modes_high_power_tx_gain_1_1, 445 ar9485Modes_high_power_tx_gain_1_1);
648 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
649 5);
650 else if (AR_SREV_9580(ah)) 446 else if (AR_SREV_9580(ah))
651 INIT_INI_ARRAY(&ah->iniModesTxGain, 447 INIT_INI_ARRAY(&ah->iniModesTxGain,
652 ar9580_1p0_high_power_tx_gain_table, 448 ar9580_1p0_high_power_tx_gain_table);
653 ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
654 5);
655 else 449 else
656 INIT_INI_ARRAY(&ah->iniModesTxGain, 450 INIT_INI_ARRAY(&ah->iniModesTxGain,
657 ar9300Modes_high_power_tx_gain_table_2p2, 451 ar9300Modes_high_power_tx_gain_table_2p2);
658 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
659 5);
660} 452}
661 453
662static void ar9003_tx_gain_table_mode4(struct ath_hw *ah) 454static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
663{ 455{
664 if (AR_SREV_9340(ah)) 456 if (AR_SREV_9340(ah))
665 INIT_INI_ARRAY(&ah->iniModesTxGain, 457 INIT_INI_ARRAY(&ah->iniModesTxGain,
666 ar9340Modes_mixed_ob_db_tx_gain_table_1p0, 458 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
667 ARRAY_SIZE(ar9340Modes_mixed_ob_db_tx_gain_table_1p0),
668 5);
669 else if (AR_SREV_9580(ah)) 459 else if (AR_SREV_9580(ah))
670 INIT_INI_ARRAY(&ah->iniModesTxGain, 460 INIT_INI_ARRAY(&ah->iniModesTxGain,
671 ar9580_1p0_mixed_ob_db_tx_gain_table, 461 ar9580_1p0_mixed_ob_db_tx_gain_table);
672 ARRAY_SIZE(ar9580_1p0_mixed_ob_db_tx_gain_table),
673 5);
674} 462}
675 463
676static void ar9003_tx_gain_table_apply(struct ath_hw *ah) 464static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
@@ -699,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
699{ 487{
700 if (AR_SREV_9330_12(ah)) 488 if (AR_SREV_9330_12(ah))
701 INIT_INI_ARRAY(&ah->iniModesRxGain, 489 INIT_INI_ARRAY(&ah->iniModesRxGain,
702 ar9331_common_rx_gain_1p2, 490 ar9331_common_rx_gain_1p2);
703 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
704 2);
705 else if (AR_SREV_9330_11(ah)) 491 else if (AR_SREV_9330_11(ah))
706 INIT_INI_ARRAY(&ah->iniModesRxGain, 492 INIT_INI_ARRAY(&ah->iniModesRxGain,
707 ar9331_common_rx_gain_1p1, 493 ar9331_common_rx_gain_1p1);
708 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
709 2);
710 else if (AR_SREV_9340(ah)) 494 else if (AR_SREV_9340(ah))
711 INIT_INI_ARRAY(&ah->iniModesRxGain, 495 INIT_INI_ARRAY(&ah->iniModesRxGain,
712 ar9340Common_rx_gain_table_1p0, 496 ar9340Common_rx_gain_table_1p0);
713 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
714 2);
715 else if (AR_SREV_9485_11(ah)) 497 else if (AR_SREV_9485_11(ah))
716 INIT_INI_ARRAY(&ah->iniModesRxGain, 498 INIT_INI_ARRAY(&ah->iniModesRxGain,
717 ar9485Common_wo_xlna_rx_gain_1_1, 499 ar9485Common_wo_xlna_rx_gain_1_1);
718 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
719 2);
720 else if (AR_SREV_9550(ah)) { 500 else if (AR_SREV_9550(ah)) {
721 INIT_INI_ARRAY(&ah->iniModesRxGain, 501 INIT_INI_ARRAY(&ah->iniModesRxGain,
722 ar955x_1p0_common_rx_gain_table, 502 ar955x_1p0_common_rx_gain_table);
723 ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
724 2);
725 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 503 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
726 ar955x_1p0_common_rx_gain_bounds, 504 ar955x_1p0_common_rx_gain_bounds);
727 ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
728 5);
729 } else if (AR_SREV_9580(ah)) 505 } else if (AR_SREV_9580(ah))
730 INIT_INI_ARRAY(&ah->iniModesRxGain, 506 INIT_INI_ARRAY(&ah->iniModesRxGain,
731 ar9580_1p0_rx_gain_table, 507 ar9580_1p0_rx_gain_table);
732 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
733 2);
734 else if (AR_SREV_9462_20(ah)) 508 else if (AR_SREV_9462_20(ah))
735 INIT_INI_ARRAY(&ah->iniModesRxGain, 509 INIT_INI_ARRAY(&ah->iniModesRxGain,
736 ar9462_common_rx_gain_table_2p0, 510 ar9462_common_rx_gain_table_2p0);
737 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
738 2);
739 else 511 else
740 INIT_INI_ARRAY(&ah->iniModesRxGain, 512 INIT_INI_ARRAY(&ah->iniModesRxGain,
741 ar9300Common_rx_gain_table_2p2, 513 ar9300Common_rx_gain_table_2p2);
742 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
743 2);
744} 514}
745 515
746static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) 516static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
747{ 517{
748 if (AR_SREV_9330_12(ah)) 518 if (AR_SREV_9330_12(ah))
749 INIT_INI_ARRAY(&ah->iniModesRxGain, 519 INIT_INI_ARRAY(&ah->iniModesRxGain,
750 ar9331_common_wo_xlna_rx_gain_1p2, 520 ar9331_common_wo_xlna_rx_gain_1p2);
751 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
752 2);
753 else if (AR_SREV_9330_11(ah)) 521 else if (AR_SREV_9330_11(ah))
754 INIT_INI_ARRAY(&ah->iniModesRxGain, 522 INIT_INI_ARRAY(&ah->iniModesRxGain,
755 ar9331_common_wo_xlna_rx_gain_1p1, 523 ar9331_common_wo_xlna_rx_gain_1p1);
756 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
757 2);
758 else if (AR_SREV_9340(ah)) 524 else if (AR_SREV_9340(ah))
759 INIT_INI_ARRAY(&ah->iniModesRxGain, 525 INIT_INI_ARRAY(&ah->iniModesRxGain,
760 ar9340Common_wo_xlna_rx_gain_table_1p0, 526 ar9340Common_wo_xlna_rx_gain_table_1p0);
761 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
762 2);
763 else if (AR_SREV_9485_11(ah)) 527 else if (AR_SREV_9485_11(ah))
764 INIT_INI_ARRAY(&ah->iniModesRxGain, 528 INIT_INI_ARRAY(&ah->iniModesRxGain,
765 ar9485Common_wo_xlna_rx_gain_1_1, 529 ar9485Common_wo_xlna_rx_gain_1_1);
766 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
767 2);
768 else if (AR_SREV_9462_20(ah)) 530 else if (AR_SREV_9462_20(ah))
769 INIT_INI_ARRAY(&ah->iniModesRxGain, 531 INIT_INI_ARRAY(&ah->iniModesRxGain,
770 ar9462_common_wo_xlna_rx_gain_table_2p0, 532 ar9462_common_wo_xlna_rx_gain_table_2p0);
771 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
772 2);
773 else if (AR_SREV_9550(ah)) { 533 else if (AR_SREV_9550(ah)) {
774 INIT_INI_ARRAY(&ah->iniModesRxGain, 534 INIT_INI_ARRAY(&ah->iniModesRxGain,
775 ar955x_1p0_common_wo_xlna_rx_gain_table, 535 ar955x_1p0_common_wo_xlna_rx_gain_table);
776 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
777 2);
778 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, 536 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
779 ar955x_1p0_common_wo_xlna_rx_gain_bounds, 537 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
780 ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
781 5);
782 } else if (AR_SREV_9580(ah)) 538 } else if (AR_SREV_9580(ah))
783 INIT_INI_ARRAY(&ah->iniModesRxGain, 539 INIT_INI_ARRAY(&ah->iniModesRxGain,
784 ar9580_1p0_wo_xlna_rx_gain_table, 540 ar9580_1p0_wo_xlna_rx_gain_table);
785 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
786 2);
787 else 541 else
788 INIT_INI_ARRAY(&ah->iniModesRxGain, 542 INIT_INI_ARRAY(&ah->iniModesRxGain,
789 ar9300Common_wo_xlna_rx_gain_table_2p2, 543 ar9300Common_wo_xlna_rx_gain_table_2p2);
790 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
791 2);
792} 544}
793 545
794static void ar9003_rx_gain_table_mode2(struct ath_hw *ah) 546static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
795{ 547{
796 if (AR_SREV_9462_20(ah)) 548 if (AR_SREV_9462_20(ah))
797 INIT_INI_ARRAY(&ah->iniModesRxGain, 549 INIT_INI_ARRAY(&ah->iniModesRxGain,
798 ar9462_common_mixed_rx_gain_table_2p0, 550 ar9462_common_mixed_rx_gain_table_2p0);
799 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
800} 551}
801 552
802static void ar9003_rx_gain_table_apply(struct ath_hw *ah) 553static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/calib.h b/drivers/net/wireless/ath/ath9k/calib.h
index 3b33996d97df..1060c19a5012 100644
--- a/drivers/net/wireless/ath/ath9k/calib.h
+++ b/drivers/net/wireless/ath/ath9k/calib.h
@@ -30,10 +30,10 @@ struct ar5416IniArray {
30 u32 ia_columns; 30 u32 ia_columns;
31}; 31};
32 32
33#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \ 33#define INIT_INI_ARRAY(iniarray, array) do { \
34 (iniarray)->ia_array = (u32 *)(array); \ 34 (iniarray)->ia_array = (u32 *)(array); \
35 (iniarray)->ia_rows = (rows); \ 35 (iniarray)->ia_rows = ARRAY_SIZE(array); \
36 (iniarray)->ia_columns = (columns); \ 36 (iniarray)->ia_columns = ARRAY_SIZE(array[0]); \
37 } while (0) 37 } while (0)
38 38
39#define INI_RA(iniarray, row, column) \ 39#define INI_RA(iniarray, row, column) \
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 23:55:07 -0500