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authorJoshua Kinard <kumba@gentoo.org>2015-01-19 04:19:20 -0500
committerRalf Baechle <ralf@linux-mips.org>2015-04-01 11:22:16 -0400
commita2e50f53d535fa885a432fb9fc3e3ca5ed97364c (patch)
treecf6bdd8cc6d54b2760484f37558220ea5ad30b8c
parent3db2742554bb7cc077de478c2ebf9c1efdd317f5 (diff)
MIPS: PCI: Add a hook for IORESOURCE_BUS in pci_controller/bridge_controller
On SGI Origin 2k/Onyx2 and SGI Octane systems, there can exist multiple PCI buses attached to the Xtalk bus. The current code will stop counting PCI buses after it finds the first one. If one installs the optional PCI cardcage ("shoebox") into these systems, because of the order of the Xtalk widgets, the current PCI code will find the cardcage first, and fail to detect the BaseIO PCI devices, which are on a higher Xtalk widget ID. This patch adds the hooks needed for resolving this issue in the IP27 PCI code (in a later patch). Verified on both an SGI Onyx2 and an SGI Octane. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Cc: Linux MIPS List <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/9074/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/asm/pci.h2
-rw-r--r--arch/mips/include/asm/pci/bridge.h1
-rw-r--r--arch/mips/pci/pci.c5
3 files changed, 7 insertions, 1 deletions
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index 193b4c6b7541..d9692993fc83 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -35,6 +35,8 @@ struct pci_controller {
35 struct resource *io_resource; 35 struct resource *io_resource;
36 unsigned long io_offset; 36 unsigned long io_offset;
37 unsigned long io_map_base; 37 unsigned long io_map_base;
38 struct resource *busn_resource;
39 unsigned long busn_offset;
38 40
39 unsigned int index; 41 unsigned int index;
40 /* For compatibility with current (as of July 2003) pciutils 42 /* For compatibility with current (as of July 2003) pciutils
diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index af2c8a351ca7..8d7a63b52ac7 100644
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -835,6 +835,7 @@ struct bridge_controller {
835 struct pci_controller pc; 835 struct pci_controller pc;
836 struct resource mem; 836 struct resource mem;
837 struct resource io; 837 struct resource io;
838 struct resource busn;
838 bridge_t *base; 839 bridge_t *base;
839 nasid_t nasid; 840 nasid_t nasid;
840 unsigned int widget_id; 841 unsigned int widget_id;
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 1bf60b127377..0e3f437e8cad 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -91,7 +91,10 @@ static void pcibios_scanbus(struct pci_controller *hose)
91 91
92 pci_add_resource_offset(&resources, 92 pci_add_resource_offset(&resources,
93 hose->mem_resource, hose->mem_offset); 93 hose->mem_resource, hose->mem_offset);
94 pci_add_resource_offset(&resources, hose->io_resource, hose->io_offset); 94 pci_add_resource_offset(&resources,
95 hose->io_resource, hose->io_offset);
96 pci_add_resource_offset(&resources,
97 hose->busn_resource, hose->busn_offset);
95 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose, 98 bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
96 &resources); 99 &resources);
97 if (!bus) 100 if (!bus)