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authorJayachandran C <jchandra@broadcom.com>2013-08-21 10:01:29 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-09-03 17:22:18 -0400
commita2ba6cd6e65bf96059632ed2fe48a7a0f5aea472 (patch)
treee6a04a3eed22d430ebcb84b6f0d68164211b8bab
parent2c4f1ac5623750e715ae2a5fc7e0569999b9bfc5 (diff)
MIPS: Netlogic: Read memory from DRAM BARs
Read the memory from the Bridge DRAM BARs, if it is not passed in from the device tree. This will allow us to remove memory configuration from built in device trees. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5743/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/bridge.h4
-rw-r--r--arch/mips/include/asm/netlogic/xlp-hal/xlp.h3
-rw-r--r--arch/mips/netlogic/xlp/nlm_hal.c35
-rw-r--r--arch/mips/netlogic/xlp/setup.c23
4 files changed, 65 insertions, 0 deletions
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index 790f0f1e55c6..4e8eacb9588a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -88,6 +88,7 @@
88#define BRIDGE_DRAM_LIMIT6 0x22 88#define BRIDGE_DRAM_LIMIT6 0x22
89#define BRIDGE_DRAM_LIMIT7 0x23 89#define BRIDGE_DRAM_LIMIT7 0x23
90 90
91#define BRIDGE_DRAM_NODE_TRANSLN(i) (0x24 + (i))
91#define BRIDGE_DRAM_NODE_TRANSLN0 0x24 92#define BRIDGE_DRAM_NODE_TRANSLN0 0x24
92#define BRIDGE_DRAM_NODE_TRANSLN1 0x25 93#define BRIDGE_DRAM_NODE_TRANSLN1 0x25
93#define BRIDGE_DRAM_NODE_TRANSLN2 0x26 94#define BRIDGE_DRAM_NODE_TRANSLN2 0x26
@@ -96,6 +97,8 @@
96#define BRIDGE_DRAM_NODE_TRANSLN5 0x29 97#define BRIDGE_DRAM_NODE_TRANSLN5 0x29
97#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a 98#define BRIDGE_DRAM_NODE_TRANSLN6 0x2a
98#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b 99#define BRIDGE_DRAM_NODE_TRANSLN7 0x2b
100
101#define BRIDGE_DRAM_CHNL_TRANSLN(i) (0x2c + (i))
99#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c 102#define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c
100#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d 103#define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d
101#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e 104#define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e
@@ -104,6 +107,7 @@
104#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 107#define BRIDGE_DRAM_CHNL_TRANSLN5 0x31
105#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 108#define BRIDGE_DRAM_CHNL_TRANSLN6 0x32
106#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 109#define BRIDGE_DRAM_CHNL_TRANSLN7 0x33
110
107#define BRIDGE_PCIEMEM_BASE0 0x34 111#define BRIDGE_PCIEMEM_BASE0 0x34
108#define BRIDGE_PCIEMEM_BASE1 0x35 112#define BRIDGE_PCIEMEM_BASE1 0x35
109#define BRIDGE_PCIEMEM_BASE2 0x36 113#define BRIDGE_PCIEMEM_BASE2 0x36
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index f4ea0f7f3965..d59cdd69496b 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -59,6 +59,9 @@ void xlp_wakeup_secondary_cpus(void);
59 59
60void xlp_mmu_init(void); 60void xlp_mmu_init(void);
61void nlm_hal_init(void); 61void nlm_hal_init(void);
62int xlp_get_dram_map(int n, uint64_t *dram_map);
63
64/* Device tree related */
62void *xlp_dt_init(void *fdtp); 65void *xlp_dt_init(void *fdtp);
63 66
64#endif /* !__ASSEMBLY__ */ 67#endif /* !__ASSEMBLY__ */
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 87560e4db35f..6f2c21008ddb 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -44,6 +44,7 @@
44#include <asm/netlogic/haldefs.h> 44#include <asm/netlogic/haldefs.h>
45#include <asm/netlogic/xlp-hal/iomap.h> 45#include <asm/netlogic/xlp-hal/iomap.h>
46#include <asm/netlogic/xlp-hal/xlp.h> 46#include <asm/netlogic/xlp-hal/xlp.h>
47#include <asm/netlogic/xlp-hal/bridge.h>
47#include <asm/netlogic/xlp-hal/pic.h> 48#include <asm/netlogic/xlp-hal/pic.h>
48#include <asm/netlogic/xlp-hal/sys.h> 49#include <asm/netlogic/xlp-hal/sys.h>
49 50
@@ -142,3 +143,37 @@ unsigned int nlm_get_cpu_frequency(void)
142{ 143{
143 return nlm_get_core_frequency(0, 0); 144 return nlm_get_core_frequency(0, 0);
144} 145}
146
147/*
148 * Fills upto 8 pairs of entries containing the DRAM map of a node
149 * if n < 0, get dram map for all nodes
150 */
151int xlp_get_dram_map(int n, uint64_t *dram_map)
152{
153 uint64_t bridgebase, base, lim;
154 uint32_t val;
155 int i, node, rv;
156
157 /* Look only at mapping on Node 0, we don't handle crazy configs */
158 bridgebase = nlm_get_bridge_regbase(0);
159 rv = 0;
160 for (i = 0; i < 8; i++) {
161 val = nlm_read_bridge_reg(bridgebase,
162 BRIDGE_DRAM_NODE_TRANSLN(i));
163 node = (val >> 1) & 0x3;
164 if (n >= 0 && n != node)
165 continue;
166 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
167 val = (val >> 12) & 0xfffff;
168 base = (uint64_t) val << 20;
169 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
170 val = (val >> 12) & 0xfffff;
171 if (val == 0) /* BAR not used */
172 continue;
173 lim = ((uint64_t)val + 1) << 20;
174 dram_map[rv] = base;
175 dram_map[rv + 1] = lim;
176 rv += 2;
177 }
178 return rv;
179}
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index 7b638f7be491..7718368e4598 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -73,6 +73,23 @@ static void nlm_fixup_mem(void)
73 } 73 }
74} 74}
75 75
76static void __init xlp_init_mem_from_bars(void)
77{
78 uint64_t map[16];
79 int i, n;
80
81 n = xlp_get_dram_map(-1, map); /* -1: info for all nodes */
82 for (i = 0; i < n; i += 2) {
83 /* exclude 0x1000_0000-0x2000_0000, u-boot device */
84 if (map[i] <= 0x10000000 && map[i+1] > 0x10000000)
85 map[i+1] = 0x10000000;
86 if (map[i] > 0x10000000 && map[i] < 0x20000000)
87 map[i] = 0x20000000;
88
89 add_memory_region(map[i], map[i+1] - map[i], BOOT_MEM_RAM);
90 }
91}
92
76void __init plat_mem_setup(void) 93void __init plat_mem_setup(void)
77{ 94{
78 panic_timeout = 5; 95 panic_timeout = 5;
@@ -82,6 +99,12 @@ void __init plat_mem_setup(void)
82 99
83 /* memory and bootargs from DT */ 100 /* memory and bootargs from DT */
84 early_init_devtree(initial_boot_params); 101 early_init_devtree(initial_boot_params);
102
103 if (boot_mem_map.nr_map == 0) {
104 pr_info("Using DRAM BARs for memory map.\n");
105 xlp_init_mem_from_bars();
106 }
107 /* Calculate and setup wired entries for mapped kernel */
85 nlm_fixup_mem(); 108 nlm_fixup_mem();
86} 109}
87 110