ASoC: tlv320aic3x: add input clock selection

This patch adds input selection of main codec clock - from what pin.
Both registers set same value since codec uses clock divider or pll at one time.

Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

2 files changed, 14 insertions, 0 deletions

diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index 0d2f8c44999d..b94f81ffed34 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -1002,6 +1002,12 @@ static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
         struct snd_soc_codec *codec = codec_dai->codec;
         struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
 
+        /* set clock on MCLK or GPIO2 or BCLK */
+        snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
+                                clk_id << PLLCLK_IN_SHIFT);
+        snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
+                                clk_id << CLKDIV_IN_SHIFT);
+
         aic3x->sysclk = freq;
         return 0;
 }
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 5da5eb3f4cc0..149338b254f6 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -195,6 +195,14 @@
 #define PLL_CLKIN_SHIFT         4
 #define MCLK_SOURCE             0x0
 #define PLL_CLKDIV_SHIFT        0
+#define PLLCLK_IN_MASK          0x30
+#define PLLCLK_IN_SHIFT         4
+#define CLKDIV_IN_MASK          0xc0
+#define CLKDIV_IN_SHIFT         6
+/* clock in source */
+#define CLKIN_MCLK              0
+#define CLKIN_GPIO2             1
+#define CLKIN_BCLK              2
 
 /* Software reset register bits */
 #define SOFT_RESET              0x80