aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorHiroshi Doyu <hdoyu@nvidia.com>2013-05-22 12:45:36 -0400
committerStephen Warren <swarren@nvidia.com>2013-05-28 18:13:51 -0400
commita1c85860e29d600f36363ffb16bdcb643a0336dc (patch)
tree458b0171783daae38af6b4fd75ac27c767443086
parent05849c9381354be4bd4a2a878b5ecb12d375a1a0 (diff)
ARM: tegra114: convert device tree files to use CLK defines
Use the Tegra114 CAR binding header (tegra114-car.h) to replace magic numbers in the device tree. For example, - clocks = <&tegra_car 28>; + clocks = <&tegra_car CLK_HOST1X>; Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> [swarren, updated since tegra20-car.h moved for consistency] Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi51
1 files changed, 26 insertions, 25 deletions
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index c376a12cfc03..289c8a28c210 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,3 +1,4 @@
1#include <dt-bindings/clock/tegra114-car.h>
1#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
2#include <dt-bindings/interrupt-controller/arm-gic.h> 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3 4
@@ -35,7 +36,7 @@
35 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 38 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
38 clocks = <&tegra_car 5>; 39 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
39 }; 40 };
40 41
41 tegra_car: clock { 42 tegra_car: clock {
@@ -79,7 +80,7 @@
79 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
82 clocks = <&tegra_car 34>; 83 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
83 }; 84 };
84 85
85 ahb: ahb { 86 ahb: ahb {
@@ -125,7 +126,7 @@
125 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 126 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
126 nvidia,dma-request-selector = <&apbdma 8>; 127 nvidia,dma-request-selector = <&apbdma 8>;
127 status = "disabled"; 128 status = "disabled";
128 clocks = <&tegra_car 6>; 129 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
129 }; 130 };
130 131
131 uartb: serial@70006040 { 132 uartb: serial@70006040 {
@@ -135,7 +136,7 @@
135 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 136 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
136 nvidia,dma-request-selector = <&apbdma 9>; 137 nvidia,dma-request-selector = <&apbdma 9>;
137 status = "disabled"; 138 status = "disabled";
138 clocks = <&tegra_car 192>; 139 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
139 }; 140 };
140 141
141 uartc: serial@70006200 { 142 uartc: serial@70006200 {
@@ -145,7 +146,7 @@
145 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
146 nvidia,dma-request-selector = <&apbdma 10>; 147 nvidia,dma-request-selector = <&apbdma 10>;
147 status = "disabled"; 148 status = "disabled";
148 clocks = <&tegra_car 55>; 149 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
149 }; 150 };
150 151
151 uartd: serial@70006300 { 152 uartd: serial@70006300 {
@@ -155,14 +156,14 @@
155 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 156 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
156 nvidia,dma-request-selector = <&apbdma 19>; 157 nvidia,dma-request-selector = <&apbdma 19>;
157 status = "disabled"; 158 status = "disabled";
158 clocks = <&tegra_car 65>; 159 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
159 }; 160 };
160 161
161 pwm: pwm { 162 pwm: pwm {
162 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 163 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
163 reg = <0x7000a000 0x100>; 164 reg = <0x7000a000 0x100>;
164 #pwm-cells = <2>; 165 #pwm-cells = <2>;
165 clocks = <&tegra_car 17>; 166 clocks = <&tegra_car TEGRA114_CLK_PWM>;
166 status = "disabled"; 167 status = "disabled";
167 }; 168 };
168 169
@@ -172,7 +173,7 @@
172 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 173 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
173 #address-cells = <1>; 174 #address-cells = <1>;
174 #size-cells = <0>; 175 #size-cells = <0>;
175 clocks = <&tegra_car 12>; 176 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
176 clock-names = "div-clk"; 177 clock-names = "div-clk";
177 status = "disabled"; 178 status = "disabled";
178 }; 179 };
@@ -183,7 +184,7 @@
183 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 184 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
184 #address-cells = <1>; 185 #address-cells = <1>;
185 #size-cells = <0>; 186 #size-cells = <0>;
186 clocks = <&tegra_car 54>; 187 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
187 clock-names = "div-clk"; 188 clock-names = "div-clk";
188 status = "disabled"; 189 status = "disabled";
189 }; 190 };
@@ -194,7 +195,7 @@
194 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
195 #address-cells = <1>; 196 #address-cells = <1>;
196 #size-cells = <0>; 197 #size-cells = <0>;
197 clocks = <&tegra_car 67>; 198 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
198 clock-names = "div-clk"; 199 clock-names = "div-clk";
199 status = "disabled"; 200 status = "disabled";
200 }; 201 };
@@ -205,7 +206,7 @@
205 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 206 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
206 #address-cells = <1>; 207 #address-cells = <1>;
207 #size-cells = <0>; 208 #size-cells = <0>;
208 clocks = <&tegra_car 103>; 209 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
209 clock-names = "div-clk"; 210 clock-names = "div-clk";
210 status = "disabled"; 211 status = "disabled";
211 }; 212 };
@@ -216,7 +217,7 @@
216 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 217 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
217 #address-cells = <1>; 218 #address-cells = <1>;
218 #size-cells = <0>; 219 #size-cells = <0>;
219 clocks = <&tegra_car 47>; 220 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
220 clock-names = "div-clk"; 221 clock-names = "div-clk";
221 status = "disabled"; 222 status = "disabled";
222 }; 223 };
@@ -228,7 +229,7 @@
228 nvidia,dma-request-selector = <&apbdma 15>; 229 nvidia,dma-request-selector = <&apbdma 15>;
229 #address-cells = <1>; 230 #address-cells = <1>;
230 #size-cells = <0>; 231 #size-cells = <0>;
231 clocks = <&tegra_car 41>; 232 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
232 clock-names = "spi"; 233 clock-names = "spi";
233 status = "disabled"; 234 status = "disabled";
234 }; 235 };
@@ -240,7 +241,7 @@
240 nvidia,dma-request-selector = <&apbdma 16>; 241 nvidia,dma-request-selector = <&apbdma 16>;
241 #address-cells = <1>; 242 #address-cells = <1>;
242 #size-cells = <0>; 243 #size-cells = <0>;
243 clocks = <&tegra_car 44>; 244 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
244 clock-names = "spi"; 245 clock-names = "spi";
245 status = "disabled"; 246 status = "disabled";
246 }; 247 };
@@ -252,7 +253,7 @@
252 nvidia,dma-request-selector = <&apbdma 17>; 253 nvidia,dma-request-selector = <&apbdma 17>;
253 #address-cells = <1>; 254 #address-cells = <1>;
254 #size-cells = <0>; 255 #size-cells = <0>;
255 clocks = <&tegra_car 46>; 256 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
256 clock-names = "spi"; 257 clock-names = "spi";
257 status = "disabled"; 258 status = "disabled";
258 }; 259 };
@@ -264,7 +265,7 @@
264 nvidia,dma-request-selector = <&apbdma 18>; 265 nvidia,dma-request-selector = <&apbdma 18>;
265 #address-cells = <1>; 266 #address-cells = <1>;
266 #size-cells = <0>; 267 #size-cells = <0>;
267 clocks = <&tegra_car 68>; 268 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
268 clock-names = "spi"; 269 clock-names = "spi";
269 status = "disabled"; 270 status = "disabled";
270 }; 271 };
@@ -276,7 +277,7 @@
276 nvidia,dma-request-selector = <&apbdma 27>; 277 nvidia,dma-request-selector = <&apbdma 27>;
277 #address-cells = <1>; 278 #address-cells = <1>;
278 #size-cells = <0>; 279 #size-cells = <0>;
279 clocks = <&tegra_car 104>; 280 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
280 clock-names = "spi"; 281 clock-names = "spi";
281 status = "disabled"; 282 status = "disabled";
282 }; 283 };
@@ -288,7 +289,7 @@
288 nvidia,dma-request-selector = <&apbdma 28>; 289 nvidia,dma-request-selector = <&apbdma 28>;
289 #address-cells = <1>; 290 #address-cells = <1>;
290 #size-cells = <0>; 291 #size-cells = <0>;
291 clocks = <&tegra_car 105>; 292 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
292 clock-names = "spi"; 293 clock-names = "spi";
293 status = "disabled"; 294 status = "disabled";
294 }; 295 };
@@ -297,21 +298,21 @@
297 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 298 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
298 reg = <0x7000e000 0x100>; 299 reg = <0x7000e000 0x100>;
299 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 300 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&tegra_car 4>; 301 clocks = <&tegra_car TEGRA114_CLK_RTC>;
301 }; 302 };
302 303
303 kbc { 304 kbc {
304 compatible = "nvidia,tegra114-kbc"; 305 compatible = "nvidia,tegra114-kbc";
305 reg = <0x7000e200 0x100>; 306 reg = <0x7000e200 0x100>;
306 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 307 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&tegra_car 36>; 308 clocks = <&tegra_car TEGRA114_CLK_KBC>;
308 status = "disabled"; 309 status = "disabled";
309 }; 310 };
310 311
311 pmc { 312 pmc {
312 compatible = "nvidia,tegra114-pmc"; 313 compatible = "nvidia,tegra114-pmc";
313 reg = <0x7000e400 0x400>; 314 reg = <0x7000e400 0x400>;
314 clocks = <&tegra_car 261>, <&clk32k_in>; 315 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
315 clock-names = "pclk", "clk32k_in"; 316 clock-names = "pclk", "clk32k_in";
316 }; 317 };
317 318
@@ -330,7 +331,7 @@
330 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 331 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
331 reg = <0x78000000 0x200>; 332 reg = <0x78000000 0x200>;
332 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 333 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&tegra_car 14>; 334 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
334 status = "disable"; 335 status = "disable";
335 }; 336 };
336 337
@@ -338,7 +339,7 @@
338 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 339 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
339 reg = <0x78000200 0x200>; 340 reg = <0x78000200 0x200>;
340 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 341 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&tegra_car 9>; 342 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
342 status = "disable"; 343 status = "disable";
343 }; 344 };
344 345
@@ -346,7 +347,7 @@
346 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 347 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
347 reg = <0x78000400 0x200>; 348 reg = <0x78000400 0x200>;
348 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 349 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&tegra_car 69>; 350 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
350 status = "disable"; 351 status = "disable";
351 }; 352 };
352 353
@@ -354,7 +355,7 @@
354 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 355 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
355 reg = <0x78000600 0x200>; 356 reg = <0x78000600 0x200>;
356 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 357 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&tegra_car 15>; 358 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
358 status = "disable"; 359 status = "disable";
359 }; 360 };
360 361