Basic lockdown functions like a page prefetching under lock method.

Conflicts:

	arch/arm/mm/cache-l2x0.c

Signed-off-by: Christopher Kenna <cjk@cs.unc.edu>

5 files changed, 256 insertions, 13 deletions

diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 4f98e8e07835..7783b715f60c 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -31,6 +31,9 @@ static void __iomem *l2x0_base;
 static DEFINE_SPINLOCK(l2x0_lock);
 static uint32_t l2x0_way_mask;  /* Bitmask of active ways */
 static uint32_t l2x0_size;
+static u32 l2x0_cache_id;
+static unsigned int l2x0_sets;
+static unsigned int l2x0_ways;
 
 static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
@@ -301,47 +304,46 @@ static void __init l2x0_unlock(__u32 cache_id)
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 {
         __u32 aux;
-        __u32 cache_id;
         __u32 way_size = 0;
-        int ways;
         const char *type;
 
         l2x0_base = base;
 
-        cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+        l2x0_cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
         aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
 
         aux &= aux_mask;
         aux |= aux_val;
 
         /* Determine the number of ways */
-        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+        switch (l2x0_cache_id & L2X0_CACHE_ID_PART_MASK) {
         case L2X0_CACHE_ID_PART_L310:
                 if (aux & (1 << 16))
-                        ways = 16;
+                        l2x0_ways = 16;
                 else
-                        ways = 8;
+                        l2x0_ways = 8;
                 type = "L310";
                 break;
         case L2X0_CACHE_ID_PART_L210:
-                ways = (aux >> 13) & 0xf;
+                l2x0_ways = (aux >> 13) & 0xf;
                 type = "L210";
                 break;
         default:
                 /* Assume unknown chips have 8 ways */
-                ways = 8;
+                l2x0_ways = 8;
                 type = "L2x0 series";
                 break;
         }
 
-        l2x0_way_mask = (1 << ways) - 1;
+        l2x0_way_mask = (1 << l2x0_ways) - 1;
 
         /*
          * L2 cache Size =  Way size * Number of ways
          */
         way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
-        way_size = 1 << (way_size + 3);
-        l2x0_size = ways * way_size * SZ_1K;
+        way_size = SZ_1K << (way_size + 3);
+        l2x0_size = l2x0_ways * way_size;
+        l2x0_sets = way_size / CACHE_LINE_SIZE;
 
         /*
          * Check if l2x0 controller is already enabled.
@@ -377,5 +379,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 
         printk(KERN_INFO "%s cache controller enabled\n", type);
         printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
-                        ways, cache_id, aux, l2x0_size);
+                        l2x0_ways, l2x0_cache_id, aux, l2x0_size);
+
+        litmus_setup_lockdown(l2x0_base, l2x0_cache_id);
 }
diff --git a/include/litmus/color.h b/include/litmus/color.h
index 615ebd80703c..5eef403a95c1 100644
--- a/include/litmus/color.h
+++ b/include/litmus/color.h
@@ -20,10 +20,15 @@ struct color_cache_info {
         unsigned long nr_colors;
 };
 
+int litmus_test_prefetch(struct ctl_table *, int, void __user *,
+                size_t *, loff_t *);
+
 /* defined in litmus/color.c */
 extern struct color_cache_info color_cache_info;
 extern unsigned long color_chunk;
 
+void litmus_setup_lockdown(void __iomem*, u32);
+
 struct vm_area_struct;
 struct ctl_table;
 
diff --git a/litmus/Makefile b/litmus/Makefile
index 76a07e8531c6..be5af62431bd 100644
--- a/litmus/Makefile
+++ b/litmus/Makefile
@@ -28,7 +28,8 @@ obj-y     = sched_plugin.o litmus.o \
             sched_pfp.o \
             sched_psn_edf.o \
             srp.o \
-            sync.o
+            sync.o \
+            lockdown.o
 
 obj-$(CONFIG_PLUGIN_CEDF) += sched_cedf.o
 obj-$(CONFIG_PLUGIN_PFAIR) += sched_pfair.o
diff --git a/litmus/color_proc.c b/litmus/color_proc.c
index 8ee624860d71..90d89da0521b 100644
--- a/litmus/color_proc.c
+++ b/litmus/color_proc.c
@@ -104,6 +104,11 @@ static struct ctl_table color_table[] =
                 .mode           = 0555,
                 .child          = cache_table,
         },
+        {
+                .procname       = "prefetch_test",
+                .mode           = 0644,
+                .proc_handler   = litmus_test_prefetch,
+        },
         { }
 };
 
diff --git a/litmus/lockdown.c b/litmus/lockdown.c
new file mode 100644
index 000000000000..b8c25006bc4f
--- /dev/null
+++ b/litmus/lockdown.c
@@ -0,0 +1,228 @@
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+
+#include <linux/smp.h> /* smp_call_func */
+#include <asm/processor.h> /* cpu relax */
+
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/cacheflush.h>
+
+#include <litmus/color.h>
+
+static void __iomem *cache_base;
+static void __iomem *lockreg_d;
+static void __iomem *lockreg_i;
+static raw_spinlock_t prefetch_lock;
+
+static u32 cache_id;
+static int nr_lockregs;
+
+#define ld_d_reg(cpu) ({ int __cpu = cpu; \
+                        void __iomem *__v = cache_base + L2X0_LOCKDOWN_WAY_D_BASE + \
+                        __cpu * L2X0_LOCKDOWN_STRIDE; __v; })
+#define ld_i_reg(cpu) ({ int __cpu = cpu; \
+                        void __iomem *__v = cache_base + L2X0_LOCKDOWN_WAY_I_BASE + \
+                        __cpu * L2X0_LOCKDOWN_STRIDE; __v; })
+
+#define MAX_NR_WAYS     16
+#define UNLOCK_ALL      0x00000000 /* allocation in any way */
+
+/*
+ * Prefetch by reading the first word of each cache line in a page.
+ *
+ * @lockdown_reg: address of the lockdown register to write
+ * @lock_val: value to be written to @lockdown_reg 
+ * @unlock_val: will unlock the cache to this value
+ * @addr: start address to be prefetched
+ * @end_addr: end address to prefetch (exclusive)
+ *
+ * Assumes: addr < end_addr AND addr != end_addr
+ */
+static u32 read_in_page(u32 lock_val,
+                  u32 unlock_val,
+                  void *start,
+                  void *end)
+{
+        unsigned long flags;
+        u32 v = 0, tmp = 0;
+
+        raw_spin_lock_irqsave(&prefetch_lock, flags);
+        __asm__ __volatile__ (
+"       .align 5\n"
+"       str     %[lockval], [%[cachereg]]\n"
+"1:     ldr     %[tmp], [%[addr]], #32          @ 32 bytes = 1 cache line\n"
+"       add     %[val], %[val], %[tmp]\n"
+"       cmp     %[addr], %[end]\n"
+"       bne     1b\n"
+"       str     %[unlockval], [%[cachereg]]\n"
+        : [addr] "+r" (start),
+          [val] "+r" (v),
+          [tmp] "+r" (tmp)
+        : [end] "r" (end),
+          [cachereg] "r" (lockreg_d),
+          [lockval] "r" (lock_val),
+          [unlockval] "r" (unlock_val)
+        : "cc");
+        raw_spin_unlock_irqrestore(&prefetch_lock, flags);
+
+        return v;
+}
+
+/*
+ * unlocked[i] : allocation can occur in way i
+ *
+ * 0 = allocation can occur in the corresponding way
+ * 1 = allocation cannot occur in the corresponding way
+ */
+static u32 unlocked[MAX_NR_WAYS]  = {
+        0xFFFFFFFE, /* way 0 unlocked */
+        0xFFFFFFFD,
+        0xFFFFFFFB, 
+        0xFFFFFFF7, 
+        0xFFFFFFEF, /* way 4 unlocked */
+        0xFFFFFFDF,
+        0xFFFFFFBF,
+        0xFFFFFF7F,
+        0xFFFFFEFF, /* way 8 unlocked */
+        0xFFFFFDFF,
+        0xFFFFFBFF,
+        0xFFFFF7FF,
+        0xFFFFEFFF, /* way 12 unlocked */
+        0xFFFFDFFF,
+        0xFFFFBFFF,
+        0xFFFF7FFF,
+};
+
+static void dump_lockdown_registers(void)
+{
+        int i;
+
+        for (i = 0; i < nr_lockregs; i++) {
+                printk("Lockdown Data CPU %2d: 0x%8x\n",
+                                i, readl_relaxed(ld_d_reg(i)));
+                printk("Lockdown Inst CPU %2d: 0x%8x\n",
+                                i, readl_relaxed(ld_d_reg(i)));
+        }
+}
+
+static void test_lockdown(void *ignore)
+{
+        int i;
+
+        printk("Start lockdown test on CPU %d.\n", smp_processor_id());
+
+        for (i = 0; i < nr_lockregs; i++) {
+                printk("CPU %2d data reg: 0x%8p\n", i, ld_d_reg(i)); printk("CPU %2d inst reg: 0x%8p\n", i, ld_i_reg(i)); }
+
+        printk("Lockdown initial state:\n");
+        dump_lockdown_registers();
+        printk("---\n");
+
+        for (i = 0; i < nr_lockregs; i++) {
+                writel_relaxed(1, ld_d_reg(i));
+                writel_relaxed(2, ld_i_reg(i));
+        }
+        printk("Lockdown all data=1 instr=2:\n");
+        dump_lockdown_registers();
+        printk("---\n");
+
+        for (i = 0; i < nr_lockregs; i++) {
+                writel_relaxed((1 << i), ld_d_reg(i));
+                writel_relaxed(((1 << 8) >> i), ld_i_reg(i));
+        }
+        printk("Lockdown varies:\n");
+        dump_lockdown_registers();
+        printk("---\n");
+
+        for (i = 0; i < nr_lockregs; i++) {
+                writel_relaxed(0, ld_d_reg(i));
+                writel_relaxed(0, ld_i_reg(i));
+        }
+        printk("Lockdown all zero:\n");
+        dump_lockdown_registers();
+
+        /* Checks that the unlocked array is set up correctly. */
+        for (i = 0; i < MAX_NR_WAYS; i++) {
+                unsigned long expected = 0xFFFFFFFF;
+                clear_bit(i, &expected);
+                if (expected != unlocked[i]) {
+                        WARN(1, "Unlock %2d: expected 0x%8x but got 0x%8x\n",
+                                        i, ((u32)expected), unlocked[i]);
+                }
+        }
+
+        printk("End lockdown test.\n");
+}
+
+#define LOCKREG_TEST_VAL        0x00000002
+#define PREFETCH_SUM_TEST_VAL   65024 /* = 0 + 8 + ... + 127 */
+int litmus_test_prefetch(struct ctl_table *table, int write, void __user *buffer,
+                size_t *lenp, loff_t *ppos)
+{
+        struct page *page;
+        void *vaddr;
+        u32 *data;
+        u32 sum = 0;
+        int i;
+        
+        if (!write)
+                return 0;
+
+        page = alloc_page(GFP_HIGHUSER | __GFP_MOVABLE);
+        if (!page) {
+                printk(KERN_WARNING "No memory\n");
+                return -ENOMEM;
+        }
+
+        vaddr = phys_to_virt(page_to_phys(page));
+        data = (u32*)vaddr;
+
+        for (i = 0; i < PAGE_SIZE / sizeof(u32); i++)
+                data[i] = i;
+
+        sum = read_in_page(UNLOCK_ALL, LOCKREG_TEST_VAL, vaddr, vaddr + PAGE_SIZE);
+        if (PREFETCH_SUM_TEST_VAL != sum) {
+                printk("%s: Expected sum %u but got %u!\n", __FUNCTION__,
+                                PREFETCH_SUM_TEST_VAL, sum);
+        } else {
+                printk("%s: Prefetch test passed.\n", __FUNCTION__);
+        }
+
+        if (LOCKREG_TEST_VAL != readl_relaxed(lockreg_d)) {
+                printk("%s: Expected lockreg value 0x%8x but got 0x%8x!\n",
+                                __FUNCTION__, LOCKREG_TEST_VAL,
+                                readl_relaxed(lockreg_d));
+        } else {
+                printk("%s: Lockdown state after prefetch test passed.\n",
+                                __FUNCTION__);
+        }
+
+        writel_relaxed(UNLOCK_ALL, ld_d_reg(i));
+
+        free_page(page_to_pfn(page));
+
+        return 0;
+}
+
+void litmus_setup_lockdown(void __iomem *base, u32 id)
+{
+        cache_base = base;
+        cache_id = id;
+        lockreg_d = cache_base + L2X0_LOCKDOWN_WAY_D_BASE;
+        lockreg_i = cache_base + L2X0_LOCKDOWN_WAY_I_BASE;
+
+
+        if (L2X0_CACHE_ID_PART_L310 == (cache_id & L2X0_CACHE_ID_PART_MASK)) {
+                nr_lockregs = 8;
+        } else {
+                printk("Unknown cache ID!\n");
+                nr_lockregs = 1;
+        }
+
+        raw_spin_lock_init(&prefetch_lock);
+
+        test_lockdown(NULL);
+}