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authorJonas Gorski <jogo@openwrt.org>2013-03-21 10:03:19 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-05-07 19:19:03 -0400
commita156ba61f0b959a803d7a6941a52c5453524c99b (patch)
tree88f63c83bbf2f130fd743d3312c4387294e6ff16
parent08a41d1206bb342c2f0a0aae25ca836658866268 (diff)
MIPS: BCM63XX: enable pcie for BCM6362
The PCIe controller is almost the same as the BCM6328 one, with only the SERDES register being at a different location. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5011/ Acked-by: John Crispin <blogic@openwrt.org>
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h3
-rw-r--r--arch/mips/pci/pci-bcm63xx.c11
2 files changed, 11 insertions, 3 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 129b8a6b7684..243bab96f3f7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -1365,7 +1365,8 @@
1365/************************************************************************* 1365/*************************************************************************
1366 * _REG relative to RSET_MISC 1366 * _REG relative to RSET_MISC
1367 *************************************************************************/ 1367 *************************************************************************/
1368#define MISC_SERDES_CTRL_REG 0x0 1368#define MISC_SERDES_CTRL_6328_REG 0x0
1369#define MISC_SERDES_CTRL_6362_REG 0x4
1369#define SERDES_PCIE_EN (1 << 0) 1370#define SERDES_PCIE_EN (1 << 0)
1370#define SERDES_PCIE_EXD_EN (1 << 15) 1371#define SERDES_PCIE_EXD_EN (1 << 15)
1371 1372
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 88e781c6b5ba..2eb954239bc5 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -121,11 +121,17 @@ void __iomem *pci_iospace_start;
121static void __init bcm63xx_reset_pcie(void) 121static void __init bcm63xx_reset_pcie(void)
122{ 122{
123 u32 val; 123 u32 val;
124 u32 reg;
124 125
125 /* enable SERDES */ 126 /* enable SERDES */
126 val = bcm_misc_readl(MISC_SERDES_CTRL_REG); 127 if (BCMCPU_IS_6328())
128 reg = MISC_SERDES_CTRL_6328_REG;
129 else
130 reg = MISC_SERDES_CTRL_6362_REG;
131
132 val = bcm_misc_readl(reg);
127 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; 133 val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
128 bcm_misc_writel(val, MISC_SERDES_CTRL_REG); 134 bcm_misc_writel(val, reg);
129 135
130 /* reset the PCIe core */ 136 /* reset the PCIe core */
131 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); 137 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
@@ -330,6 +336,7 @@ static int __init bcm63xx_pci_init(void)
330 336
331 switch (bcm63xx_get_cpu_id()) { 337 switch (bcm63xx_get_cpu_id()) {
332 case BCM6328_CPU_ID: 338 case BCM6328_CPU_ID:
339 case BCM6362_CPU_ID:
333 return bcm63xx_register_pcie(); 340 return bcm63xx_register_pcie();
334 case BCM6348_CPU_ID: 341 case BCM6348_CPU_ID:
335 case BCM6358_CPU_ID: 342 case BCM6358_CPU_ID: