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authorLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2011-11-17 12:31:51 -0500
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>2012-11-19 10:44:33 -0500
commita0ae02405076ac32bd17ece976e914b5b6075bb0 (patch)
tree210b4b6a8c58cac502ba1d1c6a4f1c33bb494cd9
parentcb8cf4f821044f140ea5b9c8d4f816f0c05fab44 (diff)
ARM: kernel: add device tree init map function
When booting through a device tree, the kernel cpu logical id map can be initialized using device tree data passed by FW or through an embedded blob. This patch adds a function that parses device tree "cpu" nodes and retrieves the corresponding CPUs hardware identifiers (MPIDR). It sets the possible cpus and the cpu logical map values according to the number of CPUs defined in the device tree and respective properties. The device tree HW identifiers are considered valid if all CPU nodes contain a "reg" property, there are no duplicate "reg" entries and the DT defines a CPU node whose "reg" property matches the MPIDR[23:0] of the boot CPU. The primary CPU is assigned cpu logical number 0 to keep the current convention valid. Current bindings documentation is included in the patch: Documentation/devicetree/bindings/arm/cpus.txt Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org>
-rw-r--r--Documentation/devicetree/bindings/arm/cpus.txt77
-rw-r--r--arch/arm/include/asm/prom.h2
-rw-r--r--arch/arm/kernel/devtree.c100
3 files changed, 179 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
new file mode 100644
index 000000000000..f32494dbfe19
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -0,0 +1,77 @@
1* ARM CPUs binding description
2
3The device tree allows to describe the layout of CPUs in a system through
4the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
5defining properties for every cpu.
6
7Bindings for CPU nodes follow the ePAPR standard, available from:
8
9http://devicetree.org
10
11For the ARM architecture every CPU node must contain the following properties:
12
13- device_type: must be "cpu"
14- reg: property matching the CPU MPIDR[23:0] register bits
15 reg[31:24] bits must be set to 0
16- compatible: should be one of:
17 "arm,arm1020"
18 "arm,arm1020e"
19 "arm,arm1022"
20 "arm,arm1026"
21 "arm,arm720"
22 "arm,arm740"
23 "arm,arm7tdmi"
24 "arm,arm920"
25 "arm,arm922"
26 "arm,arm925"
27 "arm,arm926"
28 "arm,arm940"
29 "arm,arm946"
30 "arm,arm9tdmi"
31 "arm,cortex-a5"
32 "arm,cortex-a7"
33 "arm,cortex-a8"
34 "arm,cortex-a9"
35 "arm,cortex-a15"
36 "arm,arm1136"
37 "arm,arm1156"
38 "arm,arm1176"
39 "arm,arm11mpcore"
40 "faraday,fa526"
41 "intel,sa110"
42 "intel,sa1100"
43 "marvell,feroceon"
44 "marvell,mohawk"
45 "marvell,xsc3"
46 "marvell,xscale"
47
48Example:
49
50 cpus {
51 #size-cells = <0>;
52 #address-cells = <1>;
53
54 CPU0: cpu@0 {
55 device_type = "cpu";
56 compatible = "arm,cortex-a15";
57 reg = <0x0>;
58 };
59
60 CPU1: cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <0x1>;
64 };
65
66 CPU2: cpu@100 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a7";
69 reg = <0x100>;
70 };
71
72 CPU3: cpu@101 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a7";
75 reg = <0x101>;
76 };
77 };
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index aeae9c609df4..8dd51dc1a367 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -15,6 +15,7 @@
15 15
16extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys); 16extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
17extern void arm_dt_memblock_reserve(void); 17extern void arm_dt_memblock_reserve(void);
18extern void __init arm_dt_init_cpu_maps(void);
18 19
19#else /* CONFIG_OF */ 20#else /* CONFIG_OF */
20 21
@@ -24,6 +25,7 @@ static inline struct machine_desc *setup_machine_fdt(unsigned int dt_phys)
24} 25}
25 26
26static inline void arm_dt_memblock_reserve(void) { } 27static inline void arm_dt_memblock_reserve(void) { }
28static inline void arm_dt_init_cpu_maps(void) { }
27 29
28#endif /* CONFIG_OF */ 30#endif /* CONFIG_OF */
29#endif /* ASMARM_PROM_H */ 31#endif /* ASMARM_PROM_H */
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index bee7f9d47f02..aaf9add497fe 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -19,8 +19,10 @@
19#include <linux/of_irq.h> 19#include <linux/of_irq.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21 21
22#include <asm/cputype.h>
22#include <asm/setup.h> 23#include <asm/setup.h>
23#include <asm/page.h> 24#include <asm/page.h>
25#include <asm/smp_plat.h>
24#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
25#include <asm/mach-types.h> 27#include <asm/mach-types.h>
26 28
@@ -61,6 +63,104 @@ void __init arm_dt_memblock_reserve(void)
61 } 63 }
62} 64}
63 65
66/*
67 * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
68 * and builds the cpu logical map array containing MPIDR values related to
69 * logical cpus
70 *
71 * Updates the cpu possible mask with the number of parsed cpu nodes
72 */
73void __init arm_dt_init_cpu_maps(void)
74{
75 /*
76 * Temp logical map is initialized with UINT_MAX values that are
77 * considered invalid logical map entries since the logical map must
78 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
79 * read as 0.
80 */
81 struct device_node *cpu, *cpus;
82 u32 i, j, cpuidx = 1;
83 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
84
85 u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
86 bool bootcpu_valid = false;
87 cpus = of_find_node_by_path("/cpus");
88
89 if (!cpus)
90 return;
91
92 for_each_child_of_node(cpus, cpu) {
93 u32 hwid;
94
95 pr_debug(" * %s...\n", cpu->full_name);
96 /*
97 * A device tree containing CPU nodes with missing "reg"
98 * properties is considered invalid to build the
99 * cpu_logical_map.
100 */
101 if (of_property_read_u32(cpu, "reg", &hwid)) {
102 pr_debug(" * %s missing reg property\n",
103 cpu->full_name);
104 return;
105 }
106
107 /*
108 * 8 MSBs must be set to 0 in the DT since the reg property
109 * defines the MPIDR[23:0].
110 */
111 if (hwid & ~MPIDR_HWID_BITMASK)
112 return;
113
114 /*
115 * Duplicate MPIDRs are a recipe for disaster.
116 * Scan all initialized entries and check for
117 * duplicates. If any is found just bail out.
118 * temp values were initialized to UINT_MAX
119 * to avoid matching valid MPIDR[23:0] values.
120 */
121 for (j = 0; j < cpuidx; j++)
122 if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
123 "properties in the DT\n"))
124 return;
125
126 /*
127 * Build a stashed array of MPIDR values. Numbering scheme
128 * requires that if detected the boot CPU must be assigned
129 * logical id 0. Other CPUs get sequential indexes starting
130 * from 1. If a CPU node with a reg property matching the
131 * boot CPU MPIDR is detected, this is recorded so that the
132 * logical map built from DT is validated and can be used
133 * to override the map created in smp_setup_processor_id().
134 */
135 if (hwid == mpidr) {
136 i = 0;
137 bootcpu_valid = true;
138 } else {
139 i = cpuidx++;
140 }
141
142 tmp_map[i] = hwid;
143
144 if (cpuidx > nr_cpu_ids)
145 break;
146 }
147
148 if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
149 "fall back to default cpu_logical_map\n"))
150 return;
151
152 /*
153 * Since the boot CPU node contains proper data, and all nodes have
154 * a reg property, the DT CPU list can be considered valid and the
155 * logical map created in smp_setup_processor_id() can be overridden
156 */
157 for (i = 0; i < cpuidx; i++) {
158 set_cpu_possible(i, true);
159 cpu_logical_map(i) = tmp_map[i];
160 pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
161 }
162}
163
64/** 164/**
65 * setup_machine_fdt - Machine setup when an dtb was passed to the kernel 165 * setup_machine_fdt - Machine setup when an dtb was passed to the kernel
66 * @dt_phys: physical address of dt blob 166 * @dt_phys: physical address of dt blob