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authorJesse Barnes <jbarnes@virtuousgeek.org>2013-07-26 16:32:51 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-09-03 13:17:56 -0400
commita0a1807544fe59b42d3760ee912ea4c6741298f5 (patch)
treedb91022ae6883ec1fd872f74423185de50dd3329
parentfac15c108248e8d592fb8f4cbcf26d98b3485526 (diff)
drm/i915: split PCI IDs out into i915_drm.h v4
For use by userspace (at some point in the future) and other kernel code. v2: move PCI IDs to uabi (Chris) move PCI IDs to drm/ (Dave) v3: fixup Quanta detection - needs to come first (Daniel) v4: fix up PCI match structure init for easier use by userspace (Chris) Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c164
-rw-r--r--include/drm/i915_drm.h2
-rw-r--r--include/drm/i915_pciids.h211
3 files changed, 247 insertions, 130 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ccb28ead3501..69d8ed5416c3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -157,25 +157,6 @@ MODULE_PARM_DESC(prefault_disable,
157static struct drm_driver driver; 157static struct drm_driver driver;
158extern int intel_agp_enabled; 158extern int intel_agp_enabled;
159 159
160#define INTEL_VGA_DEVICE(id, info) { \
161 .class = PCI_BASE_CLASS_DISPLAY << 16, \
162 .class_mask = 0xff0000, \
163 .vendor = 0x8086, \
164 .device = id, \
165 .subvendor = PCI_ANY_ID, \
166 .subdevice = PCI_ANY_ID, \
167 .driver_data = (unsigned long) info }
168
169#define INTEL_QUANTA_VGA_DEVICE(info) { \
170 .class = PCI_BASE_CLASS_DISPLAY << 16, \
171 .class_mask = 0xff0000, \
172 .vendor = 0x8086, \
173 .device = 0x16a, \
174 .subvendor = 0x152d, \
175 .subdevice = 0x8990, \
176 .driver_data = (unsigned long) info }
177
178
179static const struct intel_device_info intel_i830_info = { 160static const struct intel_device_info intel_i830_info = {
180 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 161 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
181 .has_overlay = 1, .overlay_needs_physical = 1, 162 .has_overlay = 1, .overlay_needs_physical = 1,
@@ -350,118 +331,41 @@ static const struct intel_device_info intel_haswell_m_info = {
350 .has_vebox_ring = 1, 331 .has_vebox_ring = 1,
351}; 332};
352 333
334/*
335 * Make sure any device matches here are from most specific to most
336 * general. For example, since the Quanta match is based on the subsystem
337 * and subvendor IDs, we need it to come before the more general IVB
338 * PCI ID matches, otherwise we'll use the wrong info struct above.
339 */
340#define INTEL_PCI_IDS \
341 INTEL_I830_IDS(&intel_i830_info), \
342 INTEL_I845G_IDS(&intel_845g_info), \
343 INTEL_I85X_IDS(&intel_i85x_info), \
344 INTEL_I865G_IDS(&intel_i865g_info), \
345 INTEL_I915G_IDS(&intel_i915g_info), \
346 INTEL_I915GM_IDS(&intel_i915gm_info), \
347 INTEL_I945G_IDS(&intel_i945g_info), \
348 INTEL_I945GM_IDS(&intel_i945gm_info), \
349 INTEL_I965G_IDS(&intel_i965g_info), \
350 INTEL_G33_IDS(&intel_g33_info), \
351 INTEL_I965GM_IDS(&intel_i965gm_info), \
352 INTEL_GM45_IDS(&intel_gm45_info), \
353 INTEL_G45_IDS(&intel_g45_info), \
354 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
355 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
356 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
357 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
358 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
359 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
360 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
361 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
362 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
363 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
364 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
365 INTEL_VLV_D_IDS(&intel_valleyview_d_info)
366
353static const struct pci_device_id pciidlist[] = { /* aka */ 367static const struct pci_device_id pciidlist[] = { /* aka */
354 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ 368 INTEL_PCI_IDS,
355 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
356 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
357 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
358 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
359 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
360 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
361 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
362 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
363 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
364 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
365 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
366 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
367 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
368 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
369 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
370 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
371 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
372 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
373 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
374 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
375 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
376 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
377 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
378 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
379 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
380 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
381 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
382 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
383 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
384 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
385 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
386 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
387 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
388 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
389 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
390 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
391 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
392 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
393 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
394 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
395 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
396 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
397 INTEL_QUANTA_VGA_DEVICE(&intel_ivybridge_q_info), /* Quanta transcode */
398 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
399 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
400 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
401 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
402 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
403 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
404 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
405 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
406 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
407 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
408 INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
409 INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
410 INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
411 INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
412 INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
413 INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
414 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
415 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
416 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
417 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
418 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
419 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
420 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
421 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
422 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
423 INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
424 INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
425 INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
426 INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
427 INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
428 INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
429 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
430 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
431 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
432 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
433 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
434 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
435 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
436 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
437 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
438 INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
439 INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
440 INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
441 INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
442 INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
443 INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
444 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
445 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
446 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
447 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
448 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
449 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
450 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
451 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
452 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
453 INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
454 INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
455 INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
456 INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
457 INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
458 INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
459 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
460 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
461 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
462 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
463 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
464 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
465 {0, 0, 0} 369 {0, 0, 0}
466}; 370};
467 371
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 63d609d8a3f6..7276a72710e2 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -26,6 +26,7 @@
26#ifndef _I915_DRM_H_ 26#ifndef _I915_DRM_H_
27#define _I915_DRM_H_ 27#define _I915_DRM_H_
28 28
29#include <drm/i915_pciids.h>
29#include <uapi/drm/i915_drm.h> 30#include <uapi/drm/i915_drm.h>
30 31
31/* For use by IPS driver */ 32/* For use by IPS driver */
@@ -34,4 +35,5 @@ extern bool i915_gpu_raise(void);
34extern bool i915_gpu_lower(void); 35extern bool i915_gpu_lower(void);
35extern bool i915_gpu_busy(void); 36extern bool i915_gpu_busy(void);
36extern bool i915_gpu_turbo_disable(void); 37extern bool i915_gpu_turbo_disable(void);
38
37#endif /* _I915_DRM_H_ */ 39#endif /* _I915_DRM_H_ */
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
new file mode 100644
index 000000000000..8a10f5c354e6
--- /dev/null
+++ b/include/drm/i915_pciids.h
@@ -0,0 +1,211 @@
1/*
2 * Copyright 2013 Intel Corporation
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25#ifndef _I915_PCIIDS_H
26#define _I915_PCIIDS_H
27
28/*
29 * A pci_device_id struct {
30 * __u32 vendor, device;
31 * __u32 subvendor, subdevice;
32 * __u32 class, class_mask;
33 * kernel_ulong_t driver_data;
34 * };
35 * Don't use C99 here because "class" is reserved and we want to
36 * give userspace flexibility.
37 */
38#define INTEL_VGA_DEVICE(id, info) { \
39 0x8086, id, \
40 ~0, ~0, \
41 0x030000, 0xff0000, \
42 (unsigned long) info }
43
44#define INTEL_QUANTA_VGA_DEVICE(info) { \
45 0x8086, 0x16a, \
46 0x152d, 0x8990, \
47 0x030000, 0xff0000, \
48 (unsigned long) info }
49
50#define INTEL_I830_IDS(info) \
51 INTEL_VGA_DEVICE(0x3577, info)
52
53#define INTEL_I845G_IDS(info) \
54 INTEL_VGA_DEVICE(0x2562, info)
55
56#define INTEL_I85X_IDS(info) \
57 INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
58 INTEL_VGA_DEVICE(0x358e, info)
59
60#define INTEL_I865G_IDS(info) \
61 INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
62
63#define INTEL_I915G_IDS(info) \
64 INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
65 INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
66
67#define INTEL_I915GM_IDS(info) \
68 INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
69
70#define INTEL_I945G_IDS(info) \
71 INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
72
73#define INTEL_I945GM_IDS(info) \
74 INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
75 INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
76
77#define INTEL_I965G_IDS(info) \
78 INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
79 INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
80 INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
81 INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
82
83#define INTEL_G33_IDS(info) \
84 INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
85 INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
86 INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
87
88#define INTEL_I965GM_IDS(info) \
89 INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
90 INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
91
92#define INTEL_GM45_IDS(info) \
93 INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
94
95#define INTEL_G45_IDS(info) \
96 INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
97 INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
98 INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
99 INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
100 INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
101 INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
102
103#define INTEL_PINEVIEW_IDS(info) \
104 INTEL_VGA_DEVICE(0xa001, info), \
105 INTEL_VGA_DEVICE(0xa011, info)
106
107#define INTEL_IRONLAKE_D_IDS(info) \
108 INTEL_VGA_DEVICE(0x0042, info)
109
110#define INTEL_IRONLAKE_M_IDS(info) \
111 INTEL_VGA_DEVICE(0x0046, info)
112
113#define INTEL_SNB_D_IDS(info) \
114 INTEL_VGA_DEVICE(0x0102, info), \
115 INTEL_VGA_DEVICE(0x0112, info), \
116 INTEL_VGA_DEVICE(0x0122, info), \
117 INTEL_VGA_DEVICE(0x010A, info)
118
119#define INTEL_SNB_M_IDS(info) \
120 INTEL_VGA_DEVICE(0x0106, info), \
121 INTEL_VGA_DEVICE(0x0116, info), \
122 INTEL_VGA_DEVICE(0x0126, info)
123
124#define INTEL_IVB_M_IDS(info) \
125 INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
126 INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
127
128#define INTEL_IVB_D_IDS(info) \
129 INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
130 INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
131 INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
132 INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
133
134#define INTEL_IVB_Q_IDS(info) \
135 INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
136
137#define INTEL_HSW_D_IDS(info) \
138 INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
139 INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
140 INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
141 INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
142 INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
143 INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
144 INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
145 INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
146 INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
147 INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
148 INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
149 INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
150 INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
151 INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
152 INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
153 INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
154 INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
155 INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
156 INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
157 INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
158 INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
159 INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
160 INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
161 INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
162 INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
163 INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
164 INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
165 INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
166 INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
167 INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
168 INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
169 INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
170 INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
171 INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
172 INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
173 INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
174 INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
175 INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
176 INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
177 INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
178 INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
179 INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
180 INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
181 INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
182 INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
183
184#define INTEL_HSW_M_IDS(info) \
185 INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
186 INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
187 INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
188 INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
189 INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
190 INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
191 INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
192 INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
193 INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
194 INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
195 INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
196 INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
197 INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
198 INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
199 INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
200
201#define INTEL_VLV_M_IDS(info) \
202 INTEL_VGA_DEVICE(0x0f30, info), \
203 INTEL_VGA_DEVICE(0x0f31, info), \
204 INTEL_VGA_DEVICE(0x0f32, info), \
205 INTEL_VGA_DEVICE(0x0f33, info), \
206 INTEL_VGA_DEVICE(0x0157, info)
207
208#define INTEL_VLV_D_IDS(info) \
209 INTEL_VGA_DEVICE(0x0155, info)
210
211#endif /* _I915_PCIIDS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 14:08:50 -0500