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authorKukjin Kim <kgene.kim@samsung.com>2014-07-01 18:50:43 -0400
committerKukjin Kim <kgene.kim@samsung.com>2014-07-07 18:28:49 -0400
commita07a6a30af15cd356b782b6ddde2c710862e8ff7 (patch)
tree43158ff0d5f0232307de7422def9d514b0466e89
parent070b8b436b5510a213b7f38e120ff6cc4d0e89a1 (diff)
gpio: samsung: remove s5p64x0 related gpio codes
This patch removes gpio codes for s5p6440 and s5p6450 SoCs. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--drivers/gpio/gpio-samsung.c446
1 files changed, 0 insertions, 446 deletions
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 07105ee5c9ae..d12945cda0b4 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -358,47 +358,6 @@ static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
358} 358}
359#endif 359#endif
360 360
361#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
362static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
363 unsigned int off, unsigned int cfg)
364{
365 void __iomem *reg = chip->base;
366 unsigned int shift;
367 u32 con;
368
369 switch (off) {
370 case 0:
371 case 1:
372 case 2:
373 case 3:
374 case 4:
375 case 5:
376 shift = (off & 7) * 4;
377 reg -= 4;
378 break;
379 case 6:
380 shift = ((off + 1) & 7) * 4;
381 reg -= 4;
382 break;
383 default:
384 shift = ((off + 1) & 7) * 4;
385 break;
386 }
387
388 if (samsung_gpio_is_cfg_special(cfg)) {
389 cfg &= 0xf;
390 cfg <<= shift;
391 }
392
393 con = __raw_readl(reg);
394 con &= ~(0xf << shift);
395 con |= cfg;
396 __raw_writel(con, reg);
397
398 return 0;
399}
400#endif
401
402static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg, 361static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
403 int nr_chips) 362 int nr_chips)
404{ 363{
@@ -426,16 +385,6 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
426}; 385};
427#endif 386#endif
428 387
429#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
430static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
431 .cfg_eint = 0x3,
432 .set_config = s5p64x0_gpio_setcfg_rbank,
433 .get_config = samsung_gpio_getcfg_4bit,
434 .set_pull = samsung_gpio_setpull_updown,
435 .get_pull = samsung_gpio_getpull_updown,
436};
437#endif
438
439static struct samsung_gpio_cfg samsung_gpio_cfgs[] = { 388static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
440 [0] = { 389 [0] = {
441 .cfg_eint = 0x0, 390 .cfg_eint = 0x0,
@@ -708,91 +657,6 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
708} 657}
709#endif 658#endif
710 659
711/* The next set of routines are for the case of s5p64x0 bank r */
712
713static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
714 unsigned int offset)
715{
716 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
717 void __iomem *base = ourchip->base;
718 void __iomem *regcon = base;
719 unsigned long con;
720 unsigned long flags;
721
722 switch (offset) {
723 case 6:
724 offset += 1;
725 case 0:
726 case 1:
727 case 2:
728 case 3:
729 case 4:
730 case 5:
731 regcon -= 4;
732 break;
733 default:
734 offset -= 7;
735 break;
736 }
737
738 samsung_gpio_lock(ourchip, flags);
739
740 con = __raw_readl(regcon);
741 con &= ~(0xf << con_4bit_shift(offset));
742 __raw_writel(con, regcon);
743
744 samsung_gpio_unlock(ourchip, flags);
745
746 return 0;
747}
748
749static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
750 unsigned int offset, int value)
751{
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
755 unsigned long con;
756 unsigned long dat;
757 unsigned long flags;
758 unsigned con_offset = offset;
759
760 switch (con_offset) {
761 case 6:
762 con_offset += 1;
763 case 0:
764 case 1:
765 case 2:
766 case 3:
767 case 4:
768 case 5:
769 regcon -= 4;
770 break;
771 default:
772 con_offset -= 7;
773 break;
774 }
775
776 samsung_gpio_lock(ourchip, flags);
777
778 con = __raw_readl(regcon);
779 con &= ~(0xf << con_4bit_shift(con_offset));
780 con |= 0x1 << con_4bit_shift(con_offset);
781
782 dat = __raw_readl(base + GPIODAT_OFF);
783 if (value)
784 dat |= 1 << offset;
785 else
786 dat &= ~(1 << offset);
787
788 __raw_writel(con, regcon);
789 __raw_writel(dat, base + GPIODAT_OFF);
790
791 samsung_gpio_unlock(ourchip, flags);
792
793 return 0;
794}
795
796static void samsung_gpiolib_set(struct gpio_chip *chip, 660static void samsung_gpiolib_set(struct gpio_chip *chip,
797 unsigned offset, int value) 661 unsigned offset, int value)
798{ 662{
@@ -999,20 +863,6 @@ static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chi
999 } 863 }
1000} 864}
1001 865
1002static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1003 int nr_chips)
1004{
1005 for (; nr_chips > 0; nr_chips--, chip++) {
1006 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1007 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1008
1009 if (!chip->pm)
1010 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1011
1012 samsung_gpiolib_add(chip);
1013 }
1014}
1015
1016int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) 866int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1017{ 867{
1018 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip); 868 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
@@ -1320,284 +1170,6 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1320}; 1170};
1321 1171
1322/* 1172/*
1323 * S5P6440 GPIO bank summary:
1324 *
1325 * Bank GPIOs Style SlpCon ExtInt Group
1326 * A 6 4Bit Yes 1
1327 * B 7 4Bit Yes 1
1328 * C 8 4Bit Yes 2
1329 * F 2 2Bit Yes 4 [1]
1330 * G 7 4Bit Yes 5
1331 * H 10 4Bit[2] Yes 6
1332 * I 16 2Bit Yes None
1333 * J 12 2Bit Yes None
1334 * N 16 2Bit No IRQ_EINT
1335 * P 8 2Bit Yes 8
1336 * R 15 4Bit[2] Yes 8
1337 */
1338
1339static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1340#ifdef CONFIG_CPU_S5P6440
1341 {
1342 .chip = {
1343 .base = S5P6440_GPA(0),
1344 .ngpio = S5P6440_GPIO_A_NR,
1345 .label = "GPA",
1346 },
1347 }, {
1348 .chip = {
1349 .base = S5P6440_GPB(0),
1350 .ngpio = S5P6440_GPIO_B_NR,
1351 .label = "GPB",
1352 },
1353 }, {
1354 .chip = {
1355 .base = S5P6440_GPC(0),
1356 .ngpio = S5P6440_GPIO_C_NR,
1357 .label = "GPC",
1358 },
1359 }, {
1360 .base = S5P64X0_GPG_BASE,
1361 .chip = {
1362 .base = S5P6440_GPG(0),
1363 .ngpio = S5P6440_GPIO_G_NR,
1364 .label = "GPG",
1365 },
1366 },
1367#endif
1368};
1369
1370static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1371#ifdef CONFIG_CPU_S5P6440
1372 {
1373 .base = S5P64X0_GPH_BASE + 0x4,
1374 .chip = {
1375 .base = S5P6440_GPH(0),
1376 .ngpio = S5P6440_GPIO_H_NR,
1377 .label = "GPH",
1378 },
1379 },
1380#endif
1381};
1382
1383static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1384#ifdef CONFIG_CPU_S5P6440
1385 {
1386 .base = S5P64X0_GPR_BASE + 0x4,
1387 .config = &s5p64x0_gpio_cfg_rbank,
1388 .chip = {
1389 .base = S5P6440_GPR(0),
1390 .ngpio = S5P6440_GPIO_R_NR,
1391 .label = "GPR",
1392 },
1393 },
1394#endif
1395};
1396
1397static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1398#ifdef CONFIG_CPU_S5P6440
1399 {
1400 .base = S5P64X0_GPF_BASE,
1401 .config = &samsung_gpio_cfgs[6],
1402 .chip = {
1403 .base = S5P6440_GPF(0),
1404 .ngpio = S5P6440_GPIO_F_NR,
1405 .label = "GPF",
1406 },
1407 }, {
1408 .base = S5P64X0_GPI_BASE,
1409 .config = &samsung_gpio_cfgs[4],
1410 .chip = {
1411 .base = S5P6440_GPI(0),
1412 .ngpio = S5P6440_GPIO_I_NR,
1413 .label = "GPI",
1414 },
1415 }, {
1416 .base = S5P64X0_GPJ_BASE,
1417 .config = &samsung_gpio_cfgs[4],
1418 .chip = {
1419 .base = S5P6440_GPJ(0),
1420 .ngpio = S5P6440_GPIO_J_NR,
1421 .label = "GPJ",
1422 },
1423 }, {
1424 .base = S5P64X0_GPN_BASE,
1425 .config = &samsung_gpio_cfgs[5],
1426 .chip = {
1427 .base = S5P6440_GPN(0),
1428 .ngpio = S5P6440_GPIO_N_NR,
1429 .label = "GPN",
1430 },
1431 }, {
1432 .base = S5P64X0_GPP_BASE,
1433 .config = &samsung_gpio_cfgs[6],
1434 .chip = {
1435 .base = S5P6440_GPP(0),
1436 .ngpio = S5P6440_GPIO_P_NR,
1437 .label = "GPP",
1438 },
1439 },
1440#endif
1441};
1442
1443/*
1444 * S5P6450 GPIO bank summary:
1445 *
1446 * Bank GPIOs Style SlpCon ExtInt Group
1447 * A 6 4Bit Yes 1
1448 * B 7 4Bit Yes 1
1449 * C 8 4Bit Yes 2
1450 * D 8 4Bit Yes None
1451 * F 2 2Bit Yes None
1452 * G 14 4Bit[2] Yes 5
1453 * H 10 4Bit[2] Yes 6
1454 * I 16 2Bit Yes None
1455 * J 12 2Bit Yes None
1456 * K 5 4Bit Yes None
1457 * N 16 2Bit No IRQ_EINT
1458 * P 11 2Bit Yes 8
1459 * Q 14 2Bit Yes None
1460 * R 15 4Bit[2] Yes None
1461 * S 8 2Bit Yes None
1462 *
1463 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1464 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1465 */
1466
1467static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1468#ifdef CONFIG_CPU_S5P6450
1469 {
1470 .chip = {
1471 .base = S5P6450_GPA(0),
1472 .ngpio = S5P6450_GPIO_A_NR,
1473 .label = "GPA",
1474 },
1475 }, {
1476 .chip = {
1477 .base = S5P6450_GPB(0),
1478 .ngpio = S5P6450_GPIO_B_NR,
1479 .label = "GPB",
1480 },
1481 }, {
1482 .chip = {
1483 .base = S5P6450_GPC(0),
1484 .ngpio = S5P6450_GPIO_C_NR,
1485 .label = "GPC",
1486 },
1487 }, {
1488 .chip = {
1489 .base = S5P6450_GPD(0),
1490 .ngpio = S5P6450_GPIO_D_NR,
1491 .label = "GPD",
1492 },
1493 }, {
1494 .base = S5P6450_GPK_BASE,
1495 .chip = {
1496 .base = S5P6450_GPK(0),
1497 .ngpio = S5P6450_GPIO_K_NR,
1498 .label = "GPK",
1499 },
1500 },
1501#endif
1502};
1503
1504static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1505#ifdef CONFIG_CPU_S5P6450
1506 {
1507 .base = S5P64X0_GPG_BASE + 0x4,
1508 .chip = {
1509 .base = S5P6450_GPG(0),
1510 .ngpio = S5P6450_GPIO_G_NR,
1511 .label = "GPG",
1512 },
1513 }, {
1514 .base = S5P64X0_GPH_BASE + 0x4,
1515 .chip = {
1516 .base = S5P6450_GPH(0),
1517 .ngpio = S5P6450_GPIO_H_NR,
1518 .label = "GPH",
1519 },
1520 },
1521#endif
1522};
1523
1524static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1525#ifdef CONFIG_CPU_S5P6450
1526 {
1527 .base = S5P64X0_GPR_BASE + 0x4,
1528 .config = &s5p64x0_gpio_cfg_rbank,
1529 .chip = {
1530 .base = S5P6450_GPR(0),
1531 .ngpio = S5P6450_GPIO_R_NR,
1532 .label = "GPR",
1533 },
1534 },
1535#endif
1536};
1537
1538static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1539#ifdef CONFIG_CPU_S5P6450
1540 {
1541 .base = S5P64X0_GPF_BASE,
1542 .config = &samsung_gpio_cfgs[6],
1543 .chip = {
1544 .base = S5P6450_GPF(0),
1545 .ngpio = S5P6450_GPIO_F_NR,
1546 .label = "GPF",
1547 },
1548 }, {
1549 .base = S5P64X0_GPI_BASE,
1550 .config = &samsung_gpio_cfgs[4],
1551 .chip = {
1552 .base = S5P6450_GPI(0),
1553 .ngpio = S5P6450_GPIO_I_NR,
1554 .label = "GPI",
1555 },
1556 }, {
1557 .base = S5P64X0_GPJ_BASE,
1558 .config = &samsung_gpio_cfgs[4],
1559 .chip = {
1560 .base = S5P6450_GPJ(0),
1561 .ngpio = S5P6450_GPIO_J_NR,
1562 .label = "GPJ",
1563 },
1564 }, {
1565 .base = S5P64X0_GPN_BASE,
1566 .config = &samsung_gpio_cfgs[5],
1567 .chip = {
1568 .base = S5P6450_GPN(0),
1569 .ngpio = S5P6450_GPIO_N_NR,
1570 .label = "GPN",
1571 },
1572 }, {
1573 .base = S5P64X0_GPP_BASE,
1574 .config = &samsung_gpio_cfgs[6],
1575 .chip = {
1576 .base = S5P6450_GPP(0),
1577 .ngpio = S5P6450_GPIO_P_NR,
1578 .label = "GPP",
1579 },
1580 }, {
1581 .base = S5P6450_GPQ_BASE,
1582 .config = &samsung_gpio_cfgs[5],
1583 .chip = {
1584 .base = S5P6450_GPQ(0),
1585 .ngpio = S5P6450_GPIO_Q_NR,
1586 .label = "GPQ",
1587 },
1588 }, {
1589 .base = S5P6450_GPS_BASE,
1590 .config = &samsung_gpio_cfgs[6],
1591 .chip = {
1592 .base = S5P6450_GPS(0),
1593 .ngpio = S5P6450_GPIO_S_NR,
1594 .label = "GPS",
1595 },
1596 },
1597#endif
1598};
1599
1600/*
1601 * S5PC100 GPIO bank summary: 1173 * S5PC100 GPIO bank summary:
1602 * 1174 *
1603 * Bank GPIOs Style INT Type 1175 * Bank GPIOs Style INT Type
@@ -2109,24 +1681,6 @@ static __init int samsung_gpiolib_init(void)
2109 S3C64XX_VA_GPIO); 1681 S3C64XX_VA_GPIO);
2110 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, 1682 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2111 ARRAY_SIZE(s3c64xx_gpios_4bit2)); 1683 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2112 } else if (soc_is_s5p6440()) {
2113 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2114 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2115 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2116 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2117 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2118 ARRAY_SIZE(s5p6440_gpios_4bit2));
2119 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2120 ARRAY_SIZE(s5p6440_gpios_rbank));
2121 } else if (soc_is_s5p6450()) {
2122 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2123 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2124 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2125 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2126 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2127 ARRAY_SIZE(s5p6450_gpios_4bit2));
2128 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2129 ARRAY_SIZE(s5p6450_gpios_rbank));
2130 } else if (soc_is_s5pc100()) { 1684 } else if (soc_is_s5pc100()) {
2131 group = 0; 1685 group = 0;
2132 chip = s5pc100_gpios_4bit; 1686 chip = s5pc100_gpios_4bit;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 10:11:34 -0400