PCI: designware: Add dw_pcie prefix before cfg_read/write

The cfg_read/write functions are DesignWare-specific.  Add dw_pcie prefix
to avoid collision in global name space.

Tested-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>

3 files changed, 19 insertions, 13 deletions

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 24beed38ddc7..3de6bfbbe8e9 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
         int ret;
 
         exynos_pcie_sideband_dbi_r_mode(pp, true);
-        ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+        ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
         exynos_pcie_sideband_dbi_r_mode(pp, false);
         return ret;
 }
@@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
         int ret;
 
         exynos_pcie_sideband_dbi_w_mode(pp, true);
-        ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
+        ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
+                        where, size, val);
         exynos_pcie_sideband_dbi_w_mode(pp, false);
         return ret;
 }
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index c85cac009583..fc97f5ace5b5 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -74,7 +74,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
         return sys->private_data;
 }
 
-int cfg_read(void __iomem *addr, int where, int size, u32 *val)
+int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
 {
         *val = readl(addr);
 
@@ -88,7 +88,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
         return PCIBIOS_SUCCESSFUL;
 }
 
-int cfg_write(void __iomem *addr, int where, int size, u32 val)
+int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
 {
         if (size == 4)
                 writel(val, addr);
@@ -126,7 +126,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
         if (pp->ops->rd_own_conf)
                 ret = pp->ops->rd_own_conf(pp, where, size, val);
         else
-                ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+                ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
+                                size, val);
 
         return ret;
 }
@@ -139,8 +140,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
         if (pp->ops->wr_own_conf)
                 ret = pp->ops->wr_own_conf(pp, where, size, val);
         else
-                ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
-                                val);
+                ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
+                                size, val);
 
         return ret;
 }
@@ -574,11 +575,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
         if (bus->parent->number == pp->root_bus_nr) {
                 dw_pcie_prog_viewport_cfg0(pp, busdev);
-                ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
+                ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
+                                val);
                 dw_pcie_prog_viewport_mem_outbound(pp);
         } else {
                 dw_pcie_prog_viewport_cfg1(pp, busdev);
-                ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
+                ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
+                                val);
                 dw_pcie_prog_viewport_io_outbound(pp);
         }
 
@@ -597,11 +600,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
         if (bus->parent->number == pp->root_bus_nr) {
                 dw_pcie_prog_viewport_cfg0(pp, busdev);
-                ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
+                ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
+                                val);
                 dw_pcie_prog_viewport_mem_outbound(pp);
         } else {
                 dw_pcie_prog_viewport_cfg1(pp, busdev);
-                ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
+                ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
+                                val);
                 dw_pcie_prog_viewport_io_outbound(pp);
         }
 
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index c15379be2372..3063b3594d88 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -66,8 +66,8 @@ struct pcie_host_ops {
         void (*host_init)(struct pcie_port *pp);
 };
 
-int cfg_read(void __iomem *addr, int where, int size, u32 *val);
-int cfg_write(void __iomem *addr, int where, int size, u32 val);
+int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
+int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
 void dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);