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authorRobert Jarzmik <robert.jarzmik@free.fr>2014-07-30 16:51:04 -0400
committerMike Turquette <mturquette@linaro.org>2014-09-30 15:45:44 -0400
commit9ff25d7b58d8a4374886843ed3ed21f1ef17bf16 (patch)
treeee9e803afb362003b49fc6ecd8eddcb5e77cb439
parent85fe55c11a410a1e26ad3cf2d7a83adf6d019d5d (diff)
arm: pxa: Transition pxa27x to clk framework
Transition the PXA27x CPUs to the clock framework. This transition still enables legacy platforms to run without device tree as before, ie relying on platform data encoded in board specific files. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-pxa/Makefile9
-rw-r--r--arch/arm/mach-pxa/pxa27x.c186
3 files changed, 17 insertions, 179 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c49a775937db..cdfd37d72ff6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -621,6 +621,7 @@ config ARCH_PXA
621 select ARCH_REQUIRE_GPIOLIB 621 select ARCH_REQUIRE_GPIOLIB
622 select ARM_CPU_SUSPEND if PM 622 select ARM_CPU_SUSPEND if PM
623 select AUTO_ZRELADDR 623 select AUTO_ZRELADDR
624 select COMMON_CLK if PXA27x
624 select CLKDEV_LOOKUP 625 select CLKDEV_LOOKUP
625 select CLKSRC_MMIO 626 select CLKSRC_MMIO
626 select CLKSRC_OF 627 select CLKSRC_OF
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 2fe1824c6dcb..f09259a71913 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,16 +3,15 @@
3# 3#
4 4
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o devices.o generic.o irq.o \ 6obj-y += devices.o generic.o irq.o reset.o
7 reset.o
8obj-$(CONFIG_PM) += pm.o sleep.o standby.o 7obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9 8
10# Generic drivers that other drivers may depend upon 9# Generic drivers that other drivers may depend upon
11 10
12# SoC-specific code 11# SoC-specific code
13obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o 12obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o clock.o clock-pxa2xx.o pxa2xx.o pxa25x.o
14obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o 13obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
15obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o 14obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o clock.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
16obj-$(CONFIG_CPU_PXA300) += pxa300.o 15obj-$(CONFIG_CPU_PXA300) += pxa300.o
17obj-$(CONFIG_CPU_PXA320) += pxa320.o 16obj-$(CONFIG_CPU_PXA320) += pxa320.o
18obj-$(CONFIG_CPU_PXA930) += pxa930.o 17obj-$(CONFIG_CPU_PXA930) += pxa930.o
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index b040d7d14888..668087f4e492 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -37,7 +37,8 @@
37 37
38#include "generic.h" 38#include "generic.h"
39#include "devices.h" 39#include "devices.h"
40#include "clock.h" 40#include <linux/clk-provider.h>
41#include <linux/clkdev.h>
41 42
42void pxa27x_clear_otgph(void) 43void pxa27x_clear_otgph(void)
43{ 44{
@@ -73,174 +74,6 @@ void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
73} 74}
74EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset); 75EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
75 76
76/* Crystal clock: 13MHz */
77#define BASE_CLK 13000000
78
79/*
80 * Get the clock frequency as reflected by CCSR and the turbo flag.
81 * We assume these values have been applied via a fcs.
82 * If info is not 0 we also display the current settings.
83 */
84unsigned int pxa27x_get_clk_frequency_khz(int info)
85{
86 unsigned long ccsr, clkcfg;
87 unsigned int l, L, m, M, n2, N, S;
88 int cccr_a, t, ht, b;
89
90 ccsr = CCSR;
91 cccr_a = CCCR & (1 << 25);
92
93 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
94 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
95 t = clkcfg & (1 << 0);
96 ht = clkcfg & (1 << 2);
97 b = clkcfg & (1 << 3);
98
99 l = ccsr & 0x1f;
100 n2 = (ccsr>>7) & 0xf;
101 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
102
103 L = l * BASE_CLK;
104 N = (L * n2) / 2;
105 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
106 S = (b) ? L : (L/2);
107
108 if (info) {
109 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
110 L / 1000000, (L % 1000000) / 10000, l );
111 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
112 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
113 (t) ? "" : "in" );
114 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
115 M / 1000000, (M % 1000000) / 10000, m );
116 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
117 S / 1000000, (S % 1000000) / 10000 );
118 }
119
120 return (t) ? (N/1000) : (L/1000);
121}
122
123/*
124 * Return the current mem clock frequency as reflected by CCCR[A], B, and L
125 */
126static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
127{
128 unsigned long ccsr, clkcfg;
129 unsigned int l, L, m, M;
130 int cccr_a, b;
131
132 ccsr = CCSR;
133 cccr_a = CCCR & (1 << 25);
134
135 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
136 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
137 b = clkcfg & (1 << 3);
138
139 l = ccsr & 0x1f;
140 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
141
142 L = l * BASE_CLK;
143 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
144
145 return M;
146}
147
148static const struct clkops clk_pxa27x_mem_ops = {
149 .enable = clk_dummy_enable,
150 .disable = clk_dummy_disable,
151 .getrate = clk_pxa27x_mem_getrate,
152};
153
154/*
155 * Return the current LCD clock frequency in units of 10kHz as
156 */
157static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
158{
159 unsigned long ccsr;
160 unsigned int l, L, k, K;
161
162 ccsr = CCSR;
163
164 l = ccsr & 0x1f;
165 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
166
167 L = l * BASE_CLK;
168 K = L / k;
169
170 return (K / 10000);
171}
172
173static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
174{
175 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
176}
177
178static const struct clkops clk_pxa27x_lcd_ops = {
179 .enable = clk_pxa2xx_cken_enable,
180 .disable = clk_pxa2xx_cken_disable,
181 .getrate = clk_pxa27x_lcd_getrate,
182};
183
184static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
185static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
186static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
187static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
188static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
189static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
190static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
191static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
192static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
193static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
194static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
195static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
196static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
197static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
198static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
199static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
200static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
201static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
202static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
203static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
204static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
205static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
206static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
207
208static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
209static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
210static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
211
212static struct clk_lookup pxa27x_clkregs[] = {
213 INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
214 INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
215 INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
216 INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
217 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
218 INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
219 INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
220 INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
221 INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
222 INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
223 INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
224 INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
225 INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
226 INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
227 INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
228 INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
229 INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
230 INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
231 INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
232 INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
233 INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
234 INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
235 INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
236 INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
237 INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
238 INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
239 INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
240 INIT_CLKREG(&clk_dummy, "pxa27x-gpio", NULL),
241 INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
242};
243
244#ifdef CONFIG_PM 77#ifdef CONFIG_PM
245 78
246#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 79#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
@@ -460,8 +293,6 @@ static int __init pxa27x_init(void)
460 293
461 reset_status = RCSR; 294 reset_status = RCSR;
462 295
463 clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
464
465 if ((ret = pxa_init_dma(IRQ_DMA, 32))) 296 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
466 return ret; 297 return ret;
467 298
@@ -469,10 +300,17 @@ static int __init pxa27x_init(void)
469 300
470 register_syscore_ops(&pxa_irq_syscore_ops); 301 register_syscore_ops(&pxa_irq_syscore_ops);
471 register_syscore_ops(&pxa2xx_mfp_syscore_ops); 302 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
472 register_syscore_ops(&pxa2xx_clock_syscore_ops);
473 303
474 pxa_register_device(&pxa27x_device_gpio, &pxa27x_gpio_info); 304 if (!of_have_populated_dt()) {
475 ret = platform_add_devices(devices, ARRAY_SIZE(devices)); 305 ret = clk_register_clkdev(NULL, NULL,
306 "pxa27x-gpio");
307 if (!ret)
308 pxa_register_device(&pxa27x_device_gpio,
309 &pxa27x_gpio_info);
310 if (!ret)
311 ret = platform_add_devices(devices,
312 ARRAY_SIZE(devices));
313 }
476 } 314 }
477 315
478 return ret; 316 return ret;