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authorMarek Olšák <marek.olsak@amd.com>2013-12-21 20:18:00 -0500
committerAlex Deucher <alexander.deucher@amd.com>2013-12-23 10:03:42 -0500
commit9fadb352ed73edd7801a280b552d33a6040c8721 (patch)
tree6b929ae350635634570b41c7119783b26efe547e
parentd00adcc8ae9e22eca9d8af5f66c59ad9a74c90ec (diff)
drm/radeon: fix render backend setup for SI and CIK
Only the render backends of the first shader engine were enabled. The others were erroneously disabled. Enabling the other render backends improves performance a lot. Unigine Sanctuary on Bonaire: Before: 15 fps After: 90 fps Judging from the fan noise, the GPU was also underclocked when the other render backends were disabled, resulting in horrible performance. The fan is a lot noisy under load now. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
-rw-r--r--drivers/gpu/drm/radeon/cik.c10
-rw-r--r--drivers/gpu/drm/radeon/si.c10
2 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index b43a3a3c9067..138a77646943 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3057,7 +3057,7 @@ static u32 cik_create_bitmask(u32 bit_width)
3057 * Returns the disabled RB bitmask. 3057 * Returns the disabled RB bitmask.
3058 */ 3058 */
3059static u32 cik_get_rb_disabled(struct radeon_device *rdev, 3059static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3060 u32 max_rb_num, u32 se_num, 3060 u32 max_rb_num_per_se,
3061 u32 sh_per_se) 3061 u32 sh_per_se)
3062{ 3062{
3063 u32 data, mask; 3063 u32 data, mask;
@@ -3071,7 +3071,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3071 3071
3072 data >>= BACKEND_DISABLE_SHIFT; 3072 data >>= BACKEND_DISABLE_SHIFT;
3073 3073
3074 mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se); 3074 mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
3075 3075
3076 return data & mask; 3076 return data & mask;
3077} 3077}
@@ -3088,7 +3088,7 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3088 */ 3088 */
3089static void cik_setup_rb(struct radeon_device *rdev, 3089static void cik_setup_rb(struct radeon_device *rdev,
3090 u32 se_num, u32 sh_per_se, 3090 u32 se_num, u32 sh_per_se,
3091 u32 max_rb_num) 3091 u32 max_rb_num_per_se)
3092{ 3092{
3093 int i, j; 3093 int i, j;
3094 u32 data, mask; 3094 u32 data, mask;
@@ -3098,7 +3098,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
3098 for (i = 0; i < se_num; i++) { 3098 for (i = 0; i < se_num; i++) {
3099 for (j = 0; j < sh_per_se; j++) { 3099 for (j = 0; j < sh_per_se; j++) {
3100 cik_select_se_sh(rdev, i, j); 3100 cik_select_se_sh(rdev, i, j);
3101 data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); 3101 data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3102 if (rdev->family == CHIP_HAWAII) 3102 if (rdev->family == CHIP_HAWAII)
3103 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH); 3103 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3104 else 3104 else
@@ -3108,7 +3108,7 @@ static void cik_setup_rb(struct radeon_device *rdev,
3108 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff); 3108 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3109 3109
3110 mask = 1; 3110 mask = 1;
3111 for (i = 0; i < max_rb_num; i++) { 3111 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3112 if (!(disabled_rbs & mask)) 3112 if (!(disabled_rbs & mask))
3113 enabled_rbs |= mask; 3113 enabled_rbs |= mask;
3114 mask <<= 1; 3114 mask <<= 1;
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a36736dab5e0..3eed9a1e44ea 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2811,7 +2811,7 @@ static void si_setup_spi(struct radeon_device *rdev,
2811} 2811}
2812 2812
2813static u32 si_get_rb_disabled(struct radeon_device *rdev, 2813static u32 si_get_rb_disabled(struct radeon_device *rdev,
2814 u32 max_rb_num, u32 se_num, 2814 u32 max_rb_num_per_se,
2815 u32 sh_per_se) 2815 u32 sh_per_se)
2816{ 2816{
2817 u32 data, mask; 2817 u32 data, mask;
@@ -2825,14 +2825,14 @@ static u32 si_get_rb_disabled(struct radeon_device *rdev,
2825 2825
2826 data >>= BACKEND_DISABLE_SHIFT; 2826 data >>= BACKEND_DISABLE_SHIFT;
2827 2827
2828 mask = si_create_bitmask(max_rb_num / se_num / sh_per_se); 2828 mask = si_create_bitmask(max_rb_num_per_se / sh_per_se);
2829 2829
2830 return data & mask; 2830 return data & mask;
2831} 2831}
2832 2832
2833static void si_setup_rb(struct radeon_device *rdev, 2833static void si_setup_rb(struct radeon_device *rdev,
2834 u32 se_num, u32 sh_per_se, 2834 u32 se_num, u32 sh_per_se,
2835 u32 max_rb_num) 2835 u32 max_rb_num_per_se)
2836{ 2836{
2837 int i, j; 2837 int i, j;
2838 u32 data, mask; 2838 u32 data, mask;
@@ -2842,14 +2842,14 @@ static void si_setup_rb(struct radeon_device *rdev,
2842 for (i = 0; i < se_num; i++) { 2842 for (i = 0; i < se_num; i++) {
2843 for (j = 0; j < sh_per_se; j++) { 2843 for (j = 0; j < sh_per_se; j++) {
2844 si_select_se_sh(rdev, i, j); 2844 si_select_se_sh(rdev, i, j);
2845 data = si_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se); 2845 data = si_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
2846 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH); 2846 disabled_rbs |= data << ((i * sh_per_se + j) * TAHITI_RB_BITMAP_WIDTH_PER_SH);
2847 } 2847 }
2848 } 2848 }
2849 si_select_se_sh(rdev, 0xffffffff, 0xffffffff); 2849 si_select_se_sh(rdev, 0xffffffff, 0xffffffff);
2850 2850
2851 mask = 1; 2851 mask = 1;
2852 for (i = 0; i < max_rb_num; i++) { 2852 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
2853 if (!(disabled_rbs & mask)) 2853 if (!(disabled_rbs & mask))
2854 enabled_rbs |= mask; 2854 enabled_rbs |= mask;
2855 mask <<= 1; 2855 mask <<= 1;