diff options
| author | Marek Vasut <marex@denx.de> | 2013-04-21 17:30:06 -0400 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-06-17 04:04:15 -0400 |
| commit | 9f7fbb150fc6d2ee8391f55409b364e990c67240 (patch) | |
| tree | be792d45d9434e99a3339c3627b86c33460d2738 | |
| parent | efee5e14b09f19864daa9a27cbabec50f18d72ac (diff) | |
ARM: mx5: Add LCD IPU pinctrl data
This patch adds pinmux for IPU LCD 1 and IPU LVDS.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index c132481ab6f9..b298025fdeef 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -508,6 +508,62 @@ | |||
| 508 | }; | 508 | }; |
| 509 | }; | 509 | }; |
| 510 | 510 | ||
| 511 | ipu_disp1 { | ||
| 512 | pinctrl_ipu_disp1_1: ipudisp1grp-1 { | ||
| 513 | fsl,pins = < | ||
| 514 | MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5 | ||
| 515 | MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5 | ||
| 516 | MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5 | ||
| 517 | MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5 | ||
| 518 | MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5 | ||
| 519 | MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5 | ||
| 520 | MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5 | ||
| 521 | MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5 | ||
| 522 | MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5 | ||
| 523 | MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5 | ||
| 524 | MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5 | ||
| 525 | MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5 | ||
| 526 | MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5 | ||
| 527 | MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5 | ||
| 528 | MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5 | ||
| 529 | MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5 | ||
| 530 | MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5 | ||
| 531 | MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5 | ||
| 532 | MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5 | ||
| 533 | MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5 | ||
| 534 | MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5 | ||
| 535 | MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5 | ||
| 536 | MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5 | ||
| 537 | MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5 | ||
| 538 | MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5 | ||
| 539 | MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5 | ||
| 540 | MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5 | ||
| 541 | MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5 | ||
| 542 | MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5 | ||
| 543 | MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5 | ||
| 544 | MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5 | ||
| 545 | MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5 | ||
| 546 | >; | ||
| 547 | }; | ||
| 548 | }; | ||
| 549 | |||
| 550 | ipu_disp2 { | ||
| 551 | pinctrl_ipu_disp2_1: ipudisp2grp-1 { | ||
| 552 | fsl,pins = < | ||
| 553 | MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 | ||
| 554 | MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 | ||
| 555 | MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 | ||
| 556 | MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 | ||
| 557 | MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 | ||
| 558 | MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000 | ||
| 559 | MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000 | ||
| 560 | MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000 | ||
| 561 | MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000 | ||
| 562 | MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000 | ||
| 563 | >; | ||
| 564 | }; | ||
| 565 | }; | ||
| 566 | |||
| 511 | nand { | 567 | nand { |
| 512 | pinctrl_nand_1: nandgrp-1 { | 568 | pinctrl_nand_1: nandgrp-1 { |
| 513 | fsl,pins = < | 569 | fsl,pins = < |