diff options
author | Felipe Balbi <felipe.balbi@nokia.com> | 2008-09-19 21:14:02 -0400 |
---|---|---|
committer | Wim Van Sebroeck <wim@iguana.be> | 2008-10-10 09:11:44 -0400 |
commit | 9f69e3b0c22200998caa73b23a39c03950b2752d (patch) | |
tree | 005c2d3b5aafe0ae4b950eabb56fbdf6c8ae85f5 | |
parent | 2817142f31bfbf26c216bf4f9192540c81b2d071 (diff) |
[WATCHDOG] omap_wdt.c: another ioremap() fix
convert to use ioremap() and __raw_{read/write} friends.
Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com>
Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
-rw-r--r-- | drivers/watchdog/omap_wdt.c | 50 |
1 files changed, 29 insertions, 21 deletions
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7de16a3f6849..9c389b16497f 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c | |||
@@ -71,12 +71,12 @@ static void omap_wdt_ping(struct omap_wdt_dev *wdev) | |||
71 | { | 71 | { |
72 | void __iomem *base = wdev->base; | 72 | void __iomem *base = wdev->base; |
73 | /* wait for posted write to complete */ | 73 | /* wait for posted write to complete */ |
74 | while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) | 74 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
75 | cpu_relax(); | 75 | cpu_relax(); |
76 | wdt_trgr_pattern = ~wdt_trgr_pattern; | 76 | wdt_trgr_pattern = ~wdt_trgr_pattern; |
77 | omap_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); | 77 | __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); |
78 | /* wait for posted write to complete */ | 78 | /* wait for posted write to complete */ |
79 | while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) | 79 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
80 | cpu_relax(); | 80 | cpu_relax(); |
81 | /* reloaded WCRR from WLDR */ | 81 | /* reloaded WCRR from WLDR */ |
82 | } | 82 | } |
@@ -86,11 +86,11 @@ static void omap_wdt_enable(struct omap_wdt_dev *wdev) | |||
86 | void __iomem *base; | 86 | void __iomem *base; |
87 | base = wdev->base; | 87 | base = wdev->base; |
88 | /* Sequence to enable the watchdog */ | 88 | /* Sequence to enable the watchdog */ |
89 | omap_writel(0xBBBB, base + OMAP_WATCHDOG_SPR); | 89 | __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR); |
90 | while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | 90 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) |
91 | cpu_relax(); | 91 | cpu_relax(); |
92 | omap_writel(0x4444, base + OMAP_WATCHDOG_SPR); | 92 | __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR); |
93 | while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | 93 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) |
94 | cpu_relax(); | 94 | cpu_relax(); |
95 | } | 95 | } |
96 | 96 | ||
@@ -99,11 +99,11 @@ static void omap_wdt_disable(struct omap_wdt_dev *wdev) | |||
99 | void __iomem *base; | 99 | void __iomem *base; |
100 | base = wdev->base; | 100 | base = wdev->base; |
101 | /* sequence required to disable watchdog */ | 101 | /* sequence required to disable watchdog */ |
102 | omap_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ | 102 | __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
103 | while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | 103 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) |
104 | cpu_relax(); | 104 | cpu_relax(); |
105 | omap_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ | 105 | __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
106 | while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | 106 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) |
107 | cpu_relax(); | 107 | cpu_relax(); |
108 | } | 108 | } |
109 | 109 | ||
@@ -123,10 +123,10 @@ static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev) | |||
123 | base = wdev->base; | 123 | base = wdev->base; |
124 | 124 | ||
125 | /* just count up at 32 KHz */ | 125 | /* just count up at 32 KHz */ |
126 | while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x04) | 126 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) |
127 | cpu_relax(); | 127 | cpu_relax(); |
128 | omap_writel(pre_margin, base + OMAP_WATCHDOG_LDR); | 128 | __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR); |
129 | while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x04) | 129 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) |
130 | cpu_relax(); | 130 | cpu_relax(); |
131 | } | 131 | } |
132 | 132 | ||
@@ -152,10 +152,10 @@ static int omap_wdt_open(struct inode *inode, struct file *file) | |||
152 | } | 152 | } |
153 | 153 | ||
154 | /* initialize prescaler */ | 154 | /* initialize prescaler */ |
155 | while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | 155 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
156 | cpu_relax(); | 156 | cpu_relax(); |
157 | omap_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); | 157 | __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); |
158 | while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | 158 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
159 | cpu_relax(); | 159 | cpu_relax(); |
160 | 160 | ||
161 | file->private_data = (void *) wdev; | 161 | file->private_data = (void *) wdev; |
@@ -224,7 +224,7 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd, | |||
224 | return put_user(0, (int __user *)arg); | 224 | return put_user(0, (int __user *)arg); |
225 | case WDIOC_GETBOOTSTATUS: | 225 | case WDIOC_GETBOOTSTATUS: |
226 | if (cpu_is_omap16xx()) | 226 | if (cpu_is_omap16xx()) |
227 | return put_user(omap_readw(ARM_SYSST), | 227 | return put_user(__raw_readw(ARM_SYSST), |
228 | (int __user *)arg); | 228 | (int __user *)arg); |
229 | if (cpu_is_omap24xx()) | 229 | if (cpu_is_omap24xx()) |
230 | return put_user(omap_prcm_get_reset_sources(), | 230 | return put_user(omap_prcm_get_reset_sources(), |
@@ -328,7 +328,12 @@ static int __init omap_wdt_probe(struct platform_device *pdev) | |||
328 | goto fail; | 328 | goto fail; |
329 | } | 329 | } |
330 | } | 330 | } |
331 | wdev->base = (void __iomem *) (mem->start); | 331 | wdev->base = ioremap(res->start, res->end - res->start + 1); |
332 | if (!wdev->base) { | ||
333 | ret = -ENOMEM; | ||
334 | goto fail; | ||
335 | } | ||
336 | |||
332 | platform_set_drvdata(pdev, wdev); | 337 | platform_set_drvdata(pdev, wdev); |
333 | 338 | ||
334 | omap_wdt_disable(wdev); | 339 | omap_wdt_disable(wdev); |
@@ -344,11 +349,11 @@ static int __init omap_wdt_probe(struct platform_device *pdev) | |||
344 | goto fail; | 349 | goto fail; |
345 | 350 | ||
346 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", | 351 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", |
347 | omap_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, | 352 | __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, |
348 | timer_margin); | 353 | timer_margin); |
349 | 354 | ||
350 | /* autogate OCP interface clock */ | 355 | /* autogate OCP interface clock */ |
351 | omap_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG); | 356 | __raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG); |
352 | 357 | ||
353 | omap_wdt_dev = pdev; | 358 | omap_wdt_dev = pdev; |
354 | 359 | ||
@@ -363,6 +368,7 @@ fail: | |||
363 | clk_put(wdev->mpu_wdt_ick); | 368 | clk_put(wdev->mpu_wdt_ick); |
364 | if (wdev->mpu_wdt_fck) | 369 | if (wdev->mpu_wdt_fck) |
365 | clk_put(wdev->mpu_wdt_fck); | 370 | clk_put(wdev->mpu_wdt_fck); |
371 | iounmap(wdev->base); | ||
366 | kfree(wdev); | 372 | kfree(wdev); |
367 | } | 373 | } |
368 | if (mem) { | 374 | if (mem) { |
@@ -404,6 +410,8 @@ static int omap_wdt_remove(struct platform_device *pdev) | |||
404 | clk_put(wdev->mpu_wdt_fck); | 410 | clk_put(wdev->mpu_wdt_fck); |
405 | wdev->mpu_wdt_fck = NULL; | 411 | wdev->mpu_wdt_fck = NULL; |
406 | } | 412 | } |
413 | iounmap(wdev->base); | ||
414 | |||
407 | kfree(wdev); | 415 | kfree(wdev); |
408 | omap_wdt_dev = NULL; | 416 | omap_wdt_dev = NULL; |
409 | return 0; | 417 | return 0; |