drm/i915: Replace ironlake_compute_wm0 with g4x_compute_wm0

The computation of the first-level watermarks for g4x and gen5+ are
based on the same algorithm, so we can refactor those code paths to
use a single function.

Note that g4x_compute_wm0 takes a 'plane' argument while
ironlake_compute_wm0 took a 'pipe' argument. Both should have used a
'plane' argument, so this patch fixes that as well (not that it caused
a problem; ironlake always uses pipe == plane).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

1 files changed, 20 insertions, 68 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bb1b59b3d12d..81a9059b6a94 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3983,54 +3983,6 @@ static void i830_update_wm(struct drm_device *dev)
 #define ILK_LP0_PLANE_LATENCY           700
 #define ILK_LP0_CURSOR_LATENCY          1300
 
-static bool ironlake_compute_wm0(struct drm_device *dev,
-                                 int pipe,
-                                 const struct intel_watermark_params *display,
-                                 int display_latency_ns,
-                                 const struct intel_watermark_params *cursor,
-                                 int cursor_latency_ns,
-                                 int *plane_wm,
-                                 int *cursor_wm)
-{
-        struct drm_crtc *crtc;
-        int htotal, hdisplay, clock, pixel_size;
-        int line_time_us, line_count;
-        int entries, tlb_miss;
-
-        crtc = intel_get_crtc_for_pipe(dev, pipe);
-        if (crtc->fb == NULL || !crtc->enabled)
-                return false;
-
-        htotal = crtc->mode.htotal;
-        hdisplay = crtc->mode.hdisplay;
-        clock = crtc->mode.clock;
-        pixel_size = crtc->fb->bits_per_pixel / 8;
-
-        /* Use the small buffer method to calculate plane watermark */
-        entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
-        tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
-        if (tlb_miss > 0)
-                entries += tlb_miss;
-        entries = DIV_ROUND_UP(entries, display->cacheline_size);
-        *plane_wm = entries + display->guard_size;
-        if (*plane_wm > (int)display->max_wm)
-                *plane_wm = display->max_wm;
-
-        /* Use the large buffer method to calculate cursor watermark */
-        line_time_us = ((htotal * 1000) / clock);
-        line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
-        entries = line_count * 64 * pixel_size;
-        tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
-        if (tlb_miss > 0)
-                entries += tlb_miss;
-        entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
-        *cursor_wm = entries + cursor->guard_size;
-        if (*cursor_wm > (int)cursor->max_wm)
-                *cursor_wm = (int)cursor->max_wm;
-
-        return true;
-}
-
 /*
  * Check the wm result.
  *
@@ -4139,12 +4091,12 @@ static void ironlake_update_wm(struct drm_device *dev)
         unsigned int enabled;
 
         enabled = 0;
-        if (ironlake_compute_wm0(dev, 0,
-                                 &ironlake_display_wm_info,
-                                 ILK_LP0_PLANE_LATENCY,
-                                 &ironlake_cursor_wm_info,
-                                 ILK_LP0_CURSOR_LATENCY,
-                                 &plane_wm, &cursor_wm)) {
+        if (g4x_compute_wm0(dev, 0,
+                            &ironlake_display_wm_info,
+                            ILK_LP0_PLANE_LATENCY,
+                            &ironlake_cursor_wm_info,
+                            ILK_LP0_CURSOR_LATENCY,
+                            &plane_wm, &cursor_wm)) {
                 I915_WRITE(WM0_PIPEA_ILK,
                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
@@ -4153,12 +4105,12 @@ static void ironlake_update_wm(struct drm_device *dev)
                 enabled |= 1;
         }
 
-        if (ironlake_compute_wm0(dev, 1,
-                                 &ironlake_display_wm_info,
-                                 ILK_LP0_PLANE_LATENCY,
-                                 &ironlake_cursor_wm_info,
-                                 ILK_LP0_CURSOR_LATENCY,
-                                 &plane_wm, &cursor_wm)) {
+        if (g4x_compute_wm0(dev, 1,
+                            &ironlake_display_wm_info,
+                            ILK_LP0_PLANE_LATENCY,
+                            &ironlake_cursor_wm_info,
+                            ILK_LP0_CURSOR_LATENCY,
+                            &plane_wm, &cursor_wm)) {
                 I915_WRITE(WM0_PIPEB_ILK,
                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
@@ -4223,10 +4175,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
         unsigned int enabled;
 
         enabled = 0;
-        if (ironlake_compute_wm0(dev, 0,
-                                 &sandybridge_display_wm_info, latency,
-                                 &sandybridge_cursor_wm_info, latency,
-                                 &plane_wm, &cursor_wm)) {
+        if (g4x_compute_wm0(dev, 0,
+                            &sandybridge_display_wm_info, latency,
+                            &sandybridge_cursor_wm_info, latency,
+                            &plane_wm, &cursor_wm)) {
                 I915_WRITE(WM0_PIPEA_ILK,
                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
@@ -4235,10 +4187,10 @@ static void sandybridge_update_wm(struct drm_device *dev)
                 enabled |= 1;
         }
 
-        if (ironlake_compute_wm0(dev, 1,
-                                 &sandybridge_display_wm_info, latency,
-                                 &sandybridge_cursor_wm_info, latency,
-                                 &plane_wm, &cursor_wm)) {
+        if (g4x_compute_wm0(dev, 1,
+                            &sandybridge_display_wm_info, latency,
+                            &sandybridge_cursor_wm_info, latency,
+                            &plane_wm, &cursor_wm)) {
                 I915_WRITE(WM0_PIPEB_ILK,
                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"