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authorArnd Bergmann <arnd@arndb.de>2013-04-10 20:04:48 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-04-11 16:14:36 -0400
commit9ee51f01eee84a108510ac2794b9a9dff8be6d3f (patch)
tree56a7520690660719fc2bc05da8a89d14fd28cbb1
parent17efd2b7867b5ee1076d3c9ae5a6c937907d9198 (diff)
tty: serial/samsung: make register definitions global
The registers for the Samsung S3C serial port are currently defined in the platform specific arch/arm/plat-samsung/include/plat/regs-serial.h file, which is not visible to multiplatform capable drivers. Unfortunately, it is not possible to move the file into a more local place as we should normally try to, because the same registers may be used in one of four places: * In the driver itself * In platform-independent ARM code for early debug output * In platform_data definitions * In the Samsung platform power management code I have also found no way to logically split out a platform_data file, other than possibly move everything into include/linux/platform_data, which also felt wrong. The only part of this file that makes sense to keep specific to the s3c24xx platform are the virtual and physical addresses defined here, which are needed in no other location. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat
-rw-r--r--arch/arm/mach-s3c24xx/clock-s3c2440.c5
-rw-r--r--arch/arm/mach-s3c24xx/common.c5
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-serial.h282
-rw-r--r--drivers/tty/serial/samsung.c6
-rw-r--r--include/linux/serial_s3c.h260
5 files changed, 274 insertions, 284 deletions
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 04b87ec92537..1069b5680826 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -123,6 +123,11 @@ static struct clk s3c2440_clk_ac97 = {
123 .ctrlbit = S3C2440_CLKCON_AC97, 123 .ctrlbit = S3C2440_CLKCON_AC97,
124}; 124};
125 125
126#define S3C24XX_VA_UART0 (S3C_VA_UART)
127#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
128#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
129#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
130
126static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) 131static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
127{ 132{
128 unsigned long ucon0, ucon1, ucon2, divisor; 133 unsigned long ucon0, ucon1, ucon2, divisor;
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 6bcf87f65f9e..92e609440c57 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -239,6 +239,11 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
239 239
240/* Serial port registrations */ 240/* Serial port registrations */
241 241
242#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
243#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
244#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
245#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
246
242static struct resource s3c2410_uart0_resource[] = { 247static struct resource s3c2410_uart0_resource[] = {
243 [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K), 248 [0] = DEFINE_RES_MEM(S3C2410_PA_UART0, SZ_16K),
244 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \ 249 [1] = DEFINE_RES_NAMED(IRQ_S3CUART_RX0, \
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 29c26a818842..f05f2afa440d 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -1,281 +1 @@
1/* arch/arm/plat-samsung/include/plat/regs-serial.h #include <linux/serial_s3c.h>
2 *
3 * From linux/include/asm-arm/hardware/serial_s3c2410.h
4 *
5 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
6 *
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 *
9 * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
10 *
11 * Adapted from:
12 *
13 * Internal header file for MX1ADS serial ports (UART1 & 2)
14 *
15 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30*/
31
32#ifndef __ASM_ARM_REGS_SERIAL_H
33#define __ASM_ARM_REGS_SERIAL_H
34
35#define S3C24XX_VA_UART0 (S3C_VA_UART)
36#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
37#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
38#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
39
40#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
42#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
43#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
44
45#define S3C2410_URXH (0x24)
46#define S3C2410_UTXH (0x20)
47#define S3C2410_ULCON (0x00)
48#define S3C2410_UCON (0x04)
49#define S3C2410_UFCON (0x08)
50#define S3C2410_UMCON (0x0C)
51#define S3C2410_UBRDIV (0x28)
52#define S3C2410_UTRSTAT (0x10)
53#define S3C2410_UERSTAT (0x14)
54#define S3C2410_UFSTAT (0x18)
55#define S3C2410_UMSTAT (0x1C)
56
57#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
58
59#define S3C2410_LCON_CS5 (0x0)
60#define S3C2410_LCON_CS6 (0x1)
61#define S3C2410_LCON_CS7 (0x2)
62#define S3C2410_LCON_CS8 (0x3)
63#define S3C2410_LCON_CSMASK (0x3)
64
65#define S3C2410_LCON_PNONE (0x0)
66#define S3C2410_LCON_PEVEN (0x5 << 3)
67#define S3C2410_LCON_PODD (0x4 << 3)
68#define S3C2410_LCON_PMASK (0x7 << 3)
69
70#define S3C2410_LCON_STOPB (1<<2)
71#define S3C2410_LCON_IRM (1<<6)
72
73#define S3C2440_UCON_CLKMASK (3<<10)
74#define S3C2440_UCON_CLKSHIFT (10)
75#define S3C2440_UCON_PCLK (0<<10)
76#define S3C2440_UCON_UCLK (1<<10)
77#define S3C2440_UCON_PCLK2 (2<<10)
78#define S3C2440_UCON_FCLK (3<<10)
79#define S3C2443_UCON_EPLL (3<<10)
80
81#define S3C6400_UCON_CLKMASK (3<<10)
82#define S3C6400_UCON_CLKSHIFT (10)
83#define S3C6400_UCON_PCLK (0<<10)
84#define S3C6400_UCON_PCLK2 (2<<10)
85#define S3C6400_UCON_UCLK0 (1<<10)
86#define S3C6400_UCON_UCLK1 (3<<10)
87
88#define S3C2440_UCON2_FCLK_EN (1<<15)
89#define S3C2440_UCON0_DIVMASK (15 << 12)
90#define S3C2440_UCON1_DIVMASK (15 << 12)
91#define S3C2440_UCON2_DIVMASK (7 << 12)
92#define S3C2440_UCON_DIVSHIFT (12)
93
94#define S3C2412_UCON_CLKMASK (3<<10)
95#define S3C2412_UCON_CLKSHIFT (10)
96#define S3C2412_UCON_UCLK (1<<10)
97#define S3C2412_UCON_USYSCLK (3<<10)
98#define S3C2412_UCON_PCLK (0<<10)
99#define S3C2412_UCON_PCLK2 (2<<10)
100
101#define S3C2410_UCON_CLKMASK (1 << 10)
102#define S3C2410_UCON_CLKSHIFT (10)
103#define S3C2410_UCON_UCLK (1<<10)
104#define S3C2410_UCON_SBREAK (1<<4)
105
106#define S3C2410_UCON_TXILEVEL (1<<9)
107#define S3C2410_UCON_RXILEVEL (1<<8)
108#define S3C2410_UCON_TXIRQMODE (1<<2)
109#define S3C2410_UCON_RXIRQMODE (1<<0)
110#define S3C2410_UCON_RXFIFO_TOI (1<<7)
111#define S3C2443_UCON_RXERR_IRQEN (1<<6)
112#define S3C2443_UCON_LOOPBACK (1<<5)
113
114#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
115 S3C2410_UCON_RXILEVEL | \
116 S3C2410_UCON_TXIRQMODE | \
117 S3C2410_UCON_RXIRQMODE | \
118 S3C2410_UCON_RXFIFO_TOI)
119
120#define S3C2410_UFCON_FIFOMODE (1<<0)
121#define S3C2410_UFCON_TXTRIG0 (0<<6)
122#define S3C2410_UFCON_RXTRIG8 (1<<4)
123#define S3C2410_UFCON_RXTRIG12 (2<<4)
124
125/* S3C2440 FIFO trigger levels */
126#define S3C2440_UFCON_RXTRIG1 (0<<4)
127#define S3C2440_UFCON_RXTRIG8 (1<<4)
128#define S3C2440_UFCON_RXTRIG16 (2<<4)
129#define S3C2440_UFCON_RXTRIG32 (3<<4)
130
131#define S3C2440_UFCON_TXTRIG0 (0<<6)
132#define S3C2440_UFCON_TXTRIG16 (1<<6)
133#define S3C2440_UFCON_TXTRIG32 (2<<6)
134#define S3C2440_UFCON_TXTRIG48 (3<<6)
135
136#define S3C2410_UFCON_RESETBOTH (3<<1)
137#define S3C2410_UFCON_RESETTX (1<<2)
138#define S3C2410_UFCON_RESETRX (1<<1)
139
140#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
141 S3C2410_UFCON_TXTRIG0 | \
142 S3C2410_UFCON_RXTRIG8 )
143
144#define S3C2410_UMCOM_AFC (1<<4)
145#define S3C2410_UMCOM_RTS_LOW (1<<0)
146
147#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
148#define S3C2412_UMCON_AFC_56 (1<<5)
149#define S3C2412_UMCON_AFC_48 (2<<5)
150#define S3C2412_UMCON_AFC_40 (3<<5)
151#define S3C2412_UMCON_AFC_32 (4<<5)
152#define S3C2412_UMCON_AFC_24 (5<<5)
153#define S3C2412_UMCON_AFC_16 (6<<5)
154#define S3C2412_UMCON_AFC_8 (7<<5)
155
156#define S3C2410_UFSTAT_TXFULL (1<<9)
157#define S3C2410_UFSTAT_RXFULL (1<<8)
158#define S3C2410_UFSTAT_TXMASK (15<<4)
159#define S3C2410_UFSTAT_TXSHIFT (4)
160#define S3C2410_UFSTAT_RXMASK (15<<0)
161#define S3C2410_UFSTAT_RXSHIFT (0)
162
163/* UFSTAT S3C2443 same as S3C2440 */
164#define S3C2440_UFSTAT_TXFULL (1<<14)
165#define S3C2440_UFSTAT_RXFULL (1<<6)
166#define S3C2440_UFSTAT_TXSHIFT (8)
167#define S3C2440_UFSTAT_RXSHIFT (0)
168#define S3C2440_UFSTAT_TXMASK (63<<8)
169#define S3C2440_UFSTAT_RXMASK (63)
170
171#define S3C2410_UTRSTAT_TXE (1<<2)
172#define S3C2410_UTRSTAT_TXFE (1<<1)
173#define S3C2410_UTRSTAT_RXDR (1<<0)
174
175#define S3C2410_UERSTAT_OVERRUN (1<<0)
176#define S3C2410_UERSTAT_FRAME (1<<2)
177#define S3C2410_UERSTAT_BREAK (1<<3)
178#define S3C2443_UERSTAT_PARITY (1<<1)
179
180#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
181 S3C2410_UERSTAT_FRAME | \
182 S3C2410_UERSTAT_BREAK)
183
184#define S3C2410_UMSTAT_CTS (1<<0)
185#define S3C2410_UMSTAT_DeltaCTS (1<<2)
186
187#define S3C2443_DIVSLOT (0x2C)
188
189/* S3C64XX interrupt registers. */
190#define S3C64XX_UINTP 0x30
191#define S3C64XX_UINTSP 0x34
192#define S3C64XX_UINTM 0x38
193
194#define S3C64XX_UINTM_RXD (0)
195#define S3C64XX_UINTM_TXD (2)
196#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
197#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
198
199/* Following are specific to S5PV210 */
200#define S5PV210_UCON_CLKMASK (1<<10)
201#define S5PV210_UCON_CLKSHIFT (10)
202#define S5PV210_UCON_PCLK (0<<10)
203#define S5PV210_UCON_UCLK (1<<10)
204
205#define S5PV210_UFCON_TXTRIG0 (0<<8)
206#define S5PV210_UFCON_TXTRIG4 (1<<8)
207#define S5PV210_UFCON_TXTRIG8 (2<<8)
208#define S5PV210_UFCON_TXTRIG16 (3<<8)
209#define S5PV210_UFCON_TXTRIG32 (4<<8)
210#define S5PV210_UFCON_TXTRIG64 (5<<8)
211#define S5PV210_UFCON_TXTRIG128 (6<<8)
212#define S5PV210_UFCON_TXTRIG256 (7<<8)
213
214#define S5PV210_UFCON_RXTRIG1 (0<<4)
215#define S5PV210_UFCON_RXTRIG4 (1<<4)
216#define S5PV210_UFCON_RXTRIG8 (2<<4)
217#define S5PV210_UFCON_RXTRIG16 (3<<4)
218#define S5PV210_UFCON_RXTRIG32 (4<<4)
219#define S5PV210_UFCON_RXTRIG64 (5<<4)
220#define S5PV210_UFCON_RXTRIG128 (6<<4)
221#define S5PV210_UFCON_RXTRIG256 (7<<4)
222
223#define S5PV210_UFSTAT_TXFULL (1<<24)
224#define S5PV210_UFSTAT_RXFULL (1<<8)
225#define S5PV210_UFSTAT_TXMASK (255<<16)
226#define S5PV210_UFSTAT_TXSHIFT (16)
227#define S5PV210_UFSTAT_RXMASK (255<<0)
228#define S5PV210_UFSTAT_RXSHIFT (0)
229
230#define S3C2410_UCON_CLKSEL0 (1 << 0)
231#define S3C2410_UCON_CLKSEL1 (1 << 1)
232#define S3C2410_UCON_CLKSEL2 (1 << 2)
233#define S3C2410_UCON_CLKSEL3 (1 << 3)
234
235/* Default values for s5pv210 UCON and UFCON uart registers */
236#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
237 S3C2410_UCON_RXILEVEL | \
238 S3C2410_UCON_TXIRQMODE | \
239 S3C2410_UCON_RXIRQMODE | \
240 S3C2410_UCON_RXFIFO_TOI | \
241 S3C2443_UCON_RXERR_IRQEN)
242
243#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
244 S5PV210_UFCON_TXTRIG4 | \
245 S5PV210_UFCON_RXTRIG4)
246
247#ifndef __ASSEMBLY__
248
249/* configuration structure for per-machine configurations for the
250 * serial port
251 *
252 * the pointer is setup by the machine specific initialisation from the
253 * arch/arm/mach-s3c2410/ directory.
254*/
255
256struct s3c2410_uartcfg {
257 unsigned char hwport; /* hardware port number */
258 unsigned char unused;
259 unsigned short flags;
260 upf_t uart_flags; /* default uart flags */
261 unsigned int clk_sel;
262
263 unsigned int has_fracval;
264
265 unsigned long ucon; /* value of ucon for port */
266 unsigned long ulcon; /* value of ulcon for port */
267 unsigned long ufcon; /* value of ufcon for port */
268};
269
270/* s3c24xx_uart_devs
271 *
272 * this is exported from the core as we cannot use driver_register(),
273 * or platform_add_device() before the console_initcall()
274*/
275
276extern struct platform_device *s3c24xx_uart_devs[4];
277
278#endif /* __ASSEMBLY__ */
279
280#endif /* __ASM_ARM_REGS_SERIAL_H */
281
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index e91378b40d58..6a3695681fa5 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -39,6 +39,7 @@
39#include <linux/tty_flip.h> 39#include <linux/tty_flip.h>
40#include <linux/serial_core.h> 40#include <linux/serial_core.h>
41#include <linux/serial.h> 41#include <linux/serial.h>
42#include <linux/serial_s3c.h>
42#include <linux/delay.h> 43#include <linux/delay.h>
43#include <linux/clk.h> 44#include <linux/clk.h>
44#include <linux/cpufreq.h> 45#include <linux/cpufreq.h>
@@ -46,10 +47,9 @@
46 47
47#include <asm/irq.h> 48#include <asm/irq.h>
48 49
49#include <mach/hardware.h> 50#ifdef CONFIG_SAMSUNG_CLOCK
50
51#include <plat/regs-serial.h>
52#include <plat/clock.h> 51#include <plat/clock.h>
52#endif
53 53
54#include "samsung.h" 54#include "samsung.h"
55 55
diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
new file mode 100644
index 000000000000..907d9d1d56cf
--- /dev/null
+++ b/include/linux/serial_s3c.h
@@ -0,0 +1,260 @@
1/*
2 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
3 *
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 *
6 * Additional defines, Copyright 2003 Simtec Electronics (linux@simtec.co.uk)
7 *
8 * Adapted from:
9 *
10 * Internal header file for MX1ADS serial ports (UART1 & 2)
11 *
12 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27*/
28
29#ifndef __ASM_ARM_REGS_SERIAL_H
30#define __ASM_ARM_REGS_SERIAL_H
31
32#define S3C2410_URXH (0x24)
33#define S3C2410_UTXH (0x20)
34#define S3C2410_ULCON (0x00)
35#define S3C2410_UCON (0x04)
36#define S3C2410_UFCON (0x08)
37#define S3C2410_UMCON (0x0C)
38#define S3C2410_UBRDIV (0x28)
39#define S3C2410_UTRSTAT (0x10)
40#define S3C2410_UERSTAT (0x14)
41#define S3C2410_UFSTAT (0x18)
42#define S3C2410_UMSTAT (0x1C)
43
44#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
45
46#define S3C2410_LCON_CS5 (0x0)
47#define S3C2410_LCON_CS6 (0x1)
48#define S3C2410_LCON_CS7 (0x2)
49#define S3C2410_LCON_CS8 (0x3)
50#define S3C2410_LCON_CSMASK (0x3)
51
52#define S3C2410_LCON_PNONE (0x0)
53#define S3C2410_LCON_PEVEN (0x5 << 3)
54#define S3C2410_LCON_PODD (0x4 << 3)
55#define S3C2410_LCON_PMASK (0x7 << 3)
56
57#define S3C2410_LCON_STOPB (1<<2)
58#define S3C2410_LCON_IRM (1<<6)
59
60#define S3C2440_UCON_CLKMASK (3<<10)
61#define S3C2440_UCON_CLKSHIFT (10)
62#define S3C2440_UCON_PCLK (0<<10)
63#define S3C2440_UCON_UCLK (1<<10)
64#define S3C2440_UCON_PCLK2 (2<<10)
65#define S3C2440_UCON_FCLK (3<<10)
66#define S3C2443_UCON_EPLL (3<<10)
67
68#define S3C6400_UCON_CLKMASK (3<<10)
69#define S3C6400_UCON_CLKSHIFT (10)
70#define S3C6400_UCON_PCLK (0<<10)
71#define S3C6400_UCON_PCLK2 (2<<10)
72#define S3C6400_UCON_UCLK0 (1<<10)
73#define S3C6400_UCON_UCLK1 (3<<10)
74
75#define S3C2440_UCON2_FCLK_EN (1<<15)
76#define S3C2440_UCON0_DIVMASK (15 << 12)
77#define S3C2440_UCON1_DIVMASK (15 << 12)
78#define S3C2440_UCON2_DIVMASK (7 << 12)
79#define S3C2440_UCON_DIVSHIFT (12)
80
81#define S3C2412_UCON_CLKMASK (3<<10)
82#define S3C2412_UCON_CLKSHIFT (10)
83#define S3C2412_UCON_UCLK (1<<10)
84#define S3C2412_UCON_USYSCLK (3<<10)
85#define S3C2412_UCON_PCLK (0<<10)
86#define S3C2412_UCON_PCLK2 (2<<10)
87
88#define S3C2410_UCON_CLKMASK (1 << 10)
89#define S3C2410_UCON_CLKSHIFT (10)
90#define S3C2410_UCON_UCLK (1<<10)
91#define S3C2410_UCON_SBREAK (1<<4)
92
93#define S3C2410_UCON_TXILEVEL (1<<9)
94#define S3C2410_UCON_RXILEVEL (1<<8)
95#define S3C2410_UCON_TXIRQMODE (1<<2)
96#define S3C2410_UCON_RXIRQMODE (1<<0)
97#define S3C2410_UCON_RXFIFO_TOI (1<<7)
98#define S3C2443_UCON_RXERR_IRQEN (1<<6)
99#define S3C2443_UCON_LOOPBACK (1<<5)
100
101#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
102 S3C2410_UCON_RXILEVEL | \
103 S3C2410_UCON_TXIRQMODE | \
104 S3C2410_UCON_RXIRQMODE | \
105 S3C2410_UCON_RXFIFO_TOI)
106
107#define S3C2410_UFCON_FIFOMODE (1<<0)
108#define S3C2410_UFCON_TXTRIG0 (0<<6)
109#define S3C2410_UFCON_RXTRIG8 (1<<4)
110#define S3C2410_UFCON_RXTRIG12 (2<<4)
111
112/* S3C2440 FIFO trigger levels */
113#define S3C2440_UFCON_RXTRIG1 (0<<4)
114#define S3C2440_UFCON_RXTRIG8 (1<<4)
115#define S3C2440_UFCON_RXTRIG16 (2<<4)
116#define S3C2440_UFCON_RXTRIG32 (3<<4)
117
118#define S3C2440_UFCON_TXTRIG0 (0<<6)
119#define S3C2440_UFCON_TXTRIG16 (1<<6)
120#define S3C2440_UFCON_TXTRIG32 (2<<6)
121#define S3C2440_UFCON_TXTRIG48 (3<<6)
122
123#define S3C2410_UFCON_RESETBOTH (3<<1)
124#define S3C2410_UFCON_RESETTX (1<<2)
125#define S3C2410_UFCON_RESETRX (1<<1)
126
127#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
128 S3C2410_UFCON_TXTRIG0 | \
129 S3C2410_UFCON_RXTRIG8 )
130
131#define S3C2410_UMCOM_AFC (1<<4)
132#define S3C2410_UMCOM_RTS_LOW (1<<0)
133
134#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
135#define S3C2412_UMCON_AFC_56 (1<<5)
136#define S3C2412_UMCON_AFC_48 (2<<5)
137#define S3C2412_UMCON_AFC_40 (3<<5)
138#define S3C2412_UMCON_AFC_32 (4<<5)
139#define S3C2412_UMCON_AFC_24 (5<<5)
140#define S3C2412_UMCON_AFC_16 (6<<5)
141#define S3C2412_UMCON_AFC_8 (7<<5)
142
143#define S3C2410_UFSTAT_TXFULL (1<<9)
144#define S3C2410_UFSTAT_RXFULL (1<<8)
145#define S3C2410_UFSTAT_TXMASK (15<<4)
146#define S3C2410_UFSTAT_TXSHIFT (4)
147#define S3C2410_UFSTAT_RXMASK (15<<0)
148#define S3C2410_UFSTAT_RXSHIFT (0)
149
150/* UFSTAT S3C2443 same as S3C2440 */
151#define S3C2440_UFSTAT_TXFULL (1<<14)
152#define S3C2440_UFSTAT_RXFULL (1<<6)
153#define S3C2440_UFSTAT_TXSHIFT (8)
154#define S3C2440_UFSTAT_RXSHIFT (0)
155#define S3C2440_UFSTAT_TXMASK (63<<8)
156#define S3C2440_UFSTAT_RXMASK (63)
157
158#define S3C2410_UTRSTAT_TXE (1<<2)
159#define S3C2410_UTRSTAT_TXFE (1<<1)
160#define S3C2410_UTRSTAT_RXDR (1<<0)
161
162#define S3C2410_UERSTAT_OVERRUN (1<<0)
163#define S3C2410_UERSTAT_FRAME (1<<2)
164#define S3C2410_UERSTAT_BREAK (1<<3)
165#define S3C2443_UERSTAT_PARITY (1<<1)
166
167#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
168 S3C2410_UERSTAT_FRAME | \
169 S3C2410_UERSTAT_BREAK)
170
171#define S3C2410_UMSTAT_CTS (1<<0)
172#define S3C2410_UMSTAT_DeltaCTS (1<<2)
173
174#define S3C2443_DIVSLOT (0x2C)
175
176/* S3C64XX interrupt registers. */
177#define S3C64XX_UINTP 0x30
178#define S3C64XX_UINTSP 0x34
179#define S3C64XX_UINTM 0x38
180
181#define S3C64XX_UINTM_RXD (0)
182#define S3C64XX_UINTM_TXD (2)
183#define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
184#define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
185
186/* Following are specific to S5PV210 */
187#define S5PV210_UCON_CLKMASK (1<<10)
188#define S5PV210_UCON_CLKSHIFT (10)
189#define S5PV210_UCON_PCLK (0<<10)
190#define S5PV210_UCON_UCLK (1<<10)
191
192#define S5PV210_UFCON_TXTRIG0 (0<<8)
193#define S5PV210_UFCON_TXTRIG4 (1<<8)
194#define S5PV210_UFCON_TXTRIG8 (2<<8)
195#define S5PV210_UFCON_TXTRIG16 (3<<8)
196#define S5PV210_UFCON_TXTRIG32 (4<<8)
197#define S5PV210_UFCON_TXTRIG64 (5<<8)
198#define S5PV210_UFCON_TXTRIG128 (6<<8)
199#define S5PV210_UFCON_TXTRIG256 (7<<8)
200
201#define S5PV210_UFCON_RXTRIG1 (0<<4)
202#define S5PV210_UFCON_RXTRIG4 (1<<4)
203#define S5PV210_UFCON_RXTRIG8 (2<<4)
204#define S5PV210_UFCON_RXTRIG16 (3<<4)
205#define S5PV210_UFCON_RXTRIG32 (4<<4)
206#define S5PV210_UFCON_RXTRIG64 (5<<4)
207#define S5PV210_UFCON_RXTRIG128 (6<<4)
208#define S5PV210_UFCON_RXTRIG256 (7<<4)
209
210#define S5PV210_UFSTAT_TXFULL (1<<24)
211#define S5PV210_UFSTAT_RXFULL (1<<8)
212#define S5PV210_UFSTAT_TXMASK (255<<16)
213#define S5PV210_UFSTAT_TXSHIFT (16)
214#define S5PV210_UFSTAT_RXMASK (255<<0)
215#define S5PV210_UFSTAT_RXSHIFT (0)
216
217#define S3C2410_UCON_CLKSEL0 (1 << 0)
218#define S3C2410_UCON_CLKSEL1 (1 << 1)
219#define S3C2410_UCON_CLKSEL2 (1 << 2)
220#define S3C2410_UCON_CLKSEL3 (1 << 3)
221
222/* Default values for s5pv210 UCON and UFCON uart registers */
223#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
224 S3C2410_UCON_RXILEVEL | \
225 S3C2410_UCON_TXIRQMODE | \
226 S3C2410_UCON_RXIRQMODE | \
227 S3C2410_UCON_RXFIFO_TOI | \
228 S3C2443_UCON_RXERR_IRQEN)
229
230#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
231 S5PV210_UFCON_TXTRIG4 | \
232 S5PV210_UFCON_RXTRIG4)
233
234#ifndef __ASSEMBLY__
235
236/* configuration structure for per-machine configurations for the
237 * serial port
238 *
239 * the pointer is setup by the machine specific initialisation from the
240 * arch/arm/mach-s3c2410/ directory.
241*/
242
243struct s3c2410_uartcfg {
244 unsigned char hwport; /* hardware port number */
245 unsigned char unused;
246 unsigned short flags;
247 upf_t uart_flags; /* default uart flags */
248 unsigned int clk_sel;
249
250 unsigned int has_fracval;
251
252 unsigned long ucon; /* value of ucon for port */
253 unsigned long ulcon; /* value of ulcon for port */
254 unsigned long ufcon; /* value of ufcon for port */
255};
256
257#endif /* __ASSEMBLY__ */
258
259#endif /* __ASM_ARM_REGS_SERIAL_H */
260
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