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authorSudhakar Rajashekhara <sudhakar.raj@ti.com>2009-04-14 08:53:02 -0400
committerKevin Hilman <khilman@deeprootsystems.com>2009-04-27 12:49:44 -0400
commit9e16469c83167d6869ad6cbe83312027ec529c64 (patch)
treea0763fcea18dc20e9595ee36e79e5e3808e514f8
parentfe277d9bbba9c2851ec11edcd5701f82e034ddd4 (diff)
davinci: DM646x: add interrupt number and priorities
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
-rw-r--r--arch/arm/mach-davinci/include/mach/irqs.h52
-rw-r--r--arch/arm/mach-davinci/irq.c83
2 files changed, 129 insertions, 6 deletions
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index f4c5ca6da9f4..9b0e412ebc28 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -96,10 +96,60 @@
96#define IRQ_EMUINT 63 96#define IRQ_EMUINT 63
97 97
98#define DAVINCI_N_AINTC_IRQ 64 98#define DAVINCI_N_AINTC_IRQ 64
99#define DAVINCI_N_GPIO 71 99#define DAVINCI_N_GPIO 104
100 100
101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) 101#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
102 102
103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 103#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
104 104
105/* DaVinci DM6467-specific Interrupts */
106#define IRQ_DM646X_VP_VERTINT0 0
107#define IRQ_DM646X_VP_VERTINT1 1
108#define IRQ_DM646X_VP_VERTINT2 2
109#define IRQ_DM646X_VP_VERTINT3 3
110#define IRQ_DM646X_VP_ERRINT 4
111#define IRQ_DM646X_RESERVED_1 5
112#define IRQ_DM646X_RESERVED_2 6
113#define IRQ_DM646X_WDINT 7
114#define IRQ_DM646X_CRGENINT0 8
115#define IRQ_DM646X_CRGENINT1 9
116#define IRQ_DM646X_TSIFINT0 10
117#define IRQ_DM646X_TSIFINT1 11
118#define IRQ_DM646X_VDCEINT 12
119#define IRQ_DM646X_USBINT 13
120#define IRQ_DM646X_USBDMAINT 14
121#define IRQ_DM646X_PCIINT 15
122#define IRQ_DM646X_TCERRINT2 20
123#define IRQ_DM646X_TCERRINT3 21
124#define IRQ_DM646X_IDE 22
125#define IRQ_DM646X_HPIINT 23
126#define IRQ_DM646X_EMACRXTHINT 24
127#define IRQ_DM646X_EMACRXINT 25
128#define IRQ_DM646X_EMACTXINT 26
129#define IRQ_DM646X_EMACMISCINT 27
130#define IRQ_DM646X_MCASP0TXINT 28
131#define IRQ_DM646X_MCASP0RXINT 29
132#define IRQ_DM646X_RESERVED_3 31
133#define IRQ_DM646X_MCASP1TXINT 32
134#define IRQ_DM646X_VLQINT 38
135#define IRQ_DM646X_UARTINT2 42
136#define IRQ_DM646X_SPINT0 43
137#define IRQ_DM646X_SPINT1 44
138#define IRQ_DM646X_DSP2ARMINT 45
139#define IRQ_DM646X_RESERVED_4 46
140#define IRQ_DM646X_PSCINT 47
141#define IRQ_DM646X_GPIO0 48
142#define IRQ_DM646X_GPIO1 49
143#define IRQ_DM646X_GPIO2 50
144#define IRQ_DM646X_GPIO3 51
145#define IRQ_DM646X_GPIO4 52
146#define IRQ_DM646X_GPIO5 53
147#define IRQ_DM646X_GPIO6 54
148#define IRQ_DM646X_GPIO7 55
149#define IRQ_DM646X_GPIOBNK0 56
150#define IRQ_DM646X_GPIOBNK1 57
151#define IRQ_DM646X_GPIOBNK2 58
152#define IRQ_DM646X_DDRINT 59
153#define IRQ_DM646X_AEMIFINT 60
154
105#endif /* __ASM_ARCH_IRQS_H */ 155#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index e76835cf1018..cf08ef2945eb 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -25,6 +25,7 @@
25#include <linux/io.h> 25#include <linux/io.h>
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/cputype.h>
28#include <asm/mach/irq.h> 29#include <asm/mach/irq.h>
29 30
30#define IRQ_BIT(irq) ((irq) & 0x1f) 31#define IRQ_BIT(irq) ((irq) & 0x1f)
@@ -40,6 +41,8 @@
40#define IRQ_INTPRI0_REG_OFFSET 0x0030 41#define IRQ_INTPRI0_REG_OFFSET 0x0030
41#define IRQ_INTPRI7_REG_OFFSET 0x004C 42#define IRQ_INTPRI7_REG_OFFSET 0x004C
42 43
44const u8 *davinci_def_priorities;
45
43#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE) 46#define INTC_BASE IO_ADDRESS(DAVINCI_ARM_INTC_BASE)
44 47
45static inline unsigned int davinci_irq_readl(int offset) 48static inline unsigned int davinci_irq_readl(int offset)
@@ -110,9 +113,8 @@ static struct irq_chip davinci_irq_chip_0 = {
110 .unmask = davinci_unmask_irq, 113 .unmask = davinci_unmask_irq,
111}; 114};
112 115
113
114/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */ 116/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
115static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = { 117static const u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
116 [IRQ_VDINT0] = 2, 118 [IRQ_VDINT0] = 2,
117 [IRQ_VDINT1] = 6, 119 [IRQ_VDINT1] = 6,
118 [IRQ_VDINT2] = 6, 120 [IRQ_VDINT2] = 6,
@@ -179,11 +181,82 @@ static const u8 default_priorities[DAVINCI_N_AINTC_IRQ] __initdata = {
179 [IRQ_EMUINT] = 7, 181 [IRQ_EMUINT] = 7,
180}; 182};
181 183
184static const u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
185 [IRQ_DM646X_VP_VERTINT0] = 7,
186 [IRQ_DM646X_VP_VERTINT1] = 7,
187 [IRQ_DM646X_VP_VERTINT2] = 7,
188 [IRQ_DM646X_VP_VERTINT3] = 7,
189 [IRQ_DM646X_VP_ERRINT] = 7,
190 [IRQ_DM646X_RESERVED_1] = 7,
191 [IRQ_DM646X_RESERVED_2] = 7,
192 [IRQ_DM646X_WDINT] = 7,
193 [IRQ_DM646X_CRGENINT0] = 7,
194 [IRQ_DM646X_CRGENINT1] = 7,
195 [IRQ_DM646X_TSIFINT0] = 7,
196 [IRQ_DM646X_TSIFINT1] = 7,
197 [IRQ_DM646X_VDCEINT] = 7,
198 [IRQ_DM646X_USBINT] = 7,
199 [IRQ_DM646X_USBDMAINT] = 7,
200 [IRQ_DM646X_PCIINT] = 7,
201 [IRQ_CCINT0] = 7, /* dma */
202 [IRQ_CCERRINT] = 7, /* dma */
203 [IRQ_TCERRINT0] = 7, /* dma */
204 [IRQ_TCERRINT] = 7, /* dma */
205 [IRQ_DM646X_TCERRINT2] = 7,
206 [IRQ_DM646X_TCERRINT3] = 7,
207 [IRQ_DM646X_IDE] = 7,
208 [IRQ_DM646X_HPIINT] = 7,
209 [IRQ_DM646X_EMACRXTHINT] = 7,
210 [IRQ_DM646X_EMACRXINT] = 7,
211 [IRQ_DM646X_EMACTXINT] = 7,
212 [IRQ_DM646X_EMACMISCINT] = 7,
213 [IRQ_DM646X_MCASP0TXINT] = 7,
214 [IRQ_DM646X_MCASP0RXINT] = 7,
215 [IRQ_AEMIFINT] = 7,
216 [IRQ_DM646X_RESERVED_3] = 7,
217 [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */
218 [IRQ_TINT0_TINT34] = 7, /* clocksource */
219 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
220 [IRQ_TINT1_TINT34] = 7, /* system tick */
221 [IRQ_PWMINT0] = 7,
222 [IRQ_PWMINT1] = 7,
223 [IRQ_DM646X_VLQINT] = 7,
224 [IRQ_I2C] = 7,
225 [IRQ_UARTINT0] = 7,
226 [IRQ_UARTINT1] = 7,
227 [IRQ_DM646X_UARTINT2] = 7,
228 [IRQ_DM646X_SPINT0] = 7,
229 [IRQ_DM646X_SPINT1] = 7,
230 [IRQ_DM646X_DSP2ARMINT] = 7,
231 [IRQ_DM646X_RESERVED_4] = 7,
232 [IRQ_DM646X_PSCINT] = 7,
233 [IRQ_DM646X_GPIO0] = 7,
234 [IRQ_DM646X_GPIO1] = 7,
235 [IRQ_DM646X_GPIO2] = 7,
236 [IRQ_DM646X_GPIO3] = 7,
237 [IRQ_DM646X_GPIO4] = 7,
238 [IRQ_DM646X_GPIO5] = 7,
239 [IRQ_DM646X_GPIO6] = 7,
240 [IRQ_DM646X_GPIO7] = 7,
241 [IRQ_DM646X_GPIOBNK0] = 7,
242 [IRQ_DM646X_GPIOBNK1] = 7,
243 [IRQ_DM646X_GPIOBNK2] = 7,
244 [IRQ_DM646X_DDRINT] = 7,
245 [IRQ_DM646X_AEMIFINT] = 7,
246 [IRQ_COMMTX] = 7,
247 [IRQ_COMMRX] = 7,
248 [IRQ_EMUINT] = 7,
249};
250
182/* ARM Interrupt Controller Initialization */ 251/* ARM Interrupt Controller Initialization */
183void __init davinci_irq_init(void) 252void __init davinci_irq_init(void)
184{ 253{
185 unsigned i; 254 unsigned i;
186 const u8 *priority = default_priorities; 255
256 if (cpu_is_davinci_dm644x())
257 davinci_def_priorities = dm644x_default_priorities;
258 else if (cpu_is_davinci_dm646x())
259 davinci_def_priorities = dm646x_default_priorities;
187 260
188 /* Clear all interrupt requests */ 261 /* Clear all interrupt requests */
189 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); 262 davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
@@ -211,8 +284,8 @@ void __init davinci_irq_init(void)
211 unsigned j; 284 unsigned j;
212 u32 pri; 285 u32 pri;
213 286
214 for (j = 0, pri = 0; j < 32; j += 4, priority++) 287 for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
215 pri |= (*priority & 0x07) << j; 288 pri |= (*davinci_def_priorities & 0x07) << j;
216 davinci_irq_writel(pri, i); 289 davinci_irq_writel(pri, i);
217 } 290 }
218 291