arm: zynq: Do not use xilinx specific function names

Remove all xilinx specific names from the driver
because this is generic driver for cadence ttc.
xttc->ttc
ttcps->ttc
...

No functional changes in this driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

1 files changed, 106 insertions, 106 deletions

diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
index ab5b839e22f0..685bc60e210a 100644
--- a/arch/arm/mach-zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -1,5 +1,5 @@
 /*
- * This file contains driver for the Xilinx PS Timer Counter IP.
+ * This file contains driver for the Cadence Triple Timer Counter Rev 06
  *
  *  Copyright (C) 2011-2013 Xilinx
  *
@@ -42,14 +42,14 @@
  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
  * and use same offsets for Timer 2
  */
-#define XTTCPS_CLK_CNTRL_OFFSET         0x00 /* Clock Control Reg, RW */
-#define XTTCPS_CNT_CNTRL_OFFSET         0x0C /* Counter Control Reg, RW */
-#define XTTCPS_COUNT_VAL_OFFSET         0x18 /* Counter Value Reg, RO */
-#define XTTCPS_INTR_VAL_OFFSET          0x24 /* Interval Count Reg, RW */
-#define XTTCPS_ISR_OFFSET               0x54 /* Interrupt Status Reg, RO */
-#define XTTCPS_IER_OFFSET               0x60 /* Interrupt Enable Reg, RW */
+#define TTC_CLK_CNTRL_OFFSET            0x00 /* Clock Control Reg, RW */
+#define TTC_CNT_CNTRL_OFFSET            0x0C /* Counter Control Reg, RW */
+#define TTC_COUNT_VAL_OFFSET            0x18 /* Counter Value Reg, RO */
+#define TTC_INTR_VAL_OFFSET             0x24 /* Interval Count Reg, RW */
+#define TTC_ISR_OFFSET          0x54 /* Interrupt Status Reg, RO */
+#define TTC_IER_OFFSET          0x60 /* Interrupt Enable Reg, RW */
 
-#define XTTCPS_CNT_CNTRL_DISABLE_MASK   0x1
+#define TTC_CNT_CNTRL_DISABLE_MASK      0x1
 
 /*
  * Setup the timers to use pre-scaling, using a fixed value for now that will
@@ -62,161 +62,161 @@
 #define CNT_CNTRL_RESET         (1 << 4)
 
 /**
- * struct xttcps_timer - This definition defines local timer structure
+ * struct ttc_timer - This definition defines local timer structure
  *
  * @base_addr:  Base address of timer
  * @clk:        Associated clock source
  * @clk_rate_change_nb  Notifier block for clock rate changes
  */
-struct xttcps_timer {
+struct ttc_timer {
         void __iomem *base_addr;
         struct clk *clk;
         struct notifier_block clk_rate_change_nb;
 };
 
-#define to_xttcps_timer(x) \
-                container_of(x, struct xttcps_timer, clk_rate_change_nb)
+#define to_ttc_timer(x) \
+                container_of(x, struct ttc_timer, clk_rate_change_nb)
 
-struct xttcps_timer_clocksource {
-        struct xttcps_timer     xttc;
+struct ttc_timer_clocksource {
+        struct ttc_timer        ttc;
         struct clocksource      cs;
 };
 
-#define to_xttcps_timer_clksrc(x) \
-                container_of(x, struct xttcps_timer_clocksource, cs)
+#define to_ttc_timer_clksrc(x) \
+                container_of(x, struct ttc_timer_clocksource, cs)
 
-struct xttcps_timer_clockevent {
-        struct xttcps_timer             xttc;
+struct ttc_timer_clockevent {
+        struct ttc_timer                ttc;
         struct clock_event_device       ce;
 };
 
-#define to_xttcps_timer_clkevent(x) \
-                container_of(x, struct xttcps_timer_clockevent, ce)
+#define to_ttc_timer_clkevent(x) \
+                container_of(x, struct ttc_timer_clockevent, ce)
 
 /**
- * xttcps_set_interval - Set the timer interval value
+ * ttc_set_interval - Set the timer interval value
  *
  * @timer:      Pointer to the timer instance
  * @cycles:     Timer interval ticks
  **/
-static void xttcps_set_interval(struct xttcps_timer *timer,
+static void ttc_set_interval(struct ttc_timer *timer,
                                         unsigned long cycles)
 {
         u32 ctrl_reg;
 
         /* Disable the counter, set the counter value  and re-enable counter */
-        ctrl_reg = __raw_readl(timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
-        ctrl_reg |= XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
+        ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
+        ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
+        __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 
-        __raw_writel(cycles, timer->base_addr + XTTCPS_INTR_VAL_OFFSET);
+        __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
 
         /*
          * Reset the counter (0x10) so that it starts from 0, one-shot
          * mode makes this needed for timing to be right.
          */
         ctrl_reg |= CNT_CNTRL_RESET;
-        ctrl_reg &= ~XTTCPS_CNT_CNTRL_DISABLE_MASK;
-        __raw_writel(ctrl_reg, timer->base_addr + XTTCPS_CNT_CNTRL_OFFSET);
+        ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
+        __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
 }
 
 /**
- * xttcps_clock_event_interrupt - Clock event timer interrupt handler
+ * ttc_clock_event_interrupt - Clock event timer interrupt handler
  *
  * @irq:        IRQ number of the Timer
- * @dev_id:     void pointer to the xttcps_timer instance
+ * @dev_id:     void pointer to the ttc_timer instance
  *
  * returns: Always IRQ_HANDLED - success
  **/
-static irqreturn_t xttcps_clock_event_interrupt(int irq, void *dev_id)
+static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
 {
-        struct xttcps_timer_clockevent *xttce = dev_id;
-        struct xttcps_timer *timer = &xttce->xttc;
+        struct ttc_timer_clockevent *ttce = dev_id;
+        struct ttc_timer *timer = &ttce->ttc;
 
         /* Acknowledge the interrupt and call event handler */
-        __raw_readl(timer->base_addr + XTTCPS_ISR_OFFSET);
+        __raw_readl(timer->base_addr + TTC_ISR_OFFSET);
 
-        xttce->ce.event_handler(&xttce->ce);
+        ttce->ce.event_handler(&ttce->ce);
 
         return IRQ_HANDLED;
 }
 
 /**
- * __xttc_clocksource_read - Reads the timer counter register
+ * __ttc_clocksource_read - Reads the timer counter register
  *
  * returns: Current timer counter register value
  **/
-static cycle_t __xttc_clocksource_read(struct clocksource *cs)
+static cycle_t __ttc_clocksource_read(struct clocksource *cs)
 {
-        struct xttcps_timer *timer = &to_xttcps_timer_clksrc(cs)->xttc;
+        struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
 
         return (cycle_t)__raw_readl(timer->base_addr +
-                                XTTCPS_COUNT_VAL_OFFSET);
+                                TTC_COUNT_VAL_OFFSET);
 }
 
 /**
- * xttcps_set_next_event - Sets the time interval for next event
+ * ttc_set_next_event - Sets the time interval for next event
  *
  * @cycles:     Timer interval ticks
  * @evt:        Address of clock event instance