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authorMarkos Chandras <markos.chandras@imgtec.com>2013-12-19 11:41:05 -0500
committerRalf Baechle <ralf@linux-mips.org>2014-03-26 18:09:16 -0400
commit9d8e573683ca85e2bd3cade8b5c42e195e6390ad (patch)
treee235e9f1c040dae06aff6d9d55e9388cf6508376
parente3a9b07a9caf4e490eee2c0645530cdc80a685f2 (diff)
MIPS: kernel: unaligned: Add EVA instruction wrappers
Use the load/store instruction wrappers from asm/asm.h to perform such operations when operating in EVA mode. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat
-rw-r--r--arch/mips/kernel/unaligned.c49
1 files changed, 25 insertions, 24 deletions
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index c369a5d35527..5ec8f00b51b5 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -7,6 +7,7 @@
7 * 7 *
8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle 8 * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
9 * Copyright (C) 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2014 Imagination Technologies Ltd.
10 * 11 *
11 * This file contains exception handler for address error exception with the 12 * This file contains exception handler for address error exception with the
12 * special capability to execute faulting instructions in software. The 13 * special capability to execute faulting instructions in software. The
@@ -110,8 +111,8 @@ extern void show_registers(struct pt_regs *regs);
110#ifdef __BIG_ENDIAN 111#ifdef __BIG_ENDIAN
111#define LoadHW(addr, value, res) \ 112#define LoadHW(addr, value, res) \
112 __asm__ __volatile__ (".set\tnoat\n" \ 113 __asm__ __volatile__ (".set\tnoat\n" \
113 "1:\tlb\t%0, 0(%2)\n" \ 114 "1:\t"user_lb("%0", "0(%2)")"\n" \
114 "2:\tlbu\t$1, 1(%2)\n\t" \ 115 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \
115 "sll\t%0, 0x8\n\t" \ 116 "sll\t%0, 0x8\n\t" \
116 "or\t%0, $1\n\t" \ 117 "or\t%0, $1\n\t" \
117 "li\t%1, 0\n" \ 118 "li\t%1, 0\n" \
@@ -130,8 +131,8 @@ extern void show_registers(struct pt_regs *regs);
130 131
131#define LoadW(addr, value, res) \ 132#define LoadW(addr, value, res) \
132 __asm__ __volatile__ ( \ 133 __asm__ __volatile__ ( \
133 "1:\tlwl\t%0, (%2)\n" \ 134 "1:\t"user_lwl("%0", "(%2)")"\n" \
134 "2:\tlwr\t%0, 3(%2)\n\t" \ 135 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \
135 "li\t%1, 0\n" \ 136 "li\t%1, 0\n" \
136 "3:\n\t" \ 137 "3:\n\t" \
137 ".insn\n\t" \ 138 ".insn\n\t" \
@@ -149,8 +150,8 @@ extern void show_registers(struct pt_regs *regs);
149#define LoadHWU(addr, value, res) \ 150#define LoadHWU(addr, value, res) \
150 __asm__ __volatile__ ( \ 151 __asm__ __volatile__ ( \
151 ".set\tnoat\n" \ 152 ".set\tnoat\n" \
152 "1:\tlbu\t%0, 0(%2)\n" \ 153 "1:\t"user_lbu("%0", "0(%2)")"\n" \
153 "2:\tlbu\t$1, 1(%2)\n\t" \ 154 "2:\t"user_lbu("$1", "1(%2)")"\n\t" \
154 "sll\t%0, 0x8\n\t" \ 155 "sll\t%0, 0x8\n\t" \
155 "or\t%0, $1\n\t" \ 156 "or\t%0, $1\n\t" \
156 "li\t%1, 0\n" \ 157 "li\t%1, 0\n" \
@@ -170,8 +171,8 @@ extern void show_registers(struct pt_regs *regs);
170 171
171#define LoadWU(addr, value, res) \ 172#define LoadWU(addr, value, res) \
172 __asm__ __volatile__ ( \ 173 __asm__ __volatile__ ( \
173 "1:\tlwl\t%0, (%2)\n" \ 174 "1:\t"user_lwl("%0", "(%2)")"\n" \
174 "2:\tlwr\t%0, 3(%2)\n\t" \ 175 "2:\t"user_lwr("%0", "3(%2)")"\n\t" \
175 "dsll\t%0, %0, 32\n\t" \ 176 "dsll\t%0, %0, 32\n\t" \
176 "dsrl\t%0, %0, 32\n\t" \ 177 "dsrl\t%0, %0, 32\n\t" \
177 "li\t%1, 0\n" \ 178 "li\t%1, 0\n" \
@@ -209,9 +210,9 @@ extern void show_registers(struct pt_regs *regs);
209#define StoreHW(addr, value, res) \ 210#define StoreHW(addr, value, res) \
210 __asm__ __volatile__ ( \ 211 __asm__ __volatile__ ( \
211 ".set\tnoat\n" \ 212 ".set\tnoat\n" \
212 "1:\tsb\t%1, 1(%2)\n\t" \ 213 "1:\t"user_sb("%1", "1(%2)")"\n" \
213 "srl\t$1, %1, 0x8\n" \ 214 "srl\t$1, %1, 0x8\n" \
214 "2:\tsb\t$1, 0(%2)\n\t" \ 215 "2:\t"user_sb("$1", "0(%2)")"\n" \
215 ".set\tat\n\t" \ 216 ".set\tat\n\t" \
216 "li\t%0, 0\n" \ 217 "li\t%0, 0\n" \
217 "3:\n\t" \ 218 "3:\n\t" \
@@ -229,8 +230,8 @@ extern void show_registers(struct pt_regs *regs);
229 230
230#define StoreW(addr, value, res) \ 231#define StoreW(addr, value, res) \
231 __asm__ __volatile__ ( \ 232 __asm__ __volatile__ ( \
232 "1:\tswl\t%1,(%2)\n" \ 233 "1:\t"user_swl("%1", "(%2)")"\n" \
233 "2:\tswr\t%1, 3(%2)\n\t" \ 234 "2:\t"user_swr("%1", "3(%2)")"\n\t" \
234 "li\t%0, 0\n" \ 235 "li\t%0, 0\n" \
235 "3:\n\t" \ 236 "3:\n\t" \
236 ".insn\n\t" \ 237 ".insn\n\t" \
@@ -267,8 +268,8 @@ extern void show_registers(struct pt_regs *regs);
267#ifdef __LITTLE_ENDIAN 268#ifdef __LITTLE_ENDIAN
268#define LoadHW(addr, value, res) \ 269#define LoadHW(addr, value, res) \
269 __asm__ __volatile__ (".set\tnoat\n" \ 270 __asm__ __volatile__ (".set\tnoat\n" \
270 "1:\tlb\t%0, 1(%2)\n" \ 271 "1:\t"user_lb("%0", "1(%2)")"\n" \
271 "2:\tlbu\t$1, 0(%2)\n\t" \ 272 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \
272 "sll\t%0, 0x8\n\t" \ 273 "sll\t%0, 0x8\n\t" \
273 "or\t%0, $1\n\t" \ 274 "or\t%0, $1\n\t" \
274 "li\t%1, 0\n" \ 275 "li\t%1, 0\n" \
@@ -287,8 +288,8 @@ extern void show_registers(struct pt_regs *regs);
287 288
288#define LoadW(addr, value, res) \ 289#define LoadW(addr, value, res) \
289 __asm__ __volatile__ ( \ 290 __asm__ __volatile__ ( \
290 "1:\tlwl\t%0, 3(%2)\n" \ 291 "1:\t"user_lwl("%0", "3(%2)")"\n" \
291 "2:\tlwr\t%0, (%2)\n\t" \ 292 "2:\t"user_lwr("%0", "(%2)")"\n\t" \
292 "li\t%1, 0\n" \ 293 "li\t%1, 0\n" \
293 "3:\n\t" \ 294 "3:\n\t" \
294 ".insn\n\t" \ 295 ".insn\n\t" \
@@ -306,8 +307,8 @@ extern void show_registers(struct pt_regs *regs);
306#define LoadHWU(addr, value, res) \ 307#define LoadHWU(addr, value, res) \
307 __asm__ __volatile__ ( \ 308 __asm__ __volatile__ ( \
308 ".set\tnoat\n" \ 309 ".set\tnoat\n" \
309 "1:\tlbu\t%0, 1(%2)\n" \ 310 "1:\t"user_lbu("%0", "1(%2)")"\n" \
310 "2:\tlbu\t$1, 0(%2)\n\t" \ 311 "2:\t"user_lbu("$1", "0(%2)")"\n\t" \
311 "sll\t%0, 0x8\n\t" \ 312 "sll\t%0, 0x8\n\t" \
312 "or\t%0, $1\n\t" \ 313 "or\t%0, $1\n\t" \
313 "li\t%1, 0\n" \ 314 "li\t%1, 0\n" \
@@ -327,8 +328,8 @@ extern void show_registers(struct pt_regs *regs);
327 328
328#define LoadWU(addr, value, res) \ 329#define LoadWU(addr, value, res) \
329 __asm__ __volatile__ ( \ 330 __asm__ __volatile__ ( \
330 "1:\tlwl\t%0, 3(%2)\n" \ 331 "1:\t"user_lwl("%0", "3(%2)")"\n" \
331 "2:\tlwr\t%0, (%2)\n\t" \ 332 "2:\t"user_lwr("%0", "(%2)")"\n\t" \
332 "dsll\t%0, %0, 32\n\t" \ 333 "dsll\t%0, %0, 32\n\t" \
333 "dsrl\t%0, %0, 32\n\t" \ 334 "dsrl\t%0, %0, 32\n\t" \
334 "li\t%1, 0\n" \ 335 "li\t%1, 0\n" \
@@ -366,9 +367,9 @@ extern void show_registers(struct pt_regs *regs);
366#define StoreHW(addr, value, res) \ 367#define StoreHW(addr, value, res) \
367 __asm__ __volatile__ ( \ 368 __asm__ __volatile__ ( \
368 ".set\tnoat\n" \ 369 ".set\tnoat\n" \
369 "1:\tsb\t%1, 0(%2)\n\t" \ 370 "1:\t"user_sb("%1", "0(%2)")"\n" \
370 "srl\t$1,%1, 0x8\n" \ 371 "srl\t$1,%1, 0x8\n" \
371 "2:\tsb\t$1, 1(%2)\n\t" \ 372 "2:\t"user_sb("$1", "1(%2)")"\n" \
372 ".set\tat\n\t" \ 373 ".set\tat\n\t" \
373 "li\t%0, 0\n" \ 374 "li\t%0, 0\n" \
374 "3:\n\t" \ 375 "3:\n\t" \
@@ -386,8 +387,8 @@ extern void show_registers(struct pt_regs *regs);
386 387
387#define StoreW(addr, value, res) \ 388#define StoreW(addr, value, res) \
388 __asm__ __volatile__ ( \ 389 __asm__ __volatile__ ( \
389 "1:\tswl\t%1, 3(%2)\n" \ 390 "1:\t"user_swl("%1", "3(%2)")"\n" \
390 "2:\tswr\t%1, (%2)\n\t" \ 391 "2:\t"user_swr("%1", "(%2)")"\n\t" \
391 "li\t%0, 0\n" \ 392 "li\t%0, 0\n" \
392 "3:\n\t" \ 393 "3:\n\t" \
393 ".insn\n\t" \ 394 ".insn\n\t" \
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