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authorShawn Guo <shawn.guo@linaro.org>2013-10-17 03:19:45 -0400
committerChris Ball <chris@printf.net>2013-10-21 15:57:48 -0400
commit9d61c0092ca1abe93853d1b8dfeb5525b6cf3ddc (patch)
tree589c347da2011f8a2aa725e1de41739451a611fb
parent31fbb3013506e58320fcea2ce07543b2a22c5ee0 (diff)
mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_USDHC
Add flag ESDHC_FLAG_USDHC to tell that the ESDHC is actually an USDHC block, and replace the is_imx6q_usdhc() occurrences with inline function esdhc_is_usdhc() which checks the flag. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Chris Ball <cjb@laptop.org>
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c37
1 files changed, 25 insertions, 12 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index d844be862cfa..2421ac7fa6bf 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -89,6 +89,11 @@
89 * affects i.MX25 and i.MX35. 89 * affects i.MX25 and i.MX35.
90 */ 90 */
91#define ESDHC_FLAG_ENGCM07207 BIT(2) 91#define ESDHC_FLAG_ENGCM07207 BIT(2)
92/*
93 * The flag tells that the ESDHC controller is an USDHC block that is
94 * integrated on the i.MX6 series.
95 */
96#define ESDHC_FLAG_USDHC BIT(3)
92 97
93enum imx_esdhc_type { 98enum imx_esdhc_type {
94 IMX25_ESDHC, 99 IMX25_ESDHC,
@@ -175,6 +180,11 @@ static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
175 return data->devtype == IMX6Q_USDHC; 180 return data->devtype == IMX6Q_USDHC;
176} 181}
177 182
183static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
184{
185 return !!(data->flags & ESDHC_FLAG_USDHC);
186}
187
178static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 188static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
179{ 189{
180 void __iomem *base = host->ioaddr + (reg & ~0x3); 190 void __iomem *base = host->ioaddr + (reg & ~0x3);
@@ -213,11 +223,11 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
213 } 223 }
214 } 224 }
215 225
216 if (unlikely(reg == SDHCI_CAPABILITIES_1) && is_imx6q_usdhc(imx_data)) 226 if (unlikely(reg == SDHCI_CAPABILITIES_1) && esdhc_is_usdhc(imx_data))
217 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 227 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
218 | SDHCI_SUPPORT_SDR50; 228 | SDHCI_SUPPORT_SDR50;
219 229
220 if (unlikely(reg == SDHCI_MAX_CURRENT) && is_imx6q_usdhc(imx_data)) { 230 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
221 val = 0; 231 val = 0;
222 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 232 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
223 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 233 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
@@ -307,7 +317,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
307 317
308 if (unlikely(reg == SDHCI_HOST_VERSION)) { 318 if (unlikely(reg == SDHCI_HOST_VERSION)) {
309 reg ^= 2; 319 reg ^= 2;
310 if (is_imx6q_usdhc(imx_data)) { 320 if (esdhc_is_usdhc(imx_data)) {
311 /* 321 /*
312 * The usdhc register returns a wrong host version. 322 * The usdhc register returns a wrong host version.
313 * Correct it here. 323 * Correct it here.
@@ -321,7 +331,7 @@ static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
321 if (val & ESDHC_VENDOR_SPEC_VSELECT) 331 if (val & ESDHC_VENDOR_SPEC_VSELECT)
322 ret |= SDHCI_CTRL_VDD_180; 332 ret |= SDHCI_CTRL_VDD_180;
323 333
324 if (is_imx6q_usdhc(imx_data)) { 334 if (esdhc_is_usdhc(imx_data)) {
325 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 335 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
326 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 336 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
327 ret |= SDHCI_CTRL_EXEC_TUNING; 337 ret |= SDHCI_CTRL_EXEC_TUNING;
@@ -379,7 +389,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
379 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 389 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
380 } 390 }
381 391
382 if (is_imx6q_usdhc(imx_data)) { 392 if (esdhc_is_usdhc(imx_data)) {
383 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 393 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
384 /* Swap AC23 bit */ 394 /* Swap AC23 bit */
385 if (val & SDHCI_TRNS_AUTO_CMD23) { 395 if (val & SDHCI_TRNS_AUTO_CMD23) {
@@ -404,7 +414,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
404 (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 414 (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
405 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 415 imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
406 416
407 if (is_imx6q_usdhc(imx_data)) 417 if (esdhc_is_usdhc(imx_data))
408 writel(val << 16, 418 writel(val << 16,
409 host->ioaddr + SDHCI_TRANSFER_MODE); 419 host->ioaddr + SDHCI_TRANSFER_MODE);
410 else 420 else
@@ -470,7 +480,7 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
470 * The reset on usdhc fails to clear MIX_CTRL register. 480 * The reset on usdhc fails to clear MIX_CTRL register.
471 * Do it manually here. 481 * Do it manually here.
472 */ 482 */
473 if (is_imx6q_usdhc(imx_data)) 483 if (esdhc_is_usdhc(imx_data))
474 writel(0, host->ioaddr + ESDHC_MIX_CTRL); 484 writel(0, host->ioaddr + ESDHC_MIX_CTRL);
475 } 485 }
476} 486}
@@ -507,7 +517,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
507 u32 temp, val; 517 u32 temp, val;
508 518
509 if (clock == 0) { 519 if (clock == 0) {
510 if (is_imx6q_usdhc(imx_data)) { 520 if (esdhc_is_usdhc(imx_data)) {
511 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 521 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
512 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 522 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
513 host->ioaddr + ESDHC_VENDOR_SPEC); 523 host->ioaddr + ESDHC_VENDOR_SPEC);
@@ -515,7 +525,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
515 goto out; 525 goto out;
516 } 526 }
517 527
518 if (is_imx6q_usdhc(imx_data)) 528 if (esdhc_is_usdhc(imx_data))
519 pre_div = 1; 529 pre_div = 1;
520 530
521 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 531 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
@@ -542,7 +552,7 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
542 | (pre_div << ESDHC_PREDIV_SHIFT)); 552 | (pre_div << ESDHC_PREDIV_SHIFT));
543 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 553 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
544 554
545 if (is_imx6q_usdhc(imx_data)) { 555 if (esdhc_is_usdhc(imx_data)) {
546 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 556 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
547 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 557 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
548 host->ioaddr + ESDHC_VENDOR_SPEC); 558 host->ioaddr + ESDHC_VENDOR_SPEC);
@@ -865,6 +875,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
865 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 875 if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
866 imx_data->flags |= ESDHC_FLAG_ENGCM07207; 876 imx_data->flags |= ESDHC_FLAG_ENGCM07207;
867 877
878 if (is_imx6q_usdhc(imx_data))
879 imx_data->flags |= ESDHC_FLAG_USDHC;
880
868 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 881 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
869 if (IS_ERR(imx_data->clk_ipg)) { 882 if (IS_ERR(imx_data->clk_ipg)) {
870 err = PTR_ERR(imx_data->clk_ipg); 883 err = PTR_ERR(imx_data->clk_ipg);
@@ -917,7 +930,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
917 * The imx6q ROM code will change the default watermark level setting 930 * The imx6q ROM code will change the default watermark level setting
918 * to something insane. Change it back here. 931 * to something insane. Change it back here.
919 */ 932 */
920 if (is_imx6q_usdhc(imx_data)) 933 if (esdhc_is_usdhc(imx_data))
921 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 934 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
922 935
923 boarddata = &imx_data->boarddata; 936 boarddata = &imx_data->boarddata;
@@ -980,7 +993,7 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
980 } 993 }
981 994
982 /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 995 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
983 if ((boarddata->support_vsel) && is_imx6q_usdhc(imx_data)) { 996 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
984 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 997 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
985 ESDHC_PINCTRL_STATE_100MHZ); 998 ESDHC_PINCTRL_STATE_100MHZ);
986 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 999 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,