drm/i915: Fix gen2 planes B and C max watermark value

The max watermark value for gen2 planes B and C is 0x1f, instead of
the 0x3f that plane A uses.

Also check against the max even if the pipe is disabled since the
FIFO size exceeds the plane B and C max watermark value.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Thomas Richter <richter@rus.uni-stuttgart.de>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 20 insertions, 4 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 376cc2c8751a..38b61e4d17ae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1001,13 +1001,20 @@ static const struct intel_watermark_params i915_wm_info = {
         .guard_size = 2,
         .cacheline_size = I915_FIFO_LINE_SIZE,
 };
-static const struct intel_watermark_params i830_wm_info = {
+static const struct intel_watermark_params i830_a_wm_info = {
         .fifo_size = I855GM_FIFO_SIZE,
         .max_wm = I915_MAX_WM,
         .default_wm = 1,
         .guard_size = 2,
         .cacheline_size = I830_FIFO_LINE_SIZE,
 };
+static const struct intel_watermark_params i830_bc_wm_info = {
+        .fifo_size = I855GM_FIFO_SIZE,
+        .max_wm = I915_MAX_WM/2,
+        .default_wm = 1,
+        .guard_size = 2,
+        .cacheline_size = I830_FIFO_LINE_SIZE,
+};
 static const struct intel_watermark_params i845_wm_info = {
         .fifo_size = I830_FIFO_SIZE,
         .max_wm = I915_MAX_WM,
@@ -1689,7 +1696,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
         else if (!IS_GEN2(dev))
                 wm_info = &i915_wm_info;
         else
-                wm_info = &i830_wm_info;
+                wm_info = &i830_a_wm_info;
 
         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
         crtc = intel_get_crtc_for_plane(dev, 0);
@@ -1704,8 +1711,14 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
                                                wm_info, fifo_size, cpp,
                                                latency_ns);
                 enabled = crtc;
-        } else
+        } else {
                 planea_wm = fifo_size - wm_info->guard_size;
+                if (planea_wm > (long)wm_info->max_wm)
+                        planea_wm = wm_info->max_wm;
+        }
+
+        if (IS_GEN2(dev))
+                wm_info = &i830_bc_wm_info;
 
         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
         crtc = intel_get_crtc_for_plane(dev, 1);
@@ -1723,8 +1736,11 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
                         enabled = crtc;
                 else
                         enabled = NULL;
-        } else
+        } else {
                 planeb_wm = fifo_size - wm_info->guard_size;
+                if (planeb_wm > (long)wm_info->max_wm)
+                        planeb_wm = wm_info->max_wm;
+        }
 
         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);